CN114582400B - Fast and low power word line driver circuit for NOR Flash - Google Patents
Fast and low power word line driver circuit for NOR Flash Download PDFInfo
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- CN114582400B CN114582400B CN202210166346.3A CN202210166346A CN114582400B CN 114582400 B CN114582400 B CN 114582400B CN 202210166346 A CN202210166346 A CN 202210166346A CN 114582400 B CN114582400 B CN 114582400B
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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Abstract
The invention discloses a fast low-power consumption word line driving circuit applied to NOR Flash, which comprises a working mode and a standby mode. The working mode comprises a charge pump power stage formed by a cross-coupled charge pump, and a dynamic frequency modulation voltage stabilizing circuit formed by a non-overlapping clock generating circuit, a voltage-controlled oscillator, an error amplifier and a resistor voltage divider. The standby mode comprises a charge pump power stage formed by a Dickson charge pump, and a SKIP modulation voltage stabilizing circuit formed by a non-overlapping clock generator, a current starvation oscillator, a hysteresis comparator, a down counter, an inverter, a NOR gate, a capacitive voltage divider and a VD point refreshing circuit. In addition, an ultra-low power consumption voltage reference source continuously provides reference voltages in two modes, and the NMOS device M5 and the output load capacitor Cout which are connected in a diode mode form a low-pass filter to optimize output voltage ripple. The invention can realize rapid and high-efficiency boost in the working mode, stably output with low ripple wave, and simultaneously maintain the required voltage with low power consumption in the standby mode.
Description
Technical Field
The invention relates to the technical field of semiconductor memories, in particular to a fast low-power consumption word line driving circuit applied to NOR Flash.
Background
Memory has been continually drawing attention in recent years as the best-incoiporated device class for the global semiconductor industry. As one of the Flash memory classes, NOR Flash is widely used in fields such as automotive electronics, smart wear, mobile phone display, and internet of things due to its fast access speed, and in particular in the field of high-reliability memory chips requiring vehicle-level authentication, NOR Flash has irreplaceable value.
The read, write and erase operations of the Flash memory all need to apply various different operation voltages to each port, and only a unified power supply voltage is provided outside the memory, so that a boost circuit is needed inside the chip.
The NOR Flash has the characteristic of quick access, so that word line voltage needs to be quickly established by a boost circuit to be met, ripple waves of output voltage are also noise performance for loads, the load circuit cannot work normally due to the fact that the ripple waves are large, erasing and programming of a memory cell are affected by the large voltage ripple waves for a Flash device, threshold voltage of a floating gate transistor deviates from an expected value, and accordingly data access errors are caused.
Besides the charge pump boosting system for each operation of the NOR Flash, the NOR Flash needs to meet the special requirements of maintaining the required voltage and reducing the power consumption of the chip on the premise of fast random reading time, which is a problem to be solved in the NOR Flash standby mode.
For the traditional word line driving circuit, the working mode and the standby mode are realized by adopting the same type of charge pump and the same type of voltage stabilizing system. In fact, the requirements for the word line driving circuit in the two modes are different, namely, in the operating mode, an output voltage which needs to be quickly boosted and has low ripple stability is required for the read, write and erase operations of the memory, and in the standby mode, the required voltage needs to be maintained and low power consumption is required. The charge pump type and voltage regulation system used by conventional word line driving circuits in the operation mode is very difficult when higher circuit performance requirements are to be met, and standby power consumption in the standby mode is high.
Disclosure of Invention
In order to enable the word line driving circuit to achieve higher performance index requirements in both an operating mode and a standby mode, the invention aims to provide a fast low-power-consumption word line driving circuit applied to NOR Flash.
A fast low-power consumption word line driving circuit applied to NOR Flash comprises two modes, namely an operating mode and a standby mode;
the circuit in the working mode comprises:
an operating mode charge pump power stage comprising a cross-coupled charge pump for generating a high voltage;
The dynamic frequency modulation voltage stabilizing circuit sequentially comprises a voltage-controlled oscillator, a non-overlapping clock generating circuit module, an error amplifier EA and resistor voltage dividers R1 and R2, and is used for outputting high voltage generated by a charge pump stably and with low ripple waves under all PVT (process, voltage and temperature);
an ultra-low power consumption voltage reference source for providing a reference voltage VREF for the error amplifier EA;
The NMOS device M1 is used as a switching tube and is controlled by a signal ACT_EN for triggering an operating mode, and the NMOS device M5 can form a low-pass filter with a load capacitor Cout and is used for effectively inhibiting output voltage ripple;
the circuit in standby mode comprises:
a standby mode charge pump power stage comprising DICKSON charge pumps for generating high voltages;
the SKIP modulation voltage stabilizing circuit sequentially comprises a current starving oscillator, a non-overlapping clock generating circuit, a hysteresis comparator, a down counter, an inverter module, a NOR gate, a capacitor voltage divider and a refreshing circuit of a connecting point VD of the capacitor voltage divider C1 and C2, and is used for maintaining output voltage in a standby mode;
an ultra-low power consumption voltage reference source for providing a reference voltage VREF for the hysteresis comparator COM and providing a bias voltage VBIAS for the current starvation oscillator;
An NMOS device M2 as a switching transistor controlled by a signal ACT_ENB for standby mode triggering;
The down counter counts the charging time of the charge pump in each standby mode, and continuously works before the down counter counts to 0 so as to avoid overshoot of the output voltage;
the inverter module comprises inverters INV 1-INV 3, wherein INV1 and INV2 are used for rectifying an output signal of the hysteresis comparator COM, and INV3 is used for inverting an output signal of the subtracter to generate ENPD signals;
the nor gate is used for generating a standby mode enable signal stb_en under the control of the signal ENPD and the signal act_en to control the current starving oscillator and the DICKSON charge pump;
The refresh circuit of the connection point VD of the capacitors C1 and C2 sequentially comprises an NMOS device M3 controlled by the enable signal act_en, a PMOS device M4 controlled by the enable signal act_enb, and resistors R3 and R4, which are used for providing an initial voltage for the connection point VD, and refreshing the connection point VD when the two modes are switched.
The cross-coupled charge pump in the operating mode is provided with a pre-charge tube to optimize the rise time and a substrate modulation tube to suppress reverse leakage current.
The ultra-low power consumption voltage reference source adopts a non-resistance full MOS tube structure, an NMOS device in a deep triode region is used for replacing a resistor, and other MOS devices are in a subthreshold region, so that nW-level power consumption is realized.
The MOS devices in the current starvation oscillator and the hysteresis comparator in the standby mode circuit work in a subthreshold area, the static power consumption is low, and the static current is in the nA level.
The NMOS device M5 is diode-connected, and uses a low threshold NMOS device to reduce the threshold voltage loss of the output voltage.
The PMOS device, the NMOS device, the MOS device and the switch MOS transistor are all metal oxide semiconductor MOS transistors.
Compared with the prior art, the invention has the following beneficial technical effects:
In the working mode, a cross-coupling charge pump which has small ripple and high efficiency and is suitable for a low-voltage process is adopted as a charge pump power stage, a pre-charging tube and a substrate modulation tube are added on the basis of the original cross-coupling charge pump structure to optimize rising time and inhibit reverse leakage current respectively, and meanwhile, a dynamic frequency modulation voltage stabilizing circuit which has small ripple, high efficiency and higher design complexity is adopted to realize stable output of output voltage under different PVT (process, voltage and temperature).
In the standby mode, a Dickson charge pump with a simple structure, low power consumption and low efficiency is still used as a charge pump power stage, and meanwhile, an SKIP modulation voltage stabilizing circuit with a simple structure is used for stabilizing output voltage, and the charging time of the charge pump in each standby mode is controlled to avoid overshoot by counting through a down counter. In addition, the hysteresis comparator in the standby mode and the MOS device in the current starvation type oscillator are in the subthreshold region, the traditional resistor divider serving as a feedback network is replaced by a capacitive divider, and standby power consumption is further reduced through the measures.
Drawings
Fig. 1 is a schematic diagram of a conventional word line driving circuit.
FIG. 2 is a schematic diagram of a fast low power word line driving circuit in accordance with the present invention.
FIG. 3 is a timing waveform diagram of a word line driver system according to the present invention.
FIG. 4 is a schematic diagram of an optimized single stage cross-coupled charge pump circuit employed in the operational mode of the present invention.
FIG. 5 is a schematic diagram showing simulation results of spectre of the word line driving circuit according to the present invention in the operation mode.
FIG. 6 is a schematic diagram showing simulation results of spectre of the word line driving circuit in standby mode according to the present invention.
Detailed Description
The invention is further described below with reference to the drawings and the detailed description, but the examples are not to be construed as limiting the invention.
As shown in fig. 1, a conventional word line voltage driving circuit is shown, in which a circuit in an operation mode includes a resistor divider formed by a DICKSON charge pump, a ring oscillator, a comparator and small resistors R1 and R2 (K ohm level), and in which a circuit in a standby mode includes a resistor divider formed by a DICKSON charge pump, a ring oscillator, a comparator, a latch and a counter and large resistors R3 and R4 (M ohm level), and in addition, a high-resistance low-power voltage reference source continuously supplies reference voltages for both modes. It can be seen that both modes use DICKSON charge pumps as charge pump power stages and SKIP modulation voltage stabilizing circuits to stabilize the output voltage, and that both modes use resistive voltage dividers as feedback networks in the voltage stabilizing circuits.
The conventional word line driving circuit has the disadvantage that the two modes adopt the same charge pump type and the same voltage stabilizing system, and cannot better meet the different performance requirements of the two modes. For the working mode, the DICKSON charge pump has the defect of low boosting efficiency caused by larger threshold voltage loss, and the SKIP modulation voltage stabilizing circuit has the defect of large ripple, so that the quick establishment of word line voltage and low ripple output are difficult to realize due to two circuit structures, the resistor voltage divider still adopted in the standby mode can generate additional static power consumption and has slower response speed, and in addition, the chip area utilization rate can be reduced by adopting the high-resistance voltage reference source as the reference circuit.
A schematic diagram of a fast low power wordline driver circuit in accordance with the present invention is shown in fig. 2. The system comprises two modes, namely a working mode and a standby mode; the circuit in the working mode comprises:
an operating mode charge pump power stage comprising a cross-coupled charge pump for generating a high voltage;
The dynamic frequency modulation voltage stabilizing circuit sequentially comprises a voltage-controlled oscillator, a non-overlapping clock generating circuit module, an error amplifier EA and resistor voltage dividers R1 and R2, and is used for outputting high voltage generated by a charge pump stably and with low ripple waves under all PVT (process, voltage and temperature);
an ultra-low power consumption voltage reference source for providing a reference voltage VREF for the error amplifier EA;
the NMOS device M1 is used as a switching tube controlled by the signal ACT_EN for triggering an operation mode, and in fact, a switching MOS tube controlled by the signal ACT_EN and an inversion signal ACT_ENB thereof is used for switching in two modes in the first-stage cross-coupled charge pump, the voltage-controlled oscillator and other modules;
the NMOS device M5 can form a low-pass filter with the load capacitor Cout to effectively suppress the output voltage ripple.
The circuit in standby mode comprises:
a standby mode charge pump power stage comprising DICKSON charge pumps for generating high voltages;
the SKIP modulation voltage stabilizing circuit sequentially comprises a current starving oscillator, a non-overlapping clock generating circuit, a hysteresis comparator, a down counter, an inverter module, a NOR gate, a capacitor voltage divider and a refreshing circuit of a connecting point VD of the capacitor voltage divider C1 and C2, and is used for maintaining output voltage in a standby mode;
an ultra-low power consumption voltage reference source for providing a reference voltage VREF for the hysteresis comparator COM and providing a bias voltage VBIAS for the current starvation oscillator;
The NMOS device M2 is controlled by the signal act_enb as a switching transistor for standby mode triggering, and in fact, the switching MOS transistor controlled by the signal stb_en is used for two-mode switching in the first stage DICKSON charge pump, current starved oscillator, and other modules.
The down counter counts the charging time of the charge pump in each standby mode, and continuously works before the down counter counts to 0 so as to avoid overshoot of the output voltage.
The inverter module comprises inverters INV 1-INV 3, the INV1 and INV2 are used for rectifying the output signal of the hysteresis comparator COM, and the INV3 is used for inverting the output signal of the subtracter to generate ENPD signals.
The nor gate is used to generate a standby mode enable signal STB EN to control the current starving oscillator and DICKSON charge pump under control of signal ENPD and signal ACT EN.
The refresh circuit of the connection point VD of the capacitors C1 and C2 sequentially comprises an NMOS device M3 controlled by the enable signal act_en, a PMOS device M4 controlled by the enable signal act_enb, and resistors R3 and R4, which are used for providing an initial voltage for the connection point VD, and refreshing the connection point VD when the two modes are switched.
The word line driving circuit in the invention replaces DICKSON charge pump in the working mode in the traditional circuit with a cross coupling charge pump after structure optimization, and replaces the SKIP modulation voltage stabilizing circuit with a dynamic frequency modulation voltage stabilizing circuit; the invention still adopts DICKSON charge pump in the traditional word line driving circuit as the power stage of the charge pump, the SKIP modulates the voltage stabilizing circuit to stabilize the output voltage, the resistance voltage divider in the SKIP modulates the voltage stabilizing circuit in the standby mode is replaced by the capacitor voltage divider to reduce standby power consumption and improve the response time of the feedback loop, in addition, the low power consumption voltage reference source of high resistance in the traditional circuit is replaced by an ultra-low power consumption voltage reference source of a full MOS tube, the utilization ratio of the chip area is improved, and simultaneously, an NMOS device connected in a diode mode is added at the voltage output position to further optimize the output voltage ripple.
Two modes of implementation are described below:
When the word line driving circuit is in a working mode, the three-stage cross-coupled charge pump is used for boosting quickly, when the charge pump is just charged, the output voltage is lower, the feedback voltage VFB obtained after detection by the resistor divider R1 and the resistor divider R2 is smaller than the reference voltage VREF, the output VCTRL of the error amplifier EA tends to be saturated so that the voltage-controlled oscillator generates a high-frequency clock signal ACT_CLK, and the charge pump is charged quickly and is stabilized to the target word line voltage quickly. A diode-connected NMOS device M5 is also added at the output of the word line voltage Vwl, which, together with the output load capacitance Cout, constitutes a low-pass filter that can further optimize the output voltage ripple.
When the word line driving circuit enters a standby mode. When the output voltage is detected by the capacitive voltage divider to obtain that the VD point voltage is smaller than the reference voltage VREF, the hysteresis comparator COM outputs a high level, the signal ENP is generated after rectification by the two-stage inverters INV1 and INV2 to trigger the counter count, the signal ENPD is generated after passing through the inverter INV3, the enable signal stb_en generated after passing through the nor gate between the signal ENPD and the signal act_en starts the current starving oscillator to generate the low-frequency clock stb_clk to drive the charge pump, and the charge pump continuously works before the counter count of the counter is 0.
After the charge pump in standby mode is charged, the signal stb_en is restored to low level, DICKSON the charge pump and the current starvation oscillator stop working, but the output voltage is inevitably reduced due to the existence of leakage current at the output voltage Vwl, so that the voltage detector formed by the capacitive voltage dividers C1 and C2, the hysteresis comparator and the like still needs to continuously work to detect the output voltage, and once the output voltage is detected to be lower than the target value, the standby mode enabling signal stb_en is turned to high level again so that the charge pump and the oscillator start working. It is noted that a refresh circuit is required for the junction VD of the capacitors C1, C2 in the standby mode, which comprises an NMOS device M3 controlled by the enable signal act_en, a PMOS device M4 controlled by the enable signal act_enb, and resistors R3 and R4, which is used to provide an initial voltage for the junction VD and refresh the junction VD when the two modes are switched.
As shown in fig. 3, the timing waveforms of the word line driving circuit system in the present invention are shown in fig. 3, when the circuit is in the operation mode, the act_en signal is at a high level, the act_enb signal and the stb_en signal are both at a low level, and the voltage-controlled oscillator in the operation mode starts to oscillate at a high frequency to generate the clock signal act_clk to charge the cross-coupled charge pump, so that the output voltage rises rapidly and stabilizes to the target voltage vout_r, and the output voltage is optimized by the ripple to generate the word line voltage Vwl.
When the circuit is in standby mode, the signal ACT_EN is low, the signal ACT_ENB is continuously high, under the condition of standby mode 1, the STB_EN signal is changed to high to start a current starvation type oscillator and DICKSON charge pump in standby mode to raise the output voltage to a value slightly higher than the target voltage, and under the condition of standby mode 2, the oscillator and the charge pump in standby mode are not operated, and a voltage detector formed by a hysteresis comparator, a capacitive voltage divider and the like continuously detects whether the output voltage is lower than the target voltage value so as to enter standby mode 1 again to raise the output voltage.
FIG. 4 is a schematic diagram of an optimized single-stage cross-coupled charge pump configuration used in the operational mode of the present invention. In addition, the NMOS devices MN3 and MN4 connected in a diode mode are added on the basis of the original structure to serve as pre-charging tubes to optimize the rising time of the output voltage, and the PMOS devices MP10 and MP20 are added to enable the substrate potential of MP1 and MP2 to be always in a high level, so that reverse leakage current is restrained to further improve the pump efficiency.
Fig. 5 is a schematic diagram showing a result of spectre analog transient simulation of the word line driving circuit in the working mode, wherein the act_en signal is at a high level, the act_enb signal and the stb_en signal are at a low level, and at this time, the voltage-controlled oscillator in the working mode starts high-frequency oscillation to generate a high-frequency clock signal act_clk to drive the cross-coupled charge pump, so that the output voltage rises to the target voltage vout_r rapidly, and the output voltage is optimized by ripple to generate the word line voltage Vwl.
FIG. 6 is a schematic diagram showing the simulation result of spectre of the word line driving circuit in standby mode according to the present invention. The signal ACT_EN is low, the signal ACT_ENB is continuously high, the current starved oscillator in standby mode generates a low frequency clock signal STB_CLK to drive DICKSON the charge pump when the signal STB_EN goes high, the charge pump is continuously operated to raise the output voltage to a value slightly higher than the target voltage before the down counter counts to 0, and the oscillator and the charge pump in standby mode are not operated when the signal STB_EN goes low, and a voltage detector formed by a comparator, a capacitive voltage divider and the like continuously detects whether the output voltage is lower than the target voltage value so as to turn on the oscillator and the charge pump again. Meanwhile, in the whole standby mode, the time required for the modules such as the current starvation oscillator, the DICKSON charge pump, the down counter and the like to work is less than the duration of the whole standby mode, so that the average power consumption in the standby mode mainly comes from the static power consumption of the circuit. And because the capacitive voltage divider is adopted, a part of static power consumption is avoided, so that the overall average standby power consumption of the standby mode is obviously reduced.
The embodiments in the foregoing description may be further combined or replaced, and the embodiments are merely illustrative of the preferred embodiments of the present invention and are not intended to limit the spirit and scope of the present invention, and various changes and modifications made by those skilled in the art to which the present invention pertains without departing from the spirit of the present invention. The scope of the invention is given by the appended claims and any equivalents thereof.
Claims (6)
1. A fast low-power consumption word line driving circuit applied to NOR Flash is characterized in that,
The system comprises two modes, namely a working mode and a standby mode; the circuit in the working mode comprises:
an operating mode charge pump power stage comprising a cross-coupled charge pump for generating a high voltage;
The dynamic frequency modulation voltage stabilizing circuit sequentially comprises a voltage-controlled oscillator, a non-overlapping clock generating circuit module, an error amplifier EA and resistor voltage dividers R1 and R2, and is used for outputting high voltage generated by a charge pump stably and with low ripple waves under all PVT conditions;
an ultra-low power consumption voltage reference source for providing a reference voltage VREF for the error amplifier EA;
the NMOS device M1 is used as a switching tube and is controlled by a signal ACT_EN for triggering an operation mode;
The NMOS device M5 can form a low-pass filter with the load capacitor Cout and is used for effectively inhibiting output voltage ripple;
the circuit in standby mode comprises:
a standby mode charge pump power stage comprising DICKSON charge pumps for generating high voltages;
the SKIP modulation voltage stabilizing circuit sequentially comprises a current starving oscillator, a non-overlapping clock generating circuit, a hysteresis comparator, a down counter, an inverter module, a NOR gate, a capacitor voltage divider and a refreshing circuit of a connecting point VD of the capacitor voltage divider C1 and C2, and is used for maintaining output voltage in a standby mode;
an ultra-low power consumption voltage reference source for providing a reference voltage VREF for the hysteresis comparator COM and providing a bias voltage VBIAS for the current starvation oscillator;
An NMOS device M2 as a switching transistor controlled by a signal ACT_ENB for standby mode triggering;
The down counter counts the charging time of the charge pump in each standby mode, and continuously works before the down counter counts to 0 so as to avoid overshoot of the output voltage;
the inverter module comprises inverters INV 1-INV 3, wherein INV1 and INV2 are used for rectifying an output signal of the hysteresis comparator COM, and INV3 is used for inverting an output signal of the subtracter to generate ENPD signals;
the nor gate is used for generating a standby mode enable signal stb_en under the control of the signal ENPD and the signal act_en to control the current starving oscillator and the DICKSON charge pump;
The refresh circuit of the connection point VD of the capacitors C1 and C2 sequentially comprises an NMOS device M3 controlled by the enable signal act_en, a PMOS device M4 controlled by the enable signal act_enb, and resistors R3 and R4, which are used for providing an initial voltage for the connection point VD, and refreshing the connection point VD when the two modes are switched.
2. The fast low power consumption word line driving circuit for NOR Flash as claimed in claim 1, wherein said cross-coupled charge pump in said operating mode has a precharge tube for optimizing rise time and a substrate modulator for suppressing reverse leakage current.
3. The fast low power consumption word line driving circuit for NOR Flash as claimed in claim 1, wherein said ultra-low power consumption voltage reference source adopts a non-resistive full MOS transistor structure, and the NMOS device in deep triode region is used to replace resistor, and the rest MOS devices are all in subthreshold region, thereby realizing nW level power consumption.
4. The fast low power consumption word line driving circuit for NOR Flash as claimed in claim 1, wherein the current starvation oscillator in the standby mode circuit and the MOS devices in the hysteresis comparator are operated in a subthreshold region, the static power consumption is lower, and the static current is in nA level.
5. The fast low power consumption word line driving circuit for NOR Flash as claimed in claim 1, wherein said NMOS device M5 is diode connected and low threshold voltage NMOS device is used to reduce threshold voltage loss of output voltage.
6. The fast low power consumption word line driving circuit for NOR Flash as claimed in claim 1, wherein said PMOS device, NMOS device, MOS device and switch MOS transistor are metal oxide semiconductor MOS transistors.
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| CN202210166346.3A CN114582400B (en) | 2022-02-23 | 2022-02-23 | Fast and low power word line driver circuit for NOR Flash |
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| CN202210166346.3A CN114582400B (en) | 2022-02-23 | 2022-02-23 | Fast and low power word line driver circuit for NOR Flash |
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| WO2012144116A1 (en) * | 2011-04-19 | 2012-10-26 | パナソニック株式会社 | Charge-pump type dc-dc converter |
| CN105932873B (en) * | 2016-06-17 | 2018-05-25 | 苏州昆泰芯微电子科技有限公司 | A kind of charge pump of low-power consumption high output voltage |
| CN111934541B (en) * | 2019-05-13 | 2021-10-01 | 北京兆易创新科技股份有限公司 | Charge pump voltage stabilizing circuit, voltage stabilizing method and nonvolatile memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2015092372A (en) * | 2014-12-15 | 2015-05-14 | 株式会社東芝 | Memory control device, semiconductor device, system board, and information processing device |
| CN106908965A (en) * | 2015-12-22 | 2017-06-30 | 庄臣及庄臣视力保护公司 | For the high voltage H bridge control circuits of the lens driver of electronic type ophthalmic lens |
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