CN114566199A - Read reference circuit, read operation circuit and memory cell - Google Patents
Read reference circuit, read operation circuit and memory cell Download PDFInfo
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- CN114566199A CN114566199A CN202011362372.0A CN202011362372A CN114566199A CN 114566199 A CN114566199 A CN 114566199A CN 202011362372 A CN202011362372 A CN 202011362372A CN 114566199 A CN114566199 A CN 114566199A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
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Abstract
The application provides a read reference circuit, a read operation circuit and a memory cell, the read reference circuit includes: one or more reference modules connected in parallel; the reference module comprises a first reference unit and a second reference unit which are connected in series and different in write data; the current directions of the first reference unit and the second reference unit are the same during writing operation and reading operation respectively. According to the technical scheme, the reading reference circuit, the reading operation circuit and the memory unit can avoid the interference of the MRAM during reading operation.
Description
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a read reference circuit, a read operation circuit, and a memory cell.
Background
Magnetic Random Access Memory (MRAM) has the characteristics of high read-write speed, high density, low power consumption, long data storage time, long service life and the like, and therefore has immeasurable and broad prospects. Since MRAM has a variability in resistance, data information can be stored by its different resistance states.
MRAM includes a Magnetic Tunnel Junction (MTJ), and since the MTJ data is written by changing the magnetic moment direction of a free layer by a spin electron current, data is also written by a small current for a long time, and thus disturbance (read disturb) is likely to occur during a read operation, thereby rewriting data.
Disclosure of Invention
The technical problem solved by the application is to avoid the interference of MRAM in the reading operation.
To solve the above technical problem, the present application provides a read reference circuit, including: one or more reference modules connected in parallel; the reference module comprises a first reference unit and a second reference unit which are connected in series and different in write data; the current directions of the first reference unit and the second reference unit are the same during writing operation and reading operation respectively.
In an embodiment of the present application, the read reference circuit further includes: a first reference bit line connected to the first reference cell; a second reference bit line connected to the second reference cell; a reference source line connecting the first reference cell and the second reference cell; wherein one of the first reference bit line and the second reference bit line outputs a reference signal, the other one is connected with a low level, and the reference source line is floating.
In the embodiment of the present application, the first reference cell writes 0, the second reference cell writes 1, the first reference bit line outputs a reference signal, and the second reference bit line is connected to a low level.
In an embodiment of the present application, the first reference cell includes: a first MTJ cell connected to the first reference bit line; a first transistor having a first electrode connected to the first MTJ cell and a second electrode connected to the reference source line and the second reference cell.
In an embodiment of the present application, the second reference cell includes: a second MTJ cell connected to the second reference bit line; a second transistor having a first electrode connected to the second MTJ cell and a second electrode connected to the reference source line and a second electrode of the first transistor.
The present application also provides a read operation circuit, comprising: the reading reference circuit is used for providing a reference signal and comprises one or more parallel reference modules, each reference module comprises a first reference unit and a second reference unit which are connected in series and different in written data, and the current directions of the first reference unit and the second reference unit are the same when the first reference unit and the second reference unit are respectively subjected to writing operation and reading operation; a data path providing data to be read and outputting a data signal; and the amplifying circuit is connected with the reference circuit and the data path and used for comparing the data signal with the reference signal and obtaining a reading result.
In an embodiment of the present application, the reference circuit further includes: a first reference bit line connected to the first reference cell; a second reference bit line connected to the second reference cell; a reference source line connecting the first reference cell and the second reference cell; one of the first reference bit line and the second reference bit line is connected with the amplifying circuit, the other one of the first reference bit line and the second reference bit line is connected with a low level, and the reference source line is floating.
In the embodiment of the present application, the first reference cell writes 0, the second reference cell writes 1, the first reference bit line is connected to the amplifying circuit, and the second reference bit line is connected to a low level.
In an embodiment of the present application, the first reference unit includes: a first MTJ cell connected to the first reference bit line; a first transistor having a first electrode connected to the first MTJ cell and a second electrode connected to the reference source line and the second reference cell.
In an embodiment of the present application, the second reference cell includes: a second MTJ cell connected to the second reference bit line; a second transistor having a first electrode connected to the second MTJ cell and a second electrode connected to the reference source line and a second electrode of the first transistor.
In an embodiment of the present application, the data path includes a data storage unit, one end of the data storage unit is connected to a bit line, the other end of the data storage unit is connected to a source line, and the source line is connected to the amplifying circuit.
In an embodiment of the present application, the data signal is an output current of the data path, and the reference signal is an output current of the reference circuit.
In an embodiment of the present application, the amplifying circuit includes a sense amplifier.
The present application also provides a memory cell comprising the read operation circuit of claim above.
The reading reference circuit comprises one or more parallel reference modules, each reference module comprises a first reference unit and a second reference unit which are connected in series and different in written data, the directions of reading operation currents and writing operation currents of the first reference unit and the second reference unit are consistent, the problem that the reading disturb easily occurs to the reference unit writing '1' is effectively solved, the data storage performance is remarkably improved, meanwhile, the consistency of the improved reference circuit and the whole array can be guaranteed, and the conventional cognition that a reference bit line is connected with a high level and a reference source line is connected with a low level in the reading operation of the conventional reading reference circuit is broken.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
FIG. 1 is a schematic diagram of a reference circuit;
FIG. 2 is a schematic diagram of a read reference circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a read operation circuit according to an embodiment of the present application.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
Referring to fig. 1, a reference circuit includes a reference cell (0cell) for writing "0" and a reference cell (1cell) for writing "1", wherein the reference cell for writing "0" includes an MTJ0 and a transistor M0, one end of the MTJ0 is connected to a reference bit line BL _ REF <1>, the other end is connected to the transistor M0, and one end of the transistor M0 is connected to a source line SL. The reference unit (1cell) for writing '1' comprises MTJ1 and transistor M1, one end of MTJl is connected to reference bit line BL _ REF <0>, the other end is connected to transistor M1, and one end of transistor M1 is connected to source line SL.
The reference unit for writing '0' and the reference unit for writing '1' are connected in parallel, and the bit line BL _ REF is used for reading<1>And the bit line BL _ REF<0>High, the source line SL is grounded, and the reference current I of the reference unit for writing' 0PFlowing from FL (free layer) to PL (fixed layer), reference current IPHas a size of V0/(R)P+ R0), V0 is the voltage across the reference cell for writing a "0", RPR0 is the resistance of transistor M0, which is the resistance of MTJ 0. Similarly, the reference current I of the reference cell for writing "1APFlowing from FL (free layer) to PL (fixed layer), reference current IAPHas a size of V1/(R)AP+ ri), V1 is the voltage across the reference cell for writing a "0", RAPR1 is the resistance of transistor M1 for the resistance of MTJ1, and the reference current I after the reference cell for writing "0" and the reference cell for writing "1" are connected in parallel is 0.5(IP+IAP)。
Usually, a set of reference circuits is used to reference devices on a plurality of bit lines BL, and assuming that the number of bit lines BL is 2, the total charge flowing through the reference device is the same as that of the general device2x times that of the reference device, which makes the total amount of charge in the reference device 2x times that of the general device, due to the reference cell write current and the reference current I for writing "1APThe flow direction of the MRAM is not consistent, which greatly improves the probability of read disturb (read disturb) occurring in 1cell in the reference device, and will greatly limit the data retention of the whole MRAM.
The technical scheme of the application provides a read reference circuit, reference bit line meets the high level when having broken through read operation, the conventional cognition that the reference source line meets the low level, the realization form through changing reference circuit improves the reliability, it uses 0cell and 1cell in series, it keeps unanimous with MTJ write-in data to realize the reference current flow direction, the problem that MRAM takes place read disturb easily is solved, effectively improve the retention property of data, can also guarantee the uniformity of reference circuit and whole array (array) after the improvement simultaneously.
The technical solution of the present application will be described in detail below with reference to the embodiments and the accompanying drawings.
Referring to fig. 2, the read reference circuit according to the embodiment of the present application includes reference modules 11, where the number of the reference modules 11 may be one or more, and the reference modules 11 are connected in parallel. The embodiment of the application takes two parallel reference modules as an example for explanation.
The reference module 11 includes a first reference cell 111 and a second reference cell 112 connected in series, where the first reference cell 111 and the second reference cell 112 have different write data, for example, the first reference cell 111 writes "0", the second reference cell 112 writes "1", or the first reference cell 111 writes "1", and the second reference cell 112 writes "0". Embodiments of the present application provide that when writing a "0" current flows from the free layer to the fixed layer of the MTJ cell, and when writing a "1" current flows from the fixed layer to the free layer of the MTJ cell. In another embodiment, it may be specified that when writing "0", current flows from the fixed layer to the free layer of the MTJ cell, and when writing "1", current flows from the free layer to the fixed layer of the MTJ cell, and programming is performed as the case may be.
In the embodiment of the present application, the first reference cell 111 has the same current flow direction when performing a write operation and a read operation, and the second reference cell 112 also has the same current flow direction when performing a write operation and a read operation, and since the first reference cell 111 and the second reference cell 112 are connected in series, the current flow direction and the magnitude of the current flowing through the first reference cell 111 and the second reference cell 112 are the same. The current directions of the first reference cell 111 and the second reference cell 112 during the write operation and the read operation are the same, so that the read disturb of the reference cells can be avoided.
The read reference circuit further comprises a first reference bit line BL _ REF <1>, a second reference bit line BL _ REF <2> and a reference source line SL _ REF, wherein the first reference bit line BL _ REF <1> is connected with the first reference unit 111, namely the first reference bit line BL _ REF <1> is connected with one end of the reference module 11, and the second reference bit line BL _ REF <2> is connected with the second reference unit 112, namely the second reference bit line BL _ REF <2> is connected with the other end of the reference module 11. The reference source line SL _ REF connects the first reference unit 111 and the second reference unit 112 of each reference module 11, that is, all the reference units share one reference source line SL _ REF.
One of the first reference bit line BL _ REF <1> and the second reference bit line BL _ REF <2> is used for outputting a reference signal, the other one is connected with a low level, and the reference source line SL _ REF is floated. The embodiment of the application enables the reference bit line connected with the reference unit for writing '0' to be used for outputting the reference signal, and the reference bit line connected with the reference unit for writing '1' to be connected with low level. In the embodiment of the present application, the first reference cell 111 writes "0", the first reference bit line BL _ REF <1> connected to the first reference cell 111 is used to output a reference signal, and the second reference cell 111 writes "1", and the second reference bit line BL _ REF <2> connected to the second reference cell 112 is connected to a low level. In other embodiments, it may be provided that the first reference cell 111 writes "1", the first reference bit line BL _ REF <1> connected to the first reference cell 111 is connected to a low level, the second reference cell 111 writes "0", and the second reference bit line BL _ REF <2> connected to the second reference cell 112 is used for outputting a reference signal, and the reference source line SL _ REF is floated.
In the embodiment of the application, by designing the connection mode of the first reference bit line BL _ REF <1>, the second reference bit line BL _ REF <2> and the reference source line SL _ REF, the current directions of the first reference cell 111 during the write operation and the read operation are the same, and the current directions of the second reference cell 112 during the write operation and the read operation are also the same, so that the phenomenon that the read disturb occurs in the reference cell writing "1" due to the fact that the flow directions of the write current and the reference current of the reference cell writing "1" are not the same is avoided.
With continued reference to fig. 2, the first reference cell 111 includes a first MTJ cell (0cell) and a first transistor M1, the first MTJ cell (0cell) being connected to the first reference bit line BL _ REF<1>And write current and reference current IREFAll flowing from FL (free layer) to PL (fixed layer). A first electrode of the first transistor M1 is connected to the first MTJ cell (0cell), and a second electrode of the first transistor M1 is connected to the reference source line SL _ REF and the second reference cell 112. In the embodiment of the present application, the first transistor M1 may be a PMOS transistor, the first electrode of the first transistor M1 may be a source, and the second electrode of the first transistor M1 may be a drain.
The second reference cell 112 includes a second MTJ cell (1cell) and a second transistor M2, the second MTJ cell (1cell) is connected to the second reference bit line BL _ REF <2>, and the directions of the write current and the reference current flowing through the second MTJ cell (1cell) are from PL to FL. A first electrode of the second transistor M2 is connected to the second MTJ cell (1cell), and a second electrode of the second transistor M2 is connected to the reference source line SL _ REF and a second electrode of the first transistor M1. In the embodiment of the present application, the second transistor M2 may be a PMOS transistor, the first electrode of the second transistor M2 may be a drain, and the second electrode of the second transistor M2 may be a source.
The reading reference circuit of the embodiment of the application adopts a connection mode of a common reference source line SL _ REF, two reference units are connected in series to form a group of reference modules, and then a plurality of groups of reference modules are connected in parallel to form a reference moduleAnd (5) blocking. When writing data, the first reference bit line BL _ REF<1>The connected reference cell writes a "0" to the second reference bit line BL _ REF<2>The data written by the connected reference cell is "1"; in a read operation, the first reference bit line BL _ REF<1>Connected to an amplifying module (such as a sense amplifier), the second reference bit line BL _ REF<2>The reference source line SL _ REF is floating, and when the number of parallel groups is 2, the obtained reference current IREFComprises the following steps:
IREF＝2V/(RP+RAP+2×r)；
where V is the total voltage of the first reference cell 111 and the second reference cell 112, and RPIs the resistance value, R, of the first MTJ cell (0cell)APIs a resistance value of the second MTJ cell (1cell), and r is resistance values of the first transistor M1 and the second transistor M2. Said IREFIs shown in figure 1 as IPAnd IAPIn the meantime.
For the first MTJ cell (0cell) of the first reference bit line BL _ REF <1>, the current direction is from FL to PL, the same as the current direction for writing data "0"; for the second MTJ cell (1cell) of the second reference bit line BL _ REF <2>, the current direction is from PL to FL, the same as the current direction for writing data "1", thus avoiding the possibility of read disturb in the reference cell.
Referring to fig. 3, an embodiment of the present application further provides a read operation circuit, which includes a reference circuit 1, a data path 2, and an amplifying circuit 3. The reference circuit 1 is configured to provide a reference signal, the data path 2 is configured to provide data to be read and output a data signal, and the amplifying circuit 3 is configured to compare the data signal with the reference signal and obtain a read result.
The reference circuit 1 includes one or more parallel reference modules 11, the reference module 11 includes two first reference cells 111 and two second reference cells 112 connected in series and having different write data, and the current directions of the first reference cells 111 and the second reference cells 112 are the same when performing write operation and read operation, respectively, so that the possibility of read disturb occurring in each reference cell can be avoided, and the data storage performance of the MRAM can be effectively improved.
The reference circuit 1 further includes a first reference bit line BL _ REF <1>, a second reference bit line BL _ REF <2>, and a reference source line SL _ REF, wherein the first reference bit line BL _ REF <1> is connected to the first reference cell 111, the second reference bit line BL _ REF <2> is connected to the second reference cell 112, and the reference source line SL _ REF is connected to the first reference cell 111 and the second reference cell 112. Wherein one of the first reference bit line BL _ REF <1> and the second reference bit line BL _ REF <2> is connected to the amplifying circuit 3, the other is connected to a low level, and the reference source line SL _ REF is floating. In the embodiment of the present application, the reference bit line connected to the reference cell for writing "0" is connected to the amplifying circuit 3, the reference bit line connected to the reference cell for writing "1" is connected to a low level, that is, the first reference bit line BL _ REF <1> is connected to the amplifying circuit 3 for outputting a reference signal, the second reference bit line BL _ REF <2> is connected to a low level to provide a low level, and the reference source line SL _ REF has no current flowing through, so that the read reference circuit is a series circuit, thereby ensuring that a reference current flows from the first reference cell 111 to the second reference cell 112.
With continued reference to fig. 3, the first reference cell 111 includes a first MTJ cell (0cell) connected to the first reference bit line BL _ REF <1> storing data "0" and a first transistor M1 having a first electrode connected to the first MTJ cell (0cell) and a second electrode connected to the reference source line SL _ REF and the second reference cell 112 of the first transistor M1. The first transistor M1 may be a PMOS transistor, the first electrode of the first transistor M1 may be a source, and the second electrode of the first transistor M1 may be a drain.
The second reference cell 112 includes a second MTJ cell (1cell) and a second transistor M2, the second MTJ cell (1cell) being connected to the second reference bit line BL _ REF <2> and storing data "1", a second electrode of the second transistor M2 being connected to the reference source line SL _ REF and a second electrode of the first transistor M1. The second transistor M2 may be a PMOS transistor, the first electrode of the second transistor M2 may be a drain, and the second electrode of the second transistor M2 may be a source.
The data path 2 includes a plurality of data storage units 21, the number of the data storage units 21 may be multiple, and the data storage units 21 are used for storing the same or different data, one end of each data storage unit 21 is connected to a bit line BL, the other end of each data storage unit is connected to a source line SL, and the source line SL is connected to the amplifying circuit 3.
The data storage unit 21 includes an MTJ cell (cell) and a transistor M0, wherein a Free Layer (FL) of the MTJ cell (cell) is connected to the bit line BL, a Pinned Layer (PL) of the MTJ cell (cell) is connected to a first electrode of the transistor M0, and a second electrode of the transistor M0 is connected to the source line SL, wherein the transistor M0 may be a PMOS, the first electrode of the transistor M0 may be a source, and the second electrode of the transistor M0 may be a drain.
The amplifying circuit 3 is connected to the reference circuit 1 and the data path 2, and specifically, the amplifying circuit 3 is connected to a first reference bit line BL _ REF of the reference circuit 1<1>And a bit line BL of the data path 2 for comparing the data signal of the data path 2 with the reference signal of the reference circuit 1 and obtaining a read result. In some embodiments, the data signal is the output current I of the data path 2cellThe reference signal is the output current I of the reference circuit 1REFIf the current I is outputcellGreater than the output current IREFThen the result of the read is "1"; if the current I is outputcellLess than the output current IREFThe result of the reading is "0".
According to the embodiment of the application, the reference bit line connected with the reference unit for writing '0' in the read reference circuit outputs the reference signal, the reference bit line connected with the reference unit for writing '1' is connected with a low level, the source line shared by the two reference units is floated, the reference units are connected in series, and meanwhile the directions of the write operation current and the read operation current of each reference unit are the same, so that the read disturb problem caused by the fact that the flow directions of the write current and the reference current of the reference unit for writing '1' are not consistent is solved, and the reading performance of the read reference circuit is greatly improved.
The embodiment of the application also provides a storage unit which comprises the read operation circuit.
In summary, after reading the present disclosure, those skilled in the art will appreciate that the foregoing may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, improvements, and modifications are intended to be within the spirit and scope of the exemplary embodiments of the application.
It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.
Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.
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