CN114547854A

CN114547854A - Chip packaging electromagnetic modeling system, method and device

Info

Publication number: CN114547854A
Application number: CN202210036350.8A
Authority: CN
Inventors: 蒋历国; 凌峰; 钟章民; 代文亮
Original assignee: Core And Semiconductor Technology Shanghai Co ltd
Current assignee: Core And Semiconductor Technology Shanghai Co ltd
Priority date: 2022-01-13
Filing date: 2022-01-13
Publication date: 2022-05-27
Anticipated expiration: 2042-01-13
Also published as: CN114547854B

Abstract

The invention is applicable to the technical field of chip packaging, and provides a chip packaging electromagnetic modeling system, method and device. A chip packaging electromagnetic modeling system, the chip packaging electromagnetic modeling system includes a design module and a simulation module: the design module completes the chip layout, constructs the chip package, and optimizes and improves the chip according to the simulation result of the chip package. package to obtain a qualified chip package; the simulation module simulates the chip package in the design environment of the design module, and transmits the simulation result to the design module. The invention realizes the interaction between simulation tools and design tools by carrying out simulation simulation in the design module, unifies the data of the design environment and the simulation environment, avoids the tedious data exchange process, and reduces the consumption of manpower and time resources; the chip packaging is optimized according to the simulation results. , to improve the rationality of chip settings.

Description

Chip packaging electromagnetic modeling system, method and device

Technical Field

The invention belongs to the technical field of advanced packaging of chip products, and particularly relates to a chip packaging electromagnetic modeling system, method and device.

Background

With the continuous development of artificial intelligence, 5G and data centers, mass data is continuously generated, and a Central Processing Unit (CPU) of a traditional architecture cannot meet the requirements of HPC (High Performance Computing). Advanced packaging technology represented by Heterogeneous Integration (Heterogeneous Integration) is an advanced technology in the post-molar era, and provides possibility for realizing higher computing power. In the Field of FPGA (Field Programmable Gate Array), GPU (graphics processing unit), and CPU, heterogeneous integration technologies are widely used, and typical examples include Fiji GPU of AMD (Advanced Micro Devices, ultra-power semiconductors in the united states) and Pascal GPU of england, where one GPU is connected to four HBMs (High Bandwidth Memory) around through a silicon adapter board.

2.5D (2.5 dimensions) and 3DIC (three-dimensional integrated circuit) advanced packaging is to interconnect the original functions requiring a package substrate for inter-chip interconnection by using a silicon substrate or a chip stack through TSV (through silicon via). One of the biggest advantages of 2.5D and 3DIC is the heterogeneity in heterogeneous integration, which actually corresponds to the previous monolithic integration. The biggest advantage of single-chip integration for making the heterogeneous structure is that the method is very flexible and can realize mixing and matching by using different process nodes; another advantage is that two dice (chips) in close proximity are directly connected, the wiring density can be much greater on a silicon carrier than on a package, the size of the chip can be made smaller, better signal performance and thermal performance can be achieved, etc.

This presents new challenges to electromagnetic field modeling schemes. The existing advanced package electromagnetic field modeling scheme is independent of the chip design flow. After the chip is designed, it is provided to an electromagnetic field simulation tool through data exchange, which models the interconnects. This scheme requires frequent data exchange and is time consuming and labor intensive.

Disclosure of Invention

The embodiment of the invention aims to provide a chip packaging electromagnetic modeling system, aiming at improving the data exchange efficiency of chip design and simulation.

The embodiment of the invention is realized in such a way that a chip packaging electromagnetic modeling system comprises a design module and a simulation module:

the design module completes chip layout, constructs chip packaging and optimizes and improves the chip packaging according to the simulation result of the chip packaging to obtain qualified chip packaging;

and the simulation module carries out simulation on the chip package in the design environment of the design module and transmits the simulation result to the design module.

Another objective of an embodiment of the present invention is to provide a chip package electromagnetic modeling method, including:

obtaining design parameters of chip packaging, finishing chip layout through a design module and constructing a first chip packaging;

performing simulation on the first chip package in the design environment of the design module to obtain a simulation result;

and optimizing and improving the chip package according to the simulation result, and obtaining the qualified chip package through time domain verification and physical verification of a verification submodule.

Another objective of an embodiment of the present invention is to provide a chip package electromagnetic modeling apparatus, which includes a design module and a simulation module:

According to the chip packaging electromagnetic modeling system provided by the embodiment of the invention, the simulation is carried out in the design module, the data of the design environment and the simulation environment are unified, the interaction between the simulation tool and the design tool is realized, the complex data exchange process is avoided, and the consumption of manpower and time resources is reduced; and optimizing the chip package according to the simulation result, and improving the reasonability of the chip setting.

Drawings

FIG. 1 is a block diagram of a chip package electromagnetic modeling system;

FIG. 2 is a flow chart of the design of a chip package;

FIG. 3 illustrates three modes of an electromagnetic field simulation tool;

FIG. 4 is an insertion loss diagram of a 2.5D silicon interposer transmission line trace;

FIG. 5 is a return loss plot of a 2.5D silicon interposer transmission line trace;

FIG. 6 is a time domain reflection diagram of a 2.5D silicon interposer transmission line trace;

FIG. 7 is a time domain eye diagram of a 2.5D silicon interposer transmission line trace;

FIG. 8 is a flow chart of a chip package electromagnetic modeling method;

FIG. 9 is a flow chart of a method for constructing a first chip package;

FIG. 10 is a flow chart of a method of obtaining simulation results;

fig. 11 is a flowchart of a method for verifying a qualified chip package.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms unless otherwise specified. These terms are only used to distinguish one element from another. For example, a first xx script may be referred to as a second xx script, and similarly, a second xx script may be referred to as a first xx script, without departing from the scope of the present application.

In one embodiment, as shown in fig. 1, a chip package electromagnetic modeling system is provided, which includes a design module and a simulation module:

In the invention, the design module is a 2.5D/3DIC packaging design environment and is used for interconnection among a plurality of Dies on a chip, and comprises a silicon substrate connecting line and a TSV hole. The simulation module is an electromagnetic field interconnection model extraction environment and comprises layout laminated material arrangement, mbump identification (micro bump) and physical routing identification; and setting an electromagnetic field simulation environment for electromagnetic field simulation according to the routing creation port. The combination of the design environment and the simulation environment directly runs simulation in the design environment, and the simulation result is directly checked in the design environment.

In the invention, the chip packaging electromagnetic modeling system unifies the design and simulation environment, realizes the interaction of the simulation tool and the design tool and avoids the complicated data exchange process. The traditional advanced encapsulation electromagnetic field modeling has the problems of cross-domain design and simulation cooperation, and errors can be generated by data interaction under different environments. The invention combines the design tool and the simulation tool, integrates the simulation and the design on one platform through integration, can conveniently embed the simulation analysis flow of the exploration of the design scheme, the verification of the design scheme and the final sign-in the design environment, and greatly reduces the consumption of manpower and time resources.

As shown in FIGS. 2 and 3, in one embodiment, the design module includes a speed design submodule;

the speed design submodule simplifies a three-dimensional structure of chip interconnection, and a first chip package is constructed by adopting a preset transmission routing template;

the simulation module starts an electromagnetic field simplification mode, and carries out simulation on the first chip package in a design environment to obtain a first simulation parameter;

and the speed design submodule adjusts the first chip package according to the first simulation parameter to obtain a second chip package.

In the invention, a simulation program in a simulation module is divided into a plurality of simulation stages according to design; after the simulation program of each simulation stage is finished, a stage simulation result is generated, a user can determine the quality of the design according to the simulation result in each stage, change the design according to the result and then confirm the simulation. The simulation phase has three: a design exploration phase, a design implementation phase, a design completion phase and a final approving phase.

In the embodiment, the speed design submodule and the simulation module implement a design scheme exploration phase. In the exploration stage of the design scheme, the speed design submodule and the simulation module adopt a speed mode and are used for quickly simulating and determining the optimal scheme and the optimal parameters, transmitting the parameters to the design environment and then carrying out optimization adjustment in the design environment.

In the invention, the speed mode carries out necessary simplification on the interconnected three-dimensional structure, and adopts 3-dimensional electromagnetic field improvement processing to improve the speed as much as possible on the premise of ensuring certain precision and meet the requirement of a design scheme exploration stage on time. The three-dimensional structure for simplifying chip interconnection comprises the following three points:

1. the small holes in the metal plane are omitted. Ignoring the small holes in the plane does not cause a large loss in accuracy, but the design and simulation speed is greatly increased.

2. The ground vias are merged. When the signal model is extracted, the simulation efficiency can be greatly reduced by the excessive ground via holes, and the ground via holes far away from the signal line are intelligently combined, so that the precision loss can be avoided, and the simulation efficiency can be improved.

3. And removing the suspended ground network. In a shear design, there may be a floating ground network that causes substantially no precision difference but affects efficiency.

The electromagnetic field simplifying mode is a simplified electromagnetic field, and therefore the efficiency of simulation solving is improved. The method of simplifying the electromagnetic field may be a magnetic flow acceleration technique. The magnetic flow acceleration carries out multi-stage splitting on the solving unit, and the method is a method for effectively accelerating the parameter solving speed.

As shown in fig. 2 and 3, in one embodiment, the design module further includes an equalization design submodule;

the balanced design submodule acquires the second chip package;

the simulation module closes the electromagnetic field simplification mode, and carries out simulation on the second chip package in a design environment to obtain a second simulation parameter;

and the balanced design submodule adjusts the second chip package according to the second simulation parameter to obtain a third chip package.

In an embodiment of the invention, the balanced design submodule and the simulation module implement a design implementation phase. In the implementation stage of the design scheme, the balance design submodule and the simulation module adopt a balance mode, and the electromagnetic field simulation setting is simplified in a similar speed mode, namely, the three-dimensional structure of chip interconnection is simplified, but the magnetic current acceleration is closed, so that the requirements on precision and speed required by real-time simulation result verification in the implementation stage of the scheme are met. In the implementation stage of the design scheme, the design environment adopts the transmitted design parameters to carry out wiring, and the effect of finishing wiring can call the simulation environment in real time to carry out verification.

As shown in fig. 2 and 3, in one embodiment, the design module further includes a precision design submodule;

the accurate design submodule acquires the third chip package, cancels the structural simplification of chip interconnection, refines the chip routing layout of the third chip package and obtains a fourth chip package;

the simulation module closes the electromagnetic field simplification mode, and carries out simulation on the fourth chip package in a design environment to obtain a third simulation parameter;

the accurate design submodule judges whether the fourth chip package meets the requirements or not according to the third simulation parameter, and interaction between a simulation tool and a design tool is realized; if the requirement is not met, the accurate design submodule readjusts the chip routing layout; and if the requirements are met, obtaining the fourth chip package.

In an embodiment of the invention, the precision design submodule and the simulation module implement a design solution completion phase. In the design scheme completion stage, the accurate design submodule and the simulation module adopt an accurate mode, the accuracy requirement is guaranteed to the maximum extent, but the efficiency in the speed aspect is reduced. The precision mode does not simplify the chip three-dimensional connection structure and the electromagnetic field setting.

In the invention, different simulation modes are used for analysis in combination with different stages of the design, so that the requirements of the different stages on the efficiency and the accuracy of an analysis structure are met, real-time interaction can be realized, data exchange and check verification do not need to be carried out between a designer and a simulator, and the method is simple and efficient.

As shown in fig. 2 and fig. 3, in an embodiment, the design module further includes a verification sub-module, where the verification sub-module is configured to determine whether the fourth chip package is the qualified chip package;

the verification sub-module acquires the routing packaged by the fourth chip and judges whether the routing meets the requirement; if the wiring requirement is met, calling the fourth chip package through the simulation module to perform electromagnetic field modeling;

the verification submodule transmits the model result to a time domain simulation tool to verify a time domain waveform and judges whether a time domain eye pattern meets the requirement;

if the judgment requirement of the time domain eye pattern is met, the verification sub-module further performs physical verification on the fourth chip package to judge whether the fourth chip package is qualified;

and if the chip is qualified, the fourth chip package is the qualified chip package.

In the embodiment of the invention, the verification submodule implements a final signing stage, and the final signing stage comprises routing verification, time domain eye waveform diagram verification and physical verification. And calling a finally finished design by the simulation environment, namely performing detailed and accurate electromagnetic field modeling on the fourth chip package, and transmitting a model result to a time domain simulation tool for verifying a time domain waveform. The time domain Simulation tool may be a Simulation circuit Simulator (SPICE) with integrated circuit models.

As shown in fig. 4 to 6, in the practical verification case, the transmission line of the 2.5D silicon interposer is designed and implemented by exploration and model verification, the width of the transmission line is 3um, the length of the transmission line is about 4000um, and the dc resistance of the transmission line is about 30 ohm. Through the final model checking, the IL of the DC point is about-2.4 dB when the frequency domain S parameter is reflected, and the final stable value of the TDR (Time domain reflectometry) is about 80ohm, which accords with the theoretical calculation value.

Wherein IL in FIG. 4 represents insertion loss; RL of FIG. 5 represents Return loss, Return loss; the horizontal axis of fig. 4 and 5 is frequency in GHz and the vertical axis is amplitude in dB.

As shown in fig. 7, the time domain eye meets the eye height and eye width requirement of the HBM2 (High Bandwidth Memory) signal, and meets the verification requirement. The horizontal axis of fig. 7 is time in ns, and the vertical axis is voltage in v.

In one embodiment, as shown in fig. 8, a chip package electromagnetic modeling method is provided, where the chip package electromagnetic modeling method includes:

step S202, obtaining design parameters of the chip package, completing chip layout through a design module, and constructing the first chip package.

Step S204, carrying out simulation on the first chip package in the design environment of the design module to obtain a simulation result.

And S206, optimizing and improving the chip package according to the simulation result, and obtaining the qualified chip package through time domain verification and physical verification of a verification submodule.

In the invention, the design and simulation environments are unified, so that a complex data exchange process is avoided, errors possibly generated due to interaction of data in different environments are avoided, and the consumption of manpower and time resources is reduced.

In one embodiment, as shown in FIG. 9, the method step S202 of constructing the first chip package may specifically include steps S302-S306:

step S302, obtaining design parameters of the first chip package, and realizing chip layout.

And S304, simplifying the three-dimensional structure of chip interconnection through the speed design submodule.

And S306, arranging the wires by adopting a preset transmission wire template to obtain the first chip package.

In the invention, after the layout scheme is finished, the wiring scheme can be researched according to the interconnection length of the layout, and the scheme is explored to meet the requirement. According to the early-stage wiring scheme evaluation, after the wiring scheme is determined, the interconnection parameters are led into the design module, and the design module carries out automatic wiring according to the wiring scheme parameters.

In an embodiment, as shown in fig. 10, the simulation result includes a first simulation parameter, a second simulation parameter, and a third simulation parameter, and the step S204 of obtaining the simulation result through simulation may further include steps S402 to S412:

step S402, starting an electromagnetic field simplification mode, and performing simulation on the first chip package in a design environment to obtain the first simulation parameter.

Step S404, adjusting the first chip package according to the first simulation parameter to obtain a second chip package.

Step S406, closing the electromagnetic field simplification mode, and performing simulation on the second chip package in a design environment to obtain the second simulation parameter.

Step S408, adjusting the second chip package according to the second simulation parameter to obtain a third chip package.

And S410, canceling the simplification of the structure of chip interconnection, and refining the chip routing layout of the third chip package to obtain a fourth chip package.

Step S412, closing the electromagnetic field simplification mode, and performing simulation on the fourth chip package in a design environment to obtain the third simulation parameter.

According to the automatic wiring method, the balance design submodule and the simulation module directly start simulation analysis from a wiring tool by adopting a balance mode according to an automatic wiring result, and whether the requirements are met or not is judged according to a second simulation parameter. And directly adjusting the wiring which does not meet the requirements in the design module, and then directly starting the simulation module to analyze the adjusted result until the result meets the requirements, thereby obtaining the third chip package.

In the invention, the precise design sub-module and the simulation module adopt a precise mode, the structure simplification of chip interconnection is cancelled, the chip wiring layout of the third chip package is refined, and then the fourth chip package is obtained; and (5) closing magnetic current acceleration, and performing simulation on the fourth chip package to obtain a third simulation parameter.

In an embodiment, as shown in fig. 11, the step S206 of obtaining the qualified chip package through verification by the verification sub-module may specifically include steps S502 to S508:

step S502, judging whether the fourth chip package meets the requirements according to the third simulation parameter; if the requirement is not met, readjusting the chip routing layout; and if the requirements are met, obtaining the fourth chip package.

Step S504, obtaining the routing of the fourth chip package, and judging whether the routing meets the requirements; and if the wiring requirement is met, calling the fourth chip package through a simulation module to perform electromagnetic field modeling.

And step S506, the verification submodule transmits the model result to a time domain spice simulation tool to verify the time domain waveform and judge whether the time domain eye diagram meets the requirement.

Step S508, if the judgment requirement of the time domain eye pattern is met, the verification sub-module further performs physical verification on the fourth chip package to judge whether the fourth chip package is qualified; and if the chip is qualified, the fourth chip package is the qualified chip package.

In the invention, after the routing finally meets the interconnection requirement, a simulation tool can be used to see the time domain eye pattern result under the condition of the interconnection model. And (5) completing simulation verification, and completing physical verification of the interconnection routing in a design tool.

As shown in fig. 1, in one embodiment, there is provided a chip-packaged electromagnetic modeling apparatus including a design module and a simulation module:

It should be understood that, although the steps in the flowcharts of the embodiments of the present invention are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in various embodiments may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a non-volatile computer-readable storage medium, and can include the processes of the embodiments of the methods described above when the program is executed. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

All possible combinations of the technical features of the above embodiments may not be described for the sake of brevity, but should be considered as within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. The chip packaging electromagnetic modeling system is characterized by comprising a design module and a simulation module; the design module and the simulation module are integrated in the same platform;

the simulation module carries out simulation on the chip package in the design environment of the design module and transmits the simulation result to the design module;

the design module comprises a speed design submodule, a balance design submodule and an accurate design submodule; the speed design submodule is used for simplifying chip design, the balanced design submodule is used for optimizing chip packaging designed by the speed design submodule, and the accurate design submodule is used for optimizing chip packaging designed by the accurate design submodule.

2. The chip package electromagnetic modeling system of claim 1, wherein the design module includes a speed design sub-module;

3. The chip package electromagnetic modeling system of claim 2, wherein the design module further comprises a balanced design sub-module;

the balanced design submodule acquires the second chip package;

4. The chip package electromagnetic modeling system of claim 3, wherein said design module further comprises a precision design sub-module;

5. The chip package electromagnetic modeling system of claim 4, wherein the design module further comprises a verification sub-module for determining whether the fourth chip package is the qualified chip package;

6. A chip package electromagnetic modeling method is characterized by comprising the following steps:

7. The chip package electromagnetic modeling method of claim 6, wherein the method of constructing the first chip package comprises:

obtaining design parameters of the first chip package to realize chip layout;

simplifying the three-dimensional structure of chip interconnection through a speed design submodule;

arranging wires by adopting a preset transmission wire template to obtain the first chip package;

wherein, the three-dimensional structure simplification of chip interconnection includes: and (4) ignoring the metal plane holes, combining the ground passing holes and removing the suspended ground network.

8. The chip package electromagnetic modeling method of claim 6, wherein the simulation result includes a first simulation parameter, a second simulation parameter, and a third simulation parameter, and the method of obtaining the first simulation parameter, the second simulation parameter, and the third simulation parameter comprises:

starting an electromagnetic field simplification mode, and carrying out simulation on the first chip package in a design environment to obtain the first simulation parameter;

adjusting the first chip package according to the first simulation parameter to obtain a second chip package;

closing the electromagnetic field simplifying mode, and performing simulation on the second chip package in a design environment to obtain a second simulation parameter;

adjusting the second chip package according to the second simulation parameter to obtain a third chip package;

structure simplification of chip interconnection is eliminated, and chip wiring layout of the third chip package is refined to obtain a fourth chip package;

and closing the electromagnetic field simplifying mode, and performing simulation on the fourth chip package in a design environment to obtain the third simulation parameter.

9. The method for electromagnetic modeling of a chip package according to claim 8, wherein the method for obtaining said qualified chip package through verification by a verification sub-module comprises:

judging whether the fourth chip package meets the requirements or not according to the third simulation parameter; if the requirement is not met, readjusting the chip routing layout; if the requirements are met, obtaining the fourth chip package;

obtaining the routing of the fourth chip package, and judging whether the routing meets the requirements; if the wiring requirement is met, calling the fourth chip package through a simulation module to perform electromagnetic field modeling;

10. The chip packaging electromagnetic modeling device is characterized by comprising a design module and a simulation module: