CN114420745B - Silicon carbide MOSFET and preparation method thereof - Google Patents

Abstract

The invention belongs to the technical field of power devices and provides a silicon carbide MOSFET and a preparation method thereof.

Description

A kind of silicon carbide MOSFET and preparation method thereof

technical field

The invention belongs to the technical field of power devices, and in particular relates to a silicon carbide MOSFET and a preparation method thereof.

Background technique

Silicon carbide MOSFET has the characteristics of high frequency and high power density. As a power device, it can greatly reduce the volume of the power supply and improve the conversion efficiency of the power supply. Therefore, it has broad application prospects.

Silicon carbide MOSFETs mainly have two structures, planar and trench. Due to the low channel mobility of planar silicon carbide MOSFETs, its current density is lower than that of trench silicon carbide MOSFETs. However, in the existing trench structure silicon carbide In MOSFETs, the electric field strength at the corners of the trenches is relatively large, and breakdown is prone to occur, which greatly affects the stability of the trench-structured silicon carbide MOSFETs.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a silicon carbide MOSFET and a preparation method thereof, aiming at solving the problem of poor stability of the existing trench structure silicon carbide MOSFET.

A first aspect of the present invention provides a silicon carbide MOSFET, and the silicon carbide MOSFET includes:

Silicon carbide substrate;

A silicon carbide epitaxial layer, both the silicon carbide epitaxial layer and the silicon carbide substrate are doped with first-type doping ions, and the doping concentration of the silicon carbide epitaxial layer is smaller than that of the silicon carbide substrate concentration;

A first well region, disposed in the deep groove on the upper surface of the silicon carbide epitaxial layer, the first well region includes a first lateral well region and a first vertical well region, wherein the first lateral well region is connected to the The first vertical well region constitutes a T-type structure doped with the second type of doping ions, and the doping concentration of the first lateral well region is greater than the doping concentration of the first vertical well region;

The second well region is disposed on the silicon carbide epitaxial layer, the second well region includes two second lateral well regions and one second vertical well region, wherein the two second lateral well regions are disposed in on both sides of the second vertical well region, and the doping concentration of the second vertical well region is greater than the doping concentration of the second lateral well region;

a first gate oxide layer and a second gate oxide layer, the first gate oxide layer and the second gate oxide layer have a concave structure and are respectively disposed on both sides of the first vertical well region;

a first polysilicon and a second polysilicon, the first polysilicon and the second polysilicon are respectively disposed in the concave regions of the first gate oxide layer and the second gate oxide layer;

an insulating protection layer disposed on the first polysilicon and the second polysilicon;

The source region is disposed on the second lateral well region, wherein the second lateral well region and the first lateral well region are respectively disposed on the bottom edge and the side edge of the first gate oxide layer.

In one embodiment, the depth of the first lateral well region is greater than the width of the first vertical well region.

In one embodiment, the width of the first lateral well region is smaller than the width of the recessed region of the first gate oxide layer.

In one embodiment, the depth of the second vertical well region is greater than the depth of the second lateral well region.

In one embodiment, the upper surface of the source region is flush with the upper surface of the second longitudinal well region.

A second aspect of the present invention also provides a preparation method of a silicon carbide MOSFET, the preparation method comprising:

A silicon carbide epitaxial layer is formed on the silicon carbide substrate, wherein both the silicon carbide epitaxial layer and the silicon carbide substrate are doped with first type dopant ions, and the silicon carbide epitaxial layer is doped with doping ions of the first type. The concentration is less than the doping concentration of the silicon carbide substrate;

A well region doped layer doped with the second type of doping ions is formed on the silicon carbide epitaxial layer, and a first etch mask layer is formed on the well region doped layer, wherein the first etch A plurality of trenches are arranged on the etching mask layer;

forming a buffer layer on the sidewall of each of the trenches on the first etch mask layer;

forming a silicon nitride filling layer in each of the trenches on the first etch mask layer, and depositing a metal mask layer on the first etch mask layer;

selectively etching the metal mask layer, the first etching mask layer, the buffer layer and the silicon nitride to expose a preset first well region, wherein the the central position of the first well region is covered by the silicon nitride filling layer;

etching the first well region to form a deep groove in the well region, wherein the depth of the deep groove in the well region is greater than the depth of the doped layer in the well region;

forming an implantation barrier layer on the deep trench in the well region and the metal mask layer;

etching the implantation barrier layer to expose the first well region doped region and the second well region doped region;

Doping ions of the second type are implanted in the first well region doping region and the second well region doping region to form a first lateral well region in the silicon carbide epitaxial layer, and doping in the well region The impurity layer forms a second vertical well region, wherein the doping concentration of the first lateral well region and the second vertical well region is greater than the doping concentration of the well region doping layer;

removing the implantation barrier layer and the buffer layer to obtain a first well region and a second well region, wherein the first well region includes the first lateral well region and a first vertical well region, the first lateral well region The well region and the first vertical well region form a T-type structure doped with second-type doping ions, the second well region includes two second lateral well regions and one of the second vertical well regions, and the two two of the second lateral well regions are disposed on both sides of the second vertical well region;

depositing a gate oxide material to form a first gate oxide layer and a second gate oxide layer, the first gate oxide layer and the second gate oxide layer have a concave structure and are respectively disposed on the first vertical well region both sides;

implanting first type dopant ions into the second lateral well region and depositing a carbon film followed by annealing treatment to form a source region on the second lateral well region;

depositing polysilicon to form a first polysilicon and a second polysilicon in the concave regions of the first gate oxide layer and the second gate oxide layer, respectively, and forming a first polysilicon and a second polysilicon in the first polysilicon and the second An insulating protective layer is formed on the polysilicon.

In one embodiment, forming a buffer layer on the sidewalls of each of the trenches on the first etch mask layer includes:

depositing silicon dioxide on the first etch mask layer as a pre-buffer layer;

Dry etching is performed on the pre-buffer layer to form a buffer layer on the inner wall of each trench.

In one embodiment, the silicon nitride is filled in each of the trenches on the first etch mask layer, and a metal mask layer is deposited on the first etch mask layer, include:

Silicon nitride is deposited on the first etch mask layer to form a silicon nitride layer, and the silicon nitride layer is etched until the buffer layer on the sidewall of the trench and the nitrogen in the filling hole Silicone flush;

A metal mask layer is formed by depositing metal on the first etch mask layer.

In one embodiment, the etching of the implantation barrier layer to expose the first well region doped region and the second well region doped region includes:

etching the implantation barrier layer in the deep groove of the well region to form the first well region doped region, wherein the widths of the first well region doped regions on both sides of the silicon nitride filling layer are equal;

The implantation barrier layer on the metal mask layer and the first etch mask layer are etched to form the second well region doped region on the well region doped layer.

In one embodiment, the forming the second vertical well region in the well region doped layer includes:

The second type of doping ions are implanted into the well region doping layer through the second well region doping region to form the second vertical well region, wherein the depth of the second vertical well region is greater than that of the well region the depth of the doped layer.

The present invention provides a silicon carbide MOSFET and a preparation method thereof. By forming a first well region and a second well region on both sides of a first gate oxide layer and a second gate oxide layer respectively, the first well region in the first well region The lateral well region and the first vertical well region form a T-type structure doped with doping ions of the second type, and the doping concentration of the first lateral well region is greater than the doping concentration of the first vertical well region, and the second well region has a doping concentration. The two second lateral well regions are arranged on both sides of the second vertical well region, and the doping concentration of the second vertical well region is greater than the doping concentration of the second lateral well region, thereby ensuring the depletion length of the MOSFET and ensuring its Fully depleted, the electric field strength at the corners of the trench is weakened, and the stability of the silicon carbide MOSFET is improved.

Description of drawings

FIG. 1 is a schematic structural diagram of a silicon carbide MOSFET provided by an embodiment of the present invention.

2 is a schematic flowchart of a method for preparing a silicon carbide MOSFET according to an embodiment of the present invention;

3 is an exemplary diagram of forming a first etching mask layer on the well region doped layer provided by an embodiment of the present invention;

4 is an exemplary diagram of forming a buffer layer provided by an embodiment of the present invention;

5 is an exemplary diagram of forming a silicon nitride filling layer and a metal mask layer according to an embodiment of the present invention;

6 is an exemplary diagram of selectively etching a metal mask layer provided by an embodiment of the present invention;

7 is an exemplary diagram of forming a deep trench in a well region provided by an embodiment of the present invention;

8 is an exemplary diagram of forming an implantation barrier layer provided by an embodiment of the present invention;

9 is an exemplary diagram of etching the implantation barrier layer provided by an embodiment of the present invention;

10 is an exemplary diagram of forming a first lateral well region and a second vertical well region provided by an embodiment of the present invention;

11 is an exemplary diagram of a first well region and a second well region provided by an embodiment of the present invention;

12 is an exemplary diagram of forming a source region provided by an embodiment of the present invention;

13 is an exemplary diagram of forming a gate oxide layer and polysilicon provided by an embodiment of the present invention;

FIG. 14 is an exemplary diagram of forming an insulating protective layer according to an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

It is to be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top" , "bottom", "inside", "outside", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, which are only for the convenience of describing the application and simplifying the description, rather than indicating or implying the indicated device. Or elements must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as a limitation of the present application.

In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as "first" or "second" may expressly or implicitly include one or more of that feature. In the description of the present application, "plurality" means two or more, unless otherwise expressly and specifically defined.

An embodiment of the present invention provides a silicon carbide MOSFET. Referring to FIG. 1, the silicon carbide MOSFET includes: a silicon carbide substrate 100, a silicon carbide epitaxial layer 200, a first well region 300, a second well region 500, and a first gate The oxide layer 410 , the second gate oxide layer 420 , the first polysilicon 610 , the second polysilicon 620 , the insulating protection layer 710 and the source region 810 .

Specifically, both the silicon carbide epitaxial layer 200 and the silicon carbide substrate 100 are doped with the first type of doping ions, and the doping concentration of the silicon carbide epitaxial layer 200 is lower than that of the silicon carbide substrate 100 .

The first well region 300 is disposed in the deep groove on the upper surface of the silicon carbide epitaxial layer 200 , and the first well region 300 includes a first lateral well region 310 and a first vertical well region 320 , wherein the first lateral well region 310 and the first The vertical well region 320 forms a T-type structure doped with the second type of doping ions. The T-type structure is an inverted T-type configuration in the device, and its bottom edge (ie, the first lateral well region 310 ) is connected to the silicon carbide epitaxial layer 200 . contact, the protruding structure (ie, the first vertical well region 320 ) is in contact with the insulating protection layer 710 , and the doping concentration of the first lateral well region 310 is greater than that of the first vertical well region 320 .

Specifically, the type of the second type of doping ions is different from that of the first type of doping ions. For example, the second type of doping ions is P-type doping, the first type of doping ions is N-type doping, or, The second type of doping ions is N-type doping, and the first type of doping ions is P-type doping.

The second well region 500 is disposed on the silicon carbide epitaxial layer 200 and is disposed on the side of the first gate oxide layer 410. The second well region 500 includes two second lateral well regions 520 and one second vertical well region 510. The two second lateral well regions 520 are disposed on both sides of the second vertical well region 510 , and the doping concentration of the second vertical well region 510 is greater than the doping concentration of the second lateral well region 520 .

The first gate oxide layer 410 and the second gate oxide layer 420 have a concave structure and are respectively disposed on both sides of the first vertical well region 320. The first well region 300 and the second well region 500 are respectively disposed in the first gate oxide layer. On both sides of the layer 410, the first lateral well region 310 in the first well region 300 is disposed on the bottom side of the first gate oxide layer 410, and the second lateral well region 520 is disposed on the side of the first gate oxide layer 410, And a corner of the first gate oxide layer 410 is disposed between the first lateral well region 310 and the second lateral well region 520 .

The first polysilicon 610 and the second polysilicon 620 are respectively disposed in the concave regions of the first gate oxide layer 410 and the second gate oxide layer 420 .

The insulating protection layer 710 is disposed on the first polysilicon 610 and the second polysilicon 620, and the source region 810 is disposed on the second lateral well region 520, wherein the second lateral well region 520 is connected to the first lateral well region 520. The well regions 310 are respectively disposed on the bottom side and the side side of the first gate oxide layer 410 .

In this embodiment, as shown in FIG. 1 , the first well region 300 has an inverted T-type structure, and the first lateral well region 310 located at the bottom of the inverted T-type structure is a heavily doped region with a doping concentration greater than that of the first lateral well region 310 at the bottom of the inverted T-type structure. For the doping concentration of a vertical well region 320, since the first lateral well region 310 is a lateral structure, its heavily doped characteristic can ensure sufficient depletion length.

The second well region 500 is disposed on the side of the first gate oxide layer 410 , wherein the doping concentration of the second vertical well region 510 in the second well region 500 is greater than the doping concentration of the second lateral well region 520 . , a depletion is formed between the first lateral well region 310 and the second vertical well region 510. By pinching off the electric field at the corners of the first gate oxide layer 410, the influence of the electric field strength on the gate oxide at the corners of the first gate oxide layer 410 can be reduced to achieve protection The effect of gate oxide, preventing it from being broken down.

Similarly, as shown in FIG. 1 , if two unit cells are included in the same power chip, a second well region 500 is provided between the adjacent unit cells, which can jointly realize the depletion of the sidewall trenches and reduce the Effect of electric field strength on trench corners.

In one embodiment, the first-type dopant ions doped in the silicon carbide epitaxial layer 200 and the silicon carbide substrate 100 may be N-type dopant ions, such as aluminum ions, boron ions, and the like.

In one embodiment, the second-type dopant ions doped in the first well region 300 and the second well region 500 may be P-type dopant ions, such as phosphorus ions, nitrogen ions, and the like.

In one embodiment, referring to FIG. 1 , the depth of the first lateral well region 310 is greater than the width of the first vertical well region 320 .

Specifically, as shown in FIG. 1 , the first vertical well region 320 is a vertical structure with a narrow lateral width, which can be used to isolate the first gate oxide layer 410 and the second gate oxide layer 420 . The region 310 may be formed by implanting the second type dopant ions into the silicon carbide epitaxial layer 200, the implantation depth of the second type dopant ions determines the depth of the first lateral well region 310, and the width of the first vertical well region 320 may be determined by etching. Mask layers are defined. In one embodiment, as shown in FIG. 1 , the width of the first lateral well region 310 is smaller than the width of the recessed region of the first gate oxide layer 410 .

Specifically, the first lateral well region 310 is disposed on the bottom edge of the first gate oxide layer 410 , and its width is smaller than the length of the bottom edge of the first gate oxide layer 410 , and the second lateral well region 520 is disposed on the bottom edge of the first gate oxide layer 410 . On the side, a corner of the first gate oxide layer 410 is disposed between the first lateral well region 310 and the second lateral well region 520 , and the thickness of the second lateral well region 520 is smaller than the length of the side of the first gate oxide layer 410 .

In one embodiment, the first vertical well region 320 is set at the position of the axis centerline of the first transverse well region 310 , with the first vertical well region 320 as the center axis, the widths of the first transverse well regions 310 on both sides thereof are the same, And the widths of the first lateral well regions 310 on both sides thereof are smaller than the widths of the gate oxide layers (the first gate oxide layer 410 and the second gate oxide layer 420 ) on both sides thereof.

In one embodiment, with the first vertical well region 320 as the central axis, the widths of the first lateral well regions 310 on both sides thereof are the same, and the widths of the first lateral well regions 310 on both sides thereof are the gates on both sides thereof Half the width of the oxide layers (first gate oxide 410 and second gate oxide 420).

In one embodiment, the depth of the second vertical well region 510 is greater than the depth of the second lateral well region 520 .

In the second well region 500 , the doping concentration of the second vertical well region 510 is greater than the doping concentration of the second lateral well region 520 , the second lateral well regions 520 are provided on both sides of the second vertical well region 510 , and The thicknesses of the second lateral well regions 520 on both sides are the same. By setting the depth of the second vertical well region 510 to be greater than the depth of the second lateral well region 520, the second well region 500 can be set to a T-type structure. The second lateral well region 520 is located above and on both sides of the second vertical well region 510 , and the second lateral well region 520 with a higher doping concentration can ensure complete depletion of the lower portion, so as to realize the electric field at the corner of the first gate oxide layer 410 weakening of strength.

In one embodiment, the upper surface of the source region 810 is flush with the upper surface of the second longitudinal well region 510 .

In this embodiment, source regions 810 are provided on both sides of the second vertical well region 510 , and the upper surface of the source region 810 is flush with the upper surface of the second vertical well region 510 .

In one embodiment, the insulating protective layer 710 is provided with a contact hole, and a gate electrode connected to the first polysilicon 610 and the second polysilicon 620 is formed on the insulating protective layer 710 by filling the electrode metal in the contact hole.

In one embodiment, the first well region 300 is connected to the second lateral well region 520 through peripheral vias, and serves as the source of the silicon carbide MOSFET.

An embodiment of the present application further provides a method for manufacturing a silicon carbide MOSFET. Referring to FIG. 2 , the manufacturing method in this embodiment includes steps S101 to S113 .

In step S101, a silicon carbide epitaxial layer is formed on the silicon carbide substrate.

Wherein, both the silicon carbide epitaxial layer and the silicon carbide substrate are doped with first-type doping ions, and the doping concentration of the silicon carbide epitaxial layer is lower than the doping concentration of the silicon carbide substrate.

In step S102, a well region doped layer doped with the second type dopant ions is formed on the silicon carbide epitaxial layer, and a first etching mask layer is formed on the well region doped layer, wherein, A plurality of trenches are provided on the first etching mask layer.

3, the silicon carbide epitaxial layer 200 is disposed on the silicon carbide substrate 100. At this time, the silicon carbide epitaxial layer 200 and the silicon carbide substrate 100 are both doped with the first type of doping ions. The doping concentration of the layer 200 is lower than the doping concentration of the silicon carbide substrate 100, the well region doping layer 330 is provided on the silicon carbide epitaxial layer 200, the first etching mask layer 340 is provided on the well region doping layer 330, And a plurality of trenches are formed on the first etching mask layer 340 .

Specifically, the well region doped layer 330 can be formed on the upper surface of the silicon carbide epitaxial layer 200 by means of epitaxy or ion implantation, and then a plurality of trenches are formed by selective etching with photoresist, and the plurality of trenches are arranged in an array , the distance between adjacent grooves is the same, and the dimensions of multiple grooves are the same.

In a specific application, the type of the second type of doping ions is different from that of the first type of doping ions, for example, the second type of doping ions is P-type doping, the first type of doping ions is N-type doping, Alternatively, the second type of doping ions are N-type doping, and the first type of doping ions are P-type doping.

In one embodiment, the first-type dopant ions doped in the silicon carbide epitaxial layer 200 and the silicon carbide substrate 100 may be N-type dopant ions, such as aluminum ions, boron ions, and the like.

In one embodiment, the second-type dopant ions doped in the first well region 300 and the second well region 500 may be P-type dopant ions, such as phosphorus ions, nitrogen ions, and the like.

In one embodiment, the first etch mask layer 340 can be a silicon nitride layer, and the silicon nitride layer can be selectively etched by using a photoresist to form a plurality of trenches on the silicon nitride layer .

In step S103, a buffer layer is formed on the sidewall of each of the trenches on the first etch mask layer.

With reference to FIG. 4 , a buffer layer 350 is formed in each trench on the first etching mask layer 340 to provide protection for the subsequent etching process and prevent the etching solution from affecting the well region doping layer 330 of the non-etched areas.

In one embodiment, in step S103, forming a buffer layer on the sidewall of each of the trenches on the first etch mask layer includes:

Step S103-1: depositing silicon dioxide on the first etching mask layer as a pre-buffer layer;

Step S103-2: dry etching the pre-buffer layer to form a buffer layer on the inner wall of each trench.

Specifically, a pre-buffer layer can be formed by depositing silicon dioxide on the first etch mask layer 340, and then the pre-buffer layer is subjected to dry etching without a mask layer to remove the first etch mask layer 340. silicon dioxide on the surface, so that unfilled holes are formed in each trench, and at this time, unetched silicon dioxide can be formed on the inner wall of each trench as a buffer layer 350 , as shown in FIG. 4 .

In step S104, a silicon nitride filling layer is formed in each of the trenches on the first etching mask layer, and a metal mask layer is deposited on the first etching mask layer.

In this embodiment, as shown in FIG. 5 , a photoresist may be used as a mask, and then silicon nitride is deposited to form a silicon nitride filling layer 360 in each trench, or a The sequence of silicon nitride forms a silicon nitride fill layer 360 within each trench, and a metal mask layer 370 is deposited on the first etch mask layer 340 after the silicon nitride fill layer 360 is formed.

In one embodiment, in step S104, silicon nitride is filled in each of the trenches on the first etching mask layer, and a metal mask is deposited on the first etching mask layer Membrane layers, including:

Step S104-1: depositing silicon nitride on the first etching mask layer to form a silicon nitride layer, and etching the silicon nitride layer until the buffer layer on the sidewall of the trench and the The silicon nitride in the filled hole is flush;

Step S104-2: depositing metal on the first etching mask layer to form a metal mask layer.

In this embodiment, a silicon nitride layer is formed by depositing silicon nitride on the first etch mask layer 340, and the silicon nitride layer is not only filled in the filling holes formed by the buffer layer 350, but also exists in the first The mask layer and the buffer layer 350 are etched by dry etching without a mask until the upper surface of the buffer layer 350 is exposed, and then a metal mask layer is deposited on the first etching mask layer 340 .

In one embodiment, a metal nickel layer may be formed as the metal mask layer 370 by depositing metal nickel on the first etch mask layer 340 .

In one embodiment, the thickness of the metal mask layer 370 may be 1-5um.

In step S105, selective etching is performed on the metal mask layer, the first etching mask layer, the buffer layer and the silicon nitride to expose a predetermined first well region , wherein the central position of the first well region is covered by the silicon nitride filling layer.

In this embodiment, as shown in FIG. 6 , by selectively etching the metal mask layer 370 , a preset first well region region, such as the first etching region 401 and the second well region in FIG. 6 , can be exposed. Etching region 402, the first well region is disposed around the silicon nitride filling layer 360, and at this time, the silicon nitride filling layer 360 can be used as a subsequent etching mask.

In a specific application, the first well region can be defined by forming a photoresist on the metal mask layer 370, and then dry etching is performed on the metal mask layer 370 to expose the silicon nitride filling layer 360 covered by the metal mask layer 370. And the buffer layer 350, since the buffer layer 350 is silicon dioxide, the wet etching of silicon nitride can be performed first under the protection of photoresist to etch away the exposed silicon nitride filling layer 360, and then the silicon nitride can be etched. In the wet etching process, due to the protection of the photoresist and the silicon nitride filling layer 360 , the exposed silicon dioxide is also etched away to obtain the structure shown in FIG. 6 .

Further, part of the metal mask layer 370 can also be etched away in the process of etching silicon dioxide with hydrofluoric acid, and the use of hydrofluoric acid can prevent it from reacting with the doping layer 330 in the well region and protect the doping layer in the well region. 330 is not affected.

In step S106, the first well region is etched to form a deep trench in the well region, wherein the depth of the deep trench in the well region is greater than the depth of the doped layer in the well region.

In this embodiment, as shown in FIG. 7 , using the silicon nitride filling layer 360 exposed in step S105 as a mask, the first well region is etched to form a deep trench in the well region (the first deep trench 411 and the first deep trench 411 and the Two deep trenches 412 ), the deep trenches in the well region surround the exposed silicon nitride filling layer 360 , and the depth of the deep trenches in the well region is greater than the depth of the doping layer 330 in the well region.

In one embodiment, the distance between the bottom surfaces of the first deep trench 411 and the second deep trench 412 and the lower surface of the well region doping layer 330 is smaller than the thickness of the well region doping layer 330 .

In step S107, an implantation barrier layer is formed on the deep trench in the well region and the metal mask layer.

Referring to FIG. 8 , an implantation barrier material is filled in the deep trenches in the well region to form an implantation barrier layer 380 . The implantation barrier layer 380 not only fills the deep trenches in the well region, but also covers the metal mask layer 370 .

In one embodiment, the implant barrier material may be silicon dioxide.

In step S108, the implantation barrier layer is etched to expose the first well region doped region and the second well region doped region.

As shown in FIG. 9 , the etching region of the implantation barrier layer 380 may be defined by photoresist, and then the implantation barrier layer 380 may be etched, thereby exposing the doping region of the first well region (see the first doping region in FIG. 9 ) impurity region 381 and second impurity region 382 ) and second well region impurity region (see third impurity region 383 in FIG. 9 ).

Specifically, the first well region doped region is located on the surface of the silicon carbide epitaxial layer 200 , and the second well region doped region is located on the surface of the well region doped layer 330 .

In one embodiment, in step S108, the implantation barrier layer is etched to expose the first well region doped region and the second well region doped region, including:

Step S108-1: Etch the implantation barrier layer in the deep groove of the well region to form the first well region doped region, wherein the first well region on both sides of the silicon nitride filling layer is doped The widths of the regions are equal;

Step S108-2: Etching the implantation barrier layer on the metal mask layer and the first etching mask layer to form the second well region doping layer on the well region doping layer area.

In this embodiment, by etching the implantation barrier layer 380 in the deep groove of the well region, the first well region doped region is exposed on both sides of the silicon nitride filling layer 360, and the first well region on both sides of the first well region is exposed. The widths of the doped regions are equal, and the position of the second well region doped region is defined by the photoresist, and the metal mask layer 370, the implantation barrier layer 380 and the first etch mask layer 350 are etched to A second well doped region is formed on the well doped layer 330 .

In step S109, implanting second type doping ions into the first well region doping region and the second well region doping region to form a first lateral well region in the silicon carbide epitaxial layer, The well region doping layer forms a second vertical well region, wherein the doping concentration of the first lateral well region and the second vertical well region is greater than the doping concentration of the well region doping layer.

With reference to FIG. 10 , under the cover of the implantation barrier layer 380 , the second type dopant ions are implanted into the doping region of the first well region, thereby forming a first lateral well region 310 in the silicon carbide epitaxial layer 200 , and in the second well region doped region 310 is formed. Doping ions of the second type are implanted into the doped region of the well region, thereby forming a second vertical well region 510 in the doped well region 330, wherein the doping concentrations of the first lateral well region 310 and the second vertical well region 510 are It is greater than the doping concentration of the well region doping layer 330 .

In one embodiment, the second type of dopant ions implanted into the first well region doping region and the second well region doping region may be aluminum ions.

In one embodiment, in step S109, forming a second vertical well region in the well region doping layer includes: implanting a second type dopant into the well region doping layer through the second well region doping region impurity ions to form the second vertical well region, wherein the depth of the second vertical well region is greater than the depth of the well region doped layer.

Specifically, as shown in FIG. 10 , the second type of doping ions are implanted into the well region doping layer 330 through the second well region doping region, so as to form a second type doping ion in the well region doping layer 330 and the silicon carbide epitaxial layer 200 . The vertical well region 510 , the second vertical well region 510 divides the well region doped layer 330 into second lateral well regions 520 with the same size and a depth greater than that of the well region doped layer 330 .

In step S110, the implantation barrier layer and the buffer layer are removed to obtain a first well region and a second well region.

Wherein, the first well region includes the first lateral well region and the first vertical well region, and the first lateral well region and the first vertical well region form T doped with the second type of doping ions type structure, the second well region includes two second lateral well regions and one of the second vertical well regions, and the two second lateral well regions are arranged on both sides of the second vertical well region.

In this embodiment, as shown in FIG. 11 , after removing the implant barrier layer 380 , the silicon nitride filling layer 360 , the buffer layer 350 and the first etching mask layer 340 , the device is annealed to obtain the first well region and a second well region, wherein the first well region includes a first lateral well region 310 and a first vertical well region 320, and the first lateral well region 310 and the first vertical well region 320 are composed of doped second-type doping ions The T-type structure is an inverted T-type structure in the device, and its bottom edge (ie, the first lateral well region 310 ) is in contact with the silicon carbide epitaxial layer 200 , and its raised structure (ie, the first vertical well region 320 ) is in contact with the silicon carbide epitaxial layer 200 . ) is in contact with the insulating protection layer 710 , and the doping concentration of the first lateral well region 310 is greater than that of the first vertical well region 320 .

The second well region includes two second lateral well regions 520 and one second vertical well region 510. The two second lateral well regions 520 are disposed on both sides of the second vertical well region 510, and the second vertical well region 510 is doped with The impurity concentration is greater than that of the second lateral well region 520 .

In step S111 , dopant ions of the first type are implanted into the second lateral well region, and a carbon film is deposited and then annealed to form a source region on the second lateral well region.

In this embodiment, the area exposed to the second lateral well region 520 may be covered with photoresist, and then the first type of dopant ions are implanted into the second lateral well region 520, and then the photoresist is removed, and a carbon film is used to cover the entire area In the device, the carbon film is protected and the device is annealed, thereby forming a source region 810 on the second lateral well region 520, as shown in FIG. 12 . By covering the device with a carbon film, dangling bonds in silicon due to silicon carbide mismatches during annealing can be avoided.

Further, in step S109, the first lateral well region 310 is doped with the second type dopant ions, and in the case of annealing, the second type dopant ions can diffuse into the first vertical well region 320, so that the first vertical well The vertical structure between the well region doping layer 330 and the silicon carbide epitaxial layer 200 in the region 320 is doped with the second type dopant ions.

In step S112 , depositing a gate oxide material to form a first gate oxide layer and a second gate oxide layer, the first gate oxide layer and the second gate oxide layer have a concave structure and are respectively disposed on the first gate oxide layer and the second gate oxide layer. Both sides of a longitudinal well region.

Referring to FIG. 13 , by depositing gate oxide material or oxidizing the bottom and sidewalls of the body side in the trench formed by the first well region, it can be formed on both sides of the first vertical well region 320 in the first well region respectively The first gate oxide layer 410 and the second gate oxide layer 420 of the concave structure. Referring to FIG. 13 , the second lateral well region 520 and the first lateral well region 310 are respectively disposed on the bottom side and the side side of the first gate oxide layer 410 .

In one embodiment, the first vertical well region 320 is set at the position of the axis centerline of the first transverse well region 310 , with the first vertical well region 320 as the center axis, the widths of the first transverse well regions 310 on both sides thereof are the same, And the widths of the first lateral well regions 310 on both sides thereof are smaller than the widths of the gate oxide layers (the first gate oxide layer 410 and the second gate oxide layer 420 ) on both sides thereof.

In step S113, polysilicon is deposited to form a first polysilicon and a second polysilicon in the concave regions of the first gate oxide layer and the second gate oxide layer, respectively, and the first polysilicon is deposited on the first polysilicon. and forming an insulating protective layer on the second polysilicon.

In this embodiment, as shown in FIG. 13 , by depositing polysilicon material, a first polysilicon is formed in the concave area of the first gate oxide layer 410 , and a second polysilicon is formed in the concave area of the second gate oxide layer 420 , respectively. polysilicon.

In this embodiment, as shown in FIG. 14 , an insulating protection layer 710 is formed on the first polysilicon 610 and the second polysilicon 620 by depositing an insulating material.

Specifically, the first lateral well region 310 is disposed on the bottom edge of the first gate oxide layer 410 , and its width is smaller than the length of the bottom edge of the first gate oxide layer 410 , and the second lateral well region 520 is disposed on the bottom edge of the first gate oxide layer 410 . On the side, a corner of the first gate oxide layer 410 is disposed between the first lateral well region 310 and the second lateral well region 520, and the thickness of the second lateral well region 520 is smaller than the length of the side of the first gate oxide layer 410, At this time, depletion is formed between the first lateral well region 310 and the second vertical well region 510. By pinching off the electric field at the corner of the first gate oxide layer 410, the influence of the electric field strength on the gate oxide at the corner can be reduced. The effect of protecting the gate oxide layer and preventing it from being broken down is achieved.

Further, in one embodiment, the insulating protection layer 710 is selectively etched to form a plurality of contact holes, respectively exposing the second lateral well region 520 and the polysilicon (the first polysilicon 610 and the second polysilicon 620 ). ) and the first well region 300, then by depositing metal and etching the metal, the polysilicon is connected to the gate electrode, the first well region 300 is connected to the second lateral well region 520 through the peripheral metal wiring, as the source of the silicon carbide MOSFET .

The present invention provides a silicon carbide MOSFET and a preparation method thereof. By forming a first well region and a second well region on both sides of a first gate oxide layer and a second gate oxide layer respectively, the first well region in the first well region The lateral well region and the first vertical well region form a T-type structure doped with doping ions of the second type, and the doping concentration of the first lateral well region is greater than the doping concentration of the first vertical well region, and the second well region has a doping concentration. The two second lateral well regions are arranged on both sides of the second vertical well region, and the doping concentration of the second vertical well region is greater than that of the second lateral well region, thereby ensuring the depletion length of the MOSFET and ensuring its Fully depleted, the electric field strength at the corners of the trench is weakened, and the stability of the silicon carbide MOSFET is improved.

Those skilled in the art can clearly understand that, for the convenience and brevity of the description, only the division of the above-mentioned doped regions is used as an example. Completion, that is, dividing the internal structure of the device into different doped regions, so as to complete all or part of the functions described above.

Each doped region in the embodiment may be integrated into one functional region, or each doped region may exist physically alone, or two or more doped regions may be integrated into one functional region. The above-mentioned integrated functional region It can be realized by using the same kind of doping ions, or it can be realized by using a variety of doping ions together. In addition, the specific names of the doped regions are only for the convenience of distinguishing from each other, and are not used to limit the protection scope of the present application. For the specific working process of the middle-doped region in the above-mentioned device fabrication method, reference may be made to the corresponding process in the foregoing method embodiments, which will not be repeated here.

The above-mentioned embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be used for the foregoing implementations. The technical solutions described in the examples are modified, or some technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the within the protection scope of the present invention.

Claims (10)

1. a preparation method of silicon carbide MOSFET, is characterized in that, described preparation method comprises: A silicon carbide epitaxial layer is formed on a silicon carbide substrate, wherein both the silicon carbide epitaxial layer and the silicon carbide substrate are doped with first-type doping ions, and the doping concentration of the silicon carbide epitaxial layer is less than the doping concentration of the silicon carbide substrate; A well region doped layer doped with the second type of doping ions is formed on the silicon carbide epitaxial layer, and a first etch mask layer is formed on the well region doped layer, wherein the first etch A plurality of trenches are arranged on the etching mask layer; forming a buffer layer on the sidewall of each of the trenches on the first etch mask layer; forming a silicon nitride filling layer in each of the trenches on the first etch mask layer, and depositing a metal mask layer on the first etch mask layer; selectively etching the metal mask layer, the first etching mask layer, the buffer layer and the silicon nitride to expose a preset first well region, wherein the the central position of the first well region is covered by the silicon nitride filling layer; etching the first well region to form a deep groove in the well region, wherein the depth of the deep groove in the well region is greater than the depth of the doped layer in the well region; forming an implantation barrier layer on the deep trench in the well region and the metal mask layer; etching the implantation barrier layer to expose the first well region doped region and the second well region doped region; Doping ions of the second type are implanted in the first well region doping region and the second well region doping region to form a first lateral well region in the silicon carbide epitaxial layer, and doping in the well region The impurity layer forms a second vertical well region, wherein the doping concentration of the first lateral well region and the second vertical well region is greater than the doping concentration of the well region doping layer; removing the implantation barrier layer and the buffer layer to obtain a first well region and a second well region, wherein the first well region includes the first lateral well region and a first vertical well region, the first lateral well region The well region and the first vertical well region form a T-type structure doped with second-type doping ions, the second well region includes two second lateral well regions and one of the second vertical well regions, and the two two of the second lateral well regions are disposed on both sides of the second vertical well region; implanting first type dopant ions into the second lateral well region and depositing a carbon film followed by annealing treatment to form a source region on the second lateral well region; depositing a gate oxide material to form a first gate oxide layer and a second gate oxide layer, the first gate oxide layer and the second gate oxide layer have a concave structure and are respectively disposed on the first vertical well region two sides; wherein, the second lateral well region and the first lateral well region are respectively disposed on the bottom edge and the side edge of the first gate oxide layer; depositing polysilicon to form a first polysilicon and a second polysilicon in the concave regions of the first gate oxide layer and the second gate oxide layer, respectively, and forming a first polysilicon and a second polysilicon in the first polysilicon and the second An insulating protective layer is formed on the polysilicon, wherein the insulating protective layer also covers the surface of the first vertical well region. 2. The preparation method according to claim 1, wherein forming a buffer layer on the sidewall of each trench on the first etch mask layer comprises: depositing silicon dioxide on the first etch mask layer as a pre-buffer layer; Dry etching is performed on the pre-buffer layer to form a buffer layer on the inner wall of each trench. 3 . The preparation method according to claim 1 , wherein, silicon nitride is filled in each of the trenches on the first etching mask layer, and the first etching process is performed in the first etching process. 4 . A metal mask layer is deposited on the mask layer, including: Silicon nitride is deposited on the first etch mask layer to form a silicon nitride layer, and the silicon nitride layer is etched until the buffer layer on the sidewall of the trench and the silicon nitride in the filling hole flush; A metal mask layer is formed by depositing metal on the first etch mask layer. 4. The preparation method according to claim 1, wherein the etching the implantation barrier layer to expose the first well region doped region and the second well region doped region, comprising: etching the implantation barrier layer in the deep groove of the well region to form the first well region doped region, wherein the widths of the first well region doped regions on both sides of the silicon nitride filling layer are equal; The implantation barrier layer on the metal mask layer and the first etch mask layer are etched to form the second well region doped region on the well region doped layer. 5. The preparation method according to claim 1, wherein the forming the second vertical well region in the well region doped layer comprises: The second type of doping ions are implanted into the well region doping layer through the second well region doping region to form the second vertical well region, wherein the depth of the second vertical well region is greater than that of the well region the depth of the doped layer. 6 . The manufacturing method of claim 1 , wherein the depth of the first lateral well region is greater than the width of the first vertical well region. 7 . 7 . The manufacturing method of claim 6 , wherein the width of the first lateral well region is smaller than the width of the concave region of the first gate oxide layer. 8 . 8 . The manufacturing method of claim 1 , wherein the depth of the second vertical well region is greater than the depth of the second lateral well region. 9 . 9 . The manufacturing method of claim 1 , wherein the upper surface of the source region is flush with the upper surface of the second longitudinal well region. 10 . 10. A silicon carbide MOSFET, characterized in that, the silicon carbide MOSFET is prepared by the preparation method according to any one of claims 1-9.

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