CN114283860A

CN114283860A - MRAM sense amplifier and screening method

Info

Publication number: CN114283860A
Application number: CN202011040948.1A
Authority: CN
Inventors: 何伟伟; 戴瑾
Original assignee: Shanghai Information Technologies Co ltd
Current assignee: Shanghai Information Technologies Co ltd
Priority date: 2020-09-28
Filing date: 2020-09-28
Publication date: 2022-04-05

Abstract

The application provides an MRAM read-out amplifier and a screening method, wherein a composite switch control mechanism is arranged at an input end of a differential amplifier to control the pre-charging of a memory cell and the starting time of the differential amplifier, so that the writing state of the memory cell is effectively reproduced. On the other hand, in the production process of the MRAM, the input end is input with different electric potentials, and the situation of the recurrence of the differential amplifier is combined, so that whether the memory cell fails or not can be judged, and the redundancy unit is used for replacing the memory cell when the memory cell fails, and the production yield of the MRAM can be effectively improved.

Description

MRAM sense amplifier and screening method

Technical Field

The present application relates to the field of register technology, and more particularly, to a method for screening an MRAM sense amplifier.

Background

A Sense Amplifier (Sense Amplifier) of an MRAM is a core cell in a circuit, and has high requirements on various aspects of speed, accuracy, and power consumption. The conventional sense amplifier of MRAM has a relatively mature manufacturing technology. However, in a large-capacity MRAM chip, there is always a small fraction of memory cells, whose resistance values differ only slightly: for a 1T1M design, the P-state or AP-state resistance of some cells may be very close to the reference value; for the 2T2M design, some cells may have too small a difference in left and right resistance in a certain state. Such memory cells are not reliable in practice. It is difficult to improve the accuracy of the sense amplifier over a wide range of operating temperatures and noise can also affect the sensing of very small resistance differences.

In the disclosure of the chinese patent application No. CN201610079008.0, a sense amplifier in an MRAM read/write circuit is disclosed, in which an input terminal of a differential current output part is connected to a reference unit and a memory unit, respectively, and the comparison result is output by comparing the currents of the two input terminals. However, this solution still fails to solve the above-mentioned accuracy problem of the sense amplifier.

Disclosure of Invention

In order to solve the above-mentioned problems, an object of the present invention is to provide an MRAM sense amplifier having a screening function and a screening method thereof.

The purpose of the application and the technical problem to be solved are realized by adopting the following technical scheme.

The application provides a method for screening a magnetic random access memory unit by a sense amplifier, wherein the magnetic random access memory unit comprises an input circuit and a differential amplifier, the input circuit comprises a storage unit with a magnetic random access junction and a reference resistor, the storage unit and the reference resistor are respectively connected with a first input end and a second input end of the differential amplifier, two sets of read operation control switches are respectively connected to the first input end and the second input end, and each read operation switch comprises a read operation switch and a switch tube. The method comprises the following steps: setting a writing state of the memory cell so that resistance values of the memory cell and the reference resistor are different; setting the same reading voltage to the drain electrodes of the two switching tubes; setting two pre-charging signals to the grids of the two switching tubes, wherein the two switching tubes acquire the voltage magnitude relation of the two pre-charging signals, and the resistance values of the two switching tubes are different in contrast to the resistance value magnitude relation of the storage unit and the reference resistor so as to adjust the input voltage of the two switching tubes to the first input end and the input voltage of the second input end; and replacing the memory cell connected with the first input end by a redundancy circuit when the written state of the memory cell connected with the first input end cannot be reproduced through the output of the differential amplifier.

Optionally, the first input terminal and the second input terminal are respectively provided with an amplifier switch, and the differential amplifier, the memory unit and the reference resistor are electrically connected or disconnected by switching states of the amplifier control signal switches.

Optionally, when the two groups of memory cells perform a write operation, the resistance of the memory cell connected to the first input terminal is higher than the resistance of the memory cell connected to the reference resistance at the second input terminal; in a read operation, the input voltage of the first input terminal is lower than the input voltage of the second input terminal.

Optionally, when the two groups of memory cells are in a write operation, the resistance of the memory cell connected to the first input terminal is lower than the resistance of the memory cell connected to the reference resistance at the second input terminal; in a read operation, the input voltage of the first input terminal is higher than the input voltage of the second input terminal.

Optionally, the redundant circuit is formed by more than one magnetic tracking junction.

Optionally, the reference resistor is formed by a high-precision thin film resistor circuit.

Alternatively, the reference resistance may be replaced with a memory cell having a magnetic tracking junction.

Optionally, the read operation control switch connected to the second input terminal may be alternatively connected to the reference voltage.

The application also provides a sense amplifier of the magnetic random access memory cell, which comprises an input circuit and a differential amplifier, wherein the input part comprises a memory cell with a magnetic tracking junction and a reference resistor which are respectively connected with two input ends of the differential amplifier; two amplifier change-over switches are respectively arranged at two input ends of the differential amplifier, one amplifier change-over switch is electrically connected with a read operation control switch and a storage unit, the other amplifier change-over switch is electrically connected with the read operation control switch and the reference resistor, and each amplifier change-over switch enables the differential amplifier, the read operation control switch, the storage unit and the reference resistor to be electrically connected or disconnected through the state of an amplifier control signal change-over switch; the read operation control switch comprises a read operation switch and a switch tube, the grid electrode of the switch tube is connected with a pre-charge signal end, the drain electrode of the switch tube is connected with a read voltage, the source electrode of the switch tube is connected with one end of the read operation switch, and the read operation switch switches the state of the switch by controlling a read activation signal, so that the read operation control switch, the differential amplifier and the storage unit are electrically connected or disconnected; the memory cell includes a magnetic follower junction and a field effect transistor for connecting a word line and a bit line.

Optionally, in the screening mode, when each memory cell is in a write operation, the resistance of the memory cell connected to one of the two input terminals is higher than the resistance of the reference resistor connected to the other of the two input terminals; setting the same reading voltage to the drain electrodes of the two switching tubes; setting two pre-charging signals to the grids of the two switching tubes, wherein the two switching tubes acquire the voltage magnitude relation of the two pre-charging signals, and the resistance values of the two switching tubes are different in contrast to the resistance value magnitude relation of the memory unit and the reference resistor so as to adjust the two switching tubes to two input ends of the differential amplifier; and replacing the memory cell by a redundancy circuit when the written state connected with the memory cell cannot be reproduced through the output of the differential amplifier.

Optionally, when it is determined that the written state of the memory cell cannot be correctly reproduced by an analyzing circuit connected to the magnetic random access memory cell, the memory cell is connected to a redundancy circuit, or the redundancy circuit connected to the memory cell is enabled.

Optionally, in the normal mode, the precharge signal terminals connected to the gates of the switching tubes are at the same potential. When the amplifier switch is turned off and the row-column decoder of the magnetic random access memory cell selects a specific row-column position, the read operation switch is turned on, and the read voltage is precharged for the selected memory cell through the switch tube. When each of the amplifier changeover switches is turned on and each of the read operation switches is turned off, the differential amplifier reproduces a write state of the memory cell.

According to the MRAM sense amplifier and the screening method, the composite control switch is arranged at the input end of the differential amplifier, and the reading operation of the memory cell is effectively controlled by controlling the pre-charging of the memory cell and the starting time of the differential amplifier, so that the reading precision of the sense amplifier is improved. On the other hand, in the production process of the MRAM, the input end is input with different electric potentials, and the situation of the recurrence of the differential amplifier is combined, so that whether the memory cell fails or not can be judged, whether the register cell is replaced by a redundant cell or not can be determined, and the production yield of the MRAM can be improved.

Drawings

FIG. 1A is a conceptual diagram of an MRAM sense amplifier circuit 2T2M according to an embodiment of the present application;

FIG. 1B is a conceptual diagram of an MRAM sense amplifier circuit 1T1M according to an embodiment of the present application;

FIG. 2 is a conceptual diagram of an MRAM sense amplifier circuit 2T2M according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an alternative architecture of an MRAM sense amplifier circuit 1T1M/2T2M according to an embodiment of the present application;

FIG. 4 is a timing diagram of an MRAM sense amplifier according to an embodiment of the present application;

FIG. 5 is a schematic diagram of an embodiment of an MRAM sense amplifier incorporating an adjustable precharge selection circuit.

Description of the symbols

10: a register unit; 20: a differential amplifier circuit; 21: a first inverter; 22: a second inverter; 31: a first magnetic tunnel junction; 32: a second magnetic tunnel junction; 41: a node; vdd: a power line; SL: a source line; BL: a bit line; RWL: reading a word line; WWL: writing a word line; n1: a first NMOS transistor; p1: a first PMOS transistor; n2: a second NMOS transistor; p2: a second PMOS transistor; n3: a first switch tube; n4: a second switching tube; n5: a third switching tube; OUT: a first output; OUT _ n: a second output; r: the resistors are shared.

Detailed Description

Refer to the drawings wherein like reference numbers refer to like elements throughout. The following description is based on illustrated embodiments of the application and should not be taken as limiting the application with respect to other embodiments that are not detailed herein.

The following description of the various embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. In the present application, directional terms such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", and the like are merely referring to the directions of the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and understanding, and is in no way limiting.

The terms "first," "second," "third," and the like in the description and in the claims of the present application and in the above-described drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "comprising" and "having," as well as variations thereof, such as, for example, are intended to cover non-exclusive inclusions.

The terminology used in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the concepts of the present application. Unless the context clearly dictates otherwise, expressions used in the singular form encompass expressions in the plural form. In the present specification, it will be understood that terms such as "including," "having," and "containing" are intended to specify the presence of the features, integers, steps, acts, or combinations thereof disclosed in the specification, and are not intended to preclude the presence or addition of one or more other features, integers, steps, acts, or combinations thereof. Like reference symbols in the various drawings indicate like elements.

The drawings and description are to be regarded as illustrative in nature, and not as restrictive. In the drawings, elements having similar structures are denoted by the same reference numerals. In addition, the size and thickness of each component shown in the drawings are arbitrarily illustrated for understanding and ease of description, but the present application is not limited thereto.

In the drawings, the range of configurations of devices, systems, components, circuits is exaggerated for clarity, understanding, and ease of description. It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.

In addition, in the description, unless explicitly described to the contrary, the word "comprise" will be understood to mean that the recited components are included, but not to exclude any other components. Further, in the specification, "on.

To further illustrate the technical means and effects of the present application for achieving the intended purpose, the following detailed description is given for the MRAM sense amplifier and the screening method according to the present application with reference to the accompanying drawings and the embodiments.

FIG. 1A is a conceptual diagram of the architecture of an MRAM sense amplifier circuit 2T2M according to an embodiment of the present disclosure, and FIG. 1B is a conceptual diagram of the architecture of an MRAM sense amplifier circuit 1T1M according to an embodiment of the present disclosure. The application provides a sense amplifier of a magnetic random access memory cell, which comprises an input circuit and a differential amplifier SA, wherein, as shown in FIG. 1B, the input part is connected with a memory cell (MR1) with a magnetic track junction and a reference resistor RC which are respectively connected with two input ends (Vin1, Vin2) of the differential amplifier SA, or as shown in FIG. 1A, the input part is connected with two groups of memory cells (MR1, MR2) with magnetic track junctions; the two input ends are respectively provided with two amplifier change-over switches (T1, T2), the other ends of the amplifier change-over switches (T1, T2) are electrically connected with a read operation control switch and a storage unit (MR1, MR2), and the amplifier change-over switches (T1, T2) change over the state of the switches through an amplifier control signal (SA _ EN), so that the differential amplifier SA, the read operation control switch and the storage unit (MR1, MR2) are electrically connected or disconnected; the read operation control switch comprises a read operation switch (T3, T4) and a switch tube (nm3, nm4), the grid electrode of the switch tube (nm3, nm4) is connected with precharge signal ends (Vclamp _ BL and Vclamp _ BLb), the drain electrode of the switch tube is connected with a read voltage (Vread), the source electrode of the switch tube is respectively connected with one end of the read operation switch, the other end of the read operation switch is connected with input ends (Vin1, Vin2) of a differential amplifier SA, and the read operation switch switches the switch state by controlling a read activation signal (RE _ EN) to enable the switch tube (nm3, nm4) and the differential amplifier SA as well as the memory cells MR1, MR2) to be electrically connected or disconnected; the memory cells MR1, MR2) include magnetic tracking junctions and field effect transistors for connecting word lines and bit lines. For ease of illustration, the 2T2M architecture is subsequently illustrated.

FIG. 2 is a schematic diagram of an MRAM sense amplifier circuit according to an embodiment of the present application. In an embodiment of the present application, the differential amplifier includes two inverters cross-connected to form an unbalanced flip-flop circuit. One end of each of the two inverters is connected to a power supply line VDD, and the other end of each of the two inverters is used as the input terminal (Vin1, Vin 2).

The two phase inverters are respectively a combination of a PMOS tube pm3 connected in series with an NMOS tube nm1 and a PMOS tube pm4 connected in series with an NMOS tube nm 2. The Gate (Gate) of the NMOS transistor nm1 and the PMOS transistor pm3 are connected to the output node OA of the other inverter at the same time; the Gate (Gate) of NMOS transistor nm2 and PMOS transistor pm4 are connected to the output node OB of the other inverter at the same time. Two PMOS tubes (pm1, pm2) are connected as grid electrodes, source electrodes are connected with a power line VDD, and drain electrodes are respectively connected with two output ends (OA, OB). The two output nodes (OA, OB) output signals (SOa, SOb) through inverters, and the Latch (SR Latch) is used for digital output (Data _ out). In some embodiments, the differential amplifier referred to herein is applicable to any kind of differential amplifier, without any limitation.

FIG. 3 is a schematic diagram of an alternative MRAM sense amplifier circuit 1T1M/2T2M according to an embodiment of the present application. In one embodiment of the present application, the memory cells (MR1, MR2) are respectively formed by magnetic tunnel junctions (MTJ1, MTJ2) in combination with bit line switches (AC1, AC2) connected to bit line switches T5(j) and T7(j), and bit line switches T6(j) and T8 (j). The ends of the memory cells (MR1, MR2) are connected to the ground through two source line switching tubes (nm5, nm6), the gates of the source line switching tubes (nm5, nm6) are connected with a read signal (RE), and the sources are connected with source input/output signals (IO _ SL, IO _ SLb). The control ends of the bit line switches T5(j) and T7(j) and the bit line switches T6(j) and T8(j) are respectively connected with the bit line (j), and the gates of the bit line switch tubes (AC1 and AC2) are connected with the word line (i).

The sense amplifier has two input points (IO _ BL and IO _ BLb). In the MRAM structure of 2T2M, the two input points (IO _ BL and IO _ BLb) are connected to one column j through bit line switches T5 and T6 in a column selection switch (MUX), respectively, and two source lines of one row i and one column j are selected by a row decoder and connected to two switching tubes nm5 and nm6 of a reading circuit through source line switches in the column selection switch (MUX), respectively, and during a reading operation, RE signals control nm5 and nm6 to ground the two source lines. In an MRAM architecture such as 1T1M of fig. 1B, the input point (IO _ BL or IO _ BLb) connected to reference resistor RC may alternatively be connected to a reference voltage.

Optionally, as shown in fig. 3, the reference resistor is formed by a high-precision thin film resistor.

Optionally, as shown in fig. 3, in the manufacturing process, the memory cell structure (composed of the magnetic tunnel junction MTJ2 and the switching tube AC2) is replaced with the same 2T2M structure (composed of the magnetic tunnel junction MTJx and the switching tube ACx) or is replaced with a 1T1M structure (composed of the high precision thin film Resistor and the switching tube ACx) according to the requirement. Alternatively, the redundant circuit described above is replaced depending on the screening configuration.

FIG. 4 is a timing diagram of an MRAM sense amplifier according to an embodiment of the present application. Please refer to the previous figures concurrently to facilitate understanding. The case where the sense amplifier is normally used includes:

the precharge signal terminals (Vclamp _ BL and Vclamp _ BLb) connected with the grid electrode of each switching tube are set to be the same potential.

The amplifier control signal (SA _ EN) is set to a potential (e.g., low level) that disables the output of the differential amplifier SA so that the amplifier switches (T1, T2) are off and the OA and OB signal outputs are high level.

Then, during the period that the row-column decoder of the magnetic random access memory cell selects a specific row-column position, Bit [ j ] is high level, the read excitation signal (RE _ EN) is high level, the read operation switches (T3 and T4) are connected, WL [ i ] level is changed from low to high, at the moment, IO _ BL and IO _ BLb establish corresponding initial pre-charging voltage according to the cell resistance state and the reference resistance, namely, the read voltage (Vread) is pre-charged for the selected memory cell (MR1 and MR2) through the switch (nm3 and nm 4).

The read enable signal (RE _ EN) is set to low level, and the precharge paths on both sides are disconnected. Then setting the amplifier control signal (SA _ EN) to be at high level, the amplifier switch (T1, T2) is connected, then OA and OB form two discharging paths until positive feedback is formed when one side voltage is lower than VDD-Vth (pm3 or pm4), the differential amplifier reproduces the writing state of the memory cell, OA and OB are finally amplified to recognizable high-low logic signals, and then the signals are latched and output by the following SR Latch.

The sense amplifier is applicable to screening of bad memory cells during production of magnetic random access memory cells. This method is applicable to the sense amplifier of the structure of fig. 1A-3 described above.

As shown in fig. 1B, taking the circuit architecture of 1T1M as an example, the mram includes an input circuit and a differential amplifier SA, and the input portion includes a memory cell (MR1) having a magnetic tunnel junction (MTJ1) and a reference resistor RC, which are respectively connected to a first input terminal Vin1 and a second input terminal Vin2 of the differential amplifier SA.

As shown in fig. 1A, fig. 2 and fig. 3, taking the circuit architecture of 2T2M as an example, the mram includes an input circuit and a differential amplifier SA, and the input portion includes two groups of memory cells (MR1, MR2) having magnetic tracking junctions (MTJ1, MTJ2), which are respectively connected to a first input terminal Vin1 and a second input terminal Vin2 of the differential amplifier SA.

In the manufacturing process of the memory, the screening process by the sense amplifier comprises the following steps:

step (S110): and cutting off the electrical connection between the input circuit and the differential amplifier SA.

Step (S120): setting a writing state of the memory cell, wherein the resistance values of the memory cell and the reference resistor are different; setting the same reading voltage to the drain electrodes of the two switching tubes; setting two pre-charging signals to the grids of the two switching tubes, wherein the two switching tubes acquire the voltage magnitude relation of the two pre-charging signals, and the resistance values of the two switching tubes are different from each other in contrast to the resistance value magnitude relation of the storage unit and the reference resistor so as to adjust the input voltage of the two switching tubes to the first input end and the input voltage of the second input end.

In some embodiments, in the 1T1M architecture, the memory cell (MR1) is precharged by setting the input voltage IO _ BL at the first input terminal Vin1 and the input voltage IO _ BLb at the second input terminal Vin2 to be different, where the input voltage IO _ BLb at the second input terminal is a reference voltage. Then, the input circuit is electrically connected to the differential amplifier SA, and the input voltages (IO _ BL, IO _ BLb) of the first input terminal Vin1 and the second input terminal Vin2 are disconnected.

In some embodiments, in the architecture of 1T1M, the memory cell (MR1 is in write operation, the resistance of the memory cell MR1 connected to the first input terminal Vin1(IO _ BL) is higher than the resistance of the reference resistor RC connected to the second input terminal Vin2(IO _ BLb). then, a difference is set such that Vclamp _ BL < Vclamp _ BLb, so that the input voltage IO _ BL of the first input terminal Vin1 is lower than the input voltage IO _ BLb of the second input terminal Vin2, and then a read operation is performed.

In some embodiments, in the architecture of 1T1M, during a write operation of the memory cell (MR1), the resistance of the memory cell MR1 connected to the first input terminal Vin1(IO _ BL) is lower than the resistance of the reference resistor RC connected to the second input terminal Vin2(IO _ BLb). Then, a difference value is set such that Vclamp _ BL > Vclamp _ BLb is set, so that the input voltage IO _ BL of the first input terminal Vin1 is higher than the input voltage IO _ BLb of the second input terminal Vin2, and then the reading operation is performed. In such a configuration, the resistance of the MTJ connected to IO _ BL must be lower than the reference resistance RC on the other side by a certain threshold value to reproduce the previously written state.

In some embodiments, in the 2T2M architecture, the two groups of memory cells (MR1, MR2) are precharged by setting the input voltage IO _ BL at the first input terminal Vin1 and the input voltage IO _ BLb at the second input terminal Vin2 to be different, where the input voltage IO _ BLb at the second input terminal is a reference voltage. Then, the input circuit is electrically connected to the differential amplifier SA, and the input voltages (IO _ BL, IO _ BLb) of the first input terminal Vin1 and the second input terminal Vin2 are disconnected.

In some embodiments, in the 2T2M architecture, during a write operation of the two groups of memory cells (MR1, MR2), the resistance of the memory cell MR1 connected to the first input terminal Vin1(IO _ BL) is higher than the resistance of the memory cell MR2 connected to the second input terminal Vin2(IO _ BLb). Then, a difference value is set such that Vclamp _ BL < Vclamp _ BLb, so that the input voltage IO _ BL of the first input terminal Vin1 is lower than the input voltage IO _ BLb of the second input terminal Vin2, and then the reading operation is performed. In such a configuration, the resistance of the MTJ connected to IO _ BL must be higher than the resistance of the other MTJ by a certain threshold to reproduce the previously written state.

In some embodiments, in the 2T2M architecture, during a write operation of the two groups of memory cells (MR1, MR2), the resistance of the memory cell MR1 connected to the first input terminal Vin1(IO _ BL) is lower than the resistance of the memory cell MR2 connected to the second input terminal Vin2(IO _ BLb). Then, a difference value is set such that Vclamp _ BL > Vclamp _ BLb is set, so that the input voltage IO _ BL of the first input terminal Vin1 is higher than the input voltage IO _ BLb of the second input terminal Vin2, and then the reading operation is performed. In such a configuration, the resistance of the MTJ connected to IO _ BL must be lower than the resistance of the other MTJ by a certain threshold value to reproduce the previously written state.

Step (S130): when the written state of the memory cell MR1 connected with the first input terminal Vin1 is judged to be not reproducible through the output of the differential amplifier SA, the memory cell MR1 connected with the first input terminal Vin1 is replaced by a redundancy circuit.

Optionally, when the input voltage IO _ BL of the first input terminal is a reference voltage, or the first input terminal Vin1 is connected to the reference resistor RC, the memory cell MR2 connected to the second input terminal Vin2 is replaced by a redundant circuit.

In the read operation of any of the above memory cells, if the previously written state cannot be reproduced, it is determined that the memory cell (MR1/MR2) is failed, i.e., replaced with a redundant circuit.

In some embodiments, the redundant circuit is formed by more than one magnetic tracking junction.

In the embodiment of the present application, in the structure of 2T2M, the first input terminal Vin1 and the second input terminal Vin2 are respectively provided with an amplifier switch (T1, T2), and the differential amplifier SA and the two groups of memory cells (MR1, MR2) are electrically connected or disconnected by switching the switch states through an amplifier control signal (SA _ EN). In the architecture of 1T1M, either of the two sets of memory cells (MR1, MR2) can be replaced by the reference resistor RC described above.

FIG. 5 is a schematic diagram of an embodiment of an adjustable precharge select circuit. In some embodiments, the aforementioned Sense Amplifier (SA) may be combined with a screening circuit to form an adjustable precharge select circuit. This structure includes: a Low dropout regulator (Low drop regulator), a Screen Switch (Screen Switch), a sense amplifier SA, a Column Selector (Column Selector), a Word Line Power supply (Word Line Power), a Row Decoder (Row Decoder), and an MRAM array. The MRAM array is provided with a plurality of memory cells, and the memory cells to be written or read are selected by a column selector and a row decoder. The low dropout linear regulator outputs a precharge voltage and a calibration potential (Vclamp, Vclamp _ Trim) thereof to the screening switch. The screening switch determines whether the screening function is enabled or not by the activation signal (Screen _ EN). When the screening function is not enabled, the two precharge signals (Vclamp _ BL, Vclamp _ BLb) output to the sense amplifier are at the same potential. If the screening is enabled, two precharge signals (Vclamp _ BL, Vclamp _ BLb) with different potentials are output to the sense amplifier according to the Data (Data) and the previous precharge voltage and the calibration potential (Vclamp, Vclamp _ Trim). The sense amplifier SA performs testing and screening on the selected memory cell according to the above operation.

According to the MRAM sense amplifier and the screening method, the composite control switch is arranged at the input end of the differential amplifier, and the reading operation of the memory cell is effectively controlled by controlling the pre-charging of the memory cell and the starting time of the differential amplifier, so that the reading precision of the sense amplifier is improved. On the other hand, in the MRAM production process, the input end is input with different electric potentials, and the combination of the reproduction situation of the differential amplifier can help to judge whether the memory cell fails or not so as to determine whether the register cell is replaced by a redundant cell when the register cell fails, thereby improving the production yield of the MRAM

The terms "in one embodiment of the present application" and "in various embodiments" are used repeatedly. This phrase generally does not refer to the same embodiment; it may also refer to the same embodiment. The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise.

Although the present application has been described with reference to specific embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.

Claims

1. A method for screening magnetic random access memory cells by a sense amplifier, the sense amplifier circuit comprising an input circuit and a differential amplifier, the input circuit comprising a memory cell with a magnetic track junction and a reference resistor, which are respectively connected to the The first input terminal and the second input terminal of the differential amplifier, two groups of read operation control switches are respectively connected to the first input terminal and the second input terminal, each read operation switch includes a read operation switch and a switch tube, which Characterized in that the method includes:

setting the write state of the memory cell so that the resistance values of the memory cell and the reference resistor are different;

setting the same read voltage to the drains of the two switches;

Set two precharge signals to the gates of the two switch tubes, and the two switch tubes obtain the voltage magnitude relationship of the two precharge signals, which is opposite to the resistance of the storage unit and the reference resistor. value relationship, the resistance values of the two switch tubes are different, so as to adjust the input voltage of the two switch tubes to the first input terminal and the input voltage of the second input terminal;

Based on the output of the differential amplifier, when it is determined that the written state of the memory cell connected to the first input end cannot be reproduced, a redundant circuit is used to replace the memory cell connected to the first input end.

2. The method according to claim 1, wherein the first input terminal and the second input terminal are respectively provided with an amplifier switch, and the switch state is switched by an amplifier control signal , the differential amplifier is electrically connected or disconnected between the storage unit and the reference resistor.

3. The method for screening magnetic random access memory cells by a sense amplifier according to claim 1, wherein when the memory cell is in a writing operation, the resistance value of the memory cell connected to the first input terminal is higher than the resistance value of the memory cell. The second input terminal is connected to the resistance value of the reference resistor; during the read operation, the input voltage of the first input terminal is lower than the input voltage of the second input terminal; or,

During the write operation of the storage unit, the resistance value of the storage unit connected to the first input end is lower than the resistance value of the reference resistor connected to the second input end; during the read operation, the first input end The input voltage of the terminal is higher than the input voltage of the second input terminal.

4. The method according to claim 1, wherein the reference resistor is composed of a high-precision thin film resistor, or the reference resistor can be replaced with a magnetic track junction. storage unit.

5 . The method for screening magnetic random access memory cells by a sense amplifier according to claim 1 , wherein the read operation control switch connected to the second input terminal can be replaced as a reference voltage. 6 .

6. A sense amplifier of a magnetic random access memory cell, comprising an input circuit and a differential amplifier, wherein the input part comprises a storage cell with a magnetic follower junction and a reference resistor, which are respectively connected to two of the differential amplifiers. an input;

The two input ends of the differential amplifier are respectively provided with two amplifier switching switches, the other end of the amplifier switching switch is electrically connected to the read operation control switch and the storage unit, and the other end of the amplifier switching switch is electrically connected to the other end. A read operation control switch and the reference resistor, each of the amplifier switching switches switches the switch state through an amplifier control signal, so that the differential amplifier, the read operation control switch, the storage unit and the reference resistor, Form electrical conduction or electrical disconnection;

The read operation control switch includes a read operation switch and a switch tube, the gate of the switch tube is connected to the precharge signal terminal, the drain is connected to the read voltage, and the source is connected to one end of the read operation switch, and the read operation switch passes through the The control of the read activation signal switches the state of the switch, so that electrical conduction or electrical disconnection is formed between the read operation control switch, the differential amplifier and the memory cell;

The memory cells include magnetic follower junctions and field effect transistors for connecting word lines and bit lines.

7 . The sense amplifier of the magnetic random access memory cell according to claim 6 , wherein, in the screening mode, when each of the memory cells is in a write operation, the storage resistance connected to one of the two input terminals is high. 8 . The resistance of the reference resistor connected to the other two input terminals; set the same read voltage to the drains of the two switches; set two precharge signals to the gates of the two switches , the two switch tubes obtain the relationship between the voltages of the two pre-charge signals. Contrary to the relationship between the resistance values of the storage unit and the reference resistor, the resistance values of the two switch tubes are different. In order to adjust the two input ends of the two switches to the differential amplifier; through the output of the differential amplifier, when it is judged that the written state connected to the storage unit cannot be reproduced, a redundant circuit is used to replace the storage unit.

8 . The sense amplifier of the magnetic random access memory cell according to claim 6 , wherein, in the normal mode, the precharge signal terminals connected to the gates of the switches are at the same potential; when the amplifier switches are After the row and column decoder of the magnetic random access memory cell selects a specific row and column position, the read operation switch is connected, and the read voltage precharges the selected memory cell through the switch tube; The amplifier switching switches are turned on, each of the read operation switches is turned off, and the differential amplifier reproduces the write state of the memory cell.

9 . The sense amplifier of the magnetic random access memory cell according to claim 6 , wherein the reference resistor is composed of a high-precision thin film resistor, or the reference resistor can be replaced with a memory cell having a magnetic track junction. 10 . .

10 . The sense amplifier of the magnetic random access memory cell according to claim 6 , wherein the read operation control switch connected to the switch of another amplifier can be alternatively connected to a reference voltage. 11 .