CN114157144B - PWM control circuit based on multiphase DC-DC buck converter - Google Patents
PWM control circuit based on multiphase DC-DC buck converter Download PDFInfo
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- CN114157144B CN114157144B CN202111488376.8A CN202111488376A CN114157144B CN 114157144 B CN114157144 B CN 114157144B CN 202111488376 A CN202111488376 A CN 202111488376A CN 114157144 B CN114157144 B CN 114157144B
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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Abstract
The invention discloses a PWM control circuit based on a multiphase DC-DC buck converter, which comprises: a multiphase DC-DC buck converter, a clock, a phase distributor, a fixed off-time generator, and a peak current mode PWM controller. The invention uses the existing peak current detector and error amplifier to distribute the current without adding an integrating circuit and a detecting circuit; the phase allocator may achieve an average phase allocation; the fixed off-time generator can eliminate the slope compensation in peak current mode PWM control and reduce the current mismatch due to the slope compensation.
Description
Technical Field
The invention belongs to the technical field of power management chips, and particularly relates to a PWM control circuit based on a multiphase DC-DC buck converter.
Background
The DC-DC buck converter is a conversion circuit for converting a higher input voltage to a lower output voltage, and as shown in fig. 1, includes a Low-pass filter (Low PASS FILTER) formed of two Power transistors (P Power FET and N Power FET), an inductor (Inductor), and a Capacitor (Capacitor). One of the power tubes is a main power tube, and the conduction time of the main power tube is the pulse width of the switching square wave.
The DC-DC buck converter can be controlled by peak current mode PWM control (Peak Current Mode PWM Control), PFM (Pulse-Frequency-Modulation) Pulse Frequency Modulation, fixed Off-time mode PFM control (Constant-Off-Time Mode PFM Control), and the like. Referring to fig. 2, the peak current mode PWM control is a control method for determining the pulse width of a fixed frequency switching square wave by using the peak value of the inductor current; PFM pulse frequency modulation is a control method that generates the desired pulse width by adjusting the switching square wave frequency; the fixed off time mode PFM control is a control method for determining the pulse width of the square wave by adjusting the switching frequency of the square wave by the off time of the fixed main power tube.
N single-phase direct current-direct current buck converters (DC-DC Step-Down converters) are arranged in parallel between the input power source and the load to output a larger load current. Each power stage in the n phases is turned on at the same intervals during switching so that the effective output voltage ripple frequency of the multiphase system is n x f, where f is the switching frequency of each converter and n is the number of phases of the converter.
Multiphase (Multi-Phase) dc-dc buck converters can provide better dynamics without increasing switching losses. The switching scheme of a Multi-Phase dc-dc buck converter is very complex, and the switching frequency phases of the individual single-Phase converters must be equally distributed to obtain the lowest RMS (Root-Mean-Square) value of the output current. While the output current is equally distributed among the n single-phase converters to reduce interference between the individual converters. It is difficult to control all single-phase converters in coordination, so that there is a need for new control techniques to avoid the disadvantages of multiple systems.
Reference is made to fig. 3 for the problem of average current output of the power stages of two dc-dc down-converters, and reference is made to fig. 4 for the problem of average frequency-phase distribution of the power stages of two dc-dc down-converters. In order to deal with multiphase current distribution and Phase (Phase) distribution, an integrating circuit and a detecting circuit are added to integrate the output voltage (e.g. US 9369043B 2 and WO2013127750 A3) or the output current (e.g. CN 103457455) of each power stage, and then the integrated signal is added to a feedback loop to achieve the purpose of Phase and current distribution. These integrating and detecting circuits increase chip cost, increase loop complexity, and increase the risk of mismatch (mismatch). To reduce the problem of multiple power stage current and phase imbalance, the mismatch introduced by the new added circuitry increases the power stage current and phase errors.
Accordingly, in view of the above-mentioned technical problems, it is necessary to provide a PWM control circuit based on a multiphase DC-DC buck converter.
Disclosure of Invention
Accordingly, an objective of the present invention is to provide a PWM control circuit based on a multiphase DC-DC buck converter to achieve a coordinated operation of the multiphase DC-DC buck converter.
In order to achieve the above object, an embodiment of the present invention provides the following technical solution:
a PWM control circuit based on a multiphase DC-DC buck converter, the PWM control circuit comprising:
The multi-phase DC-DC buck converter comprises n power stages connected in parallel between an input voltage VIN and an output voltage VOUT, wherein each power stage is a single-phase DC-DC buck converter;
A clock for providing a clock signal;
the phase distributor is connected with the clock and is used for outputting n frequency division signals with evenly distributed phases according to the clock signal;
the fixed turn-off time generator is connected with the phase distributor and is used for generating n fixed turn-off time pulse signals Toff 1-Toff n according to the frequency division signals output by the phase distributor;
And the peak current mode PWM controller is connected with the fixed turn-off time generator and the multiphase DC-DC buck converter and is used for generating a grid control signal for controlling each power stage according to n fixed turn-off time pulse signals Toff 1-Toff n and the peak current signal of each power stage.
In an embodiment, the single-phase DC-DC buck converter includes a first power tube, a second power tube, and a filtering unit, where the first power tube is a PMOS tube, the second power tube is an NMOS tube, a source electrode of the first power tube is connected to the input voltage VIN, a source electrode of the second power tube is connected to the reference potential, and a drain electrode of the first power tube is connected to the drain electrode of the second power tube and then connected to the filtering unit.
In one embodiment, the phase distributor comprises a plurality of D flip-flops connected in series with a clock, and a plurality of logic gates, wherein the number of the D flip-flops is 2x, and x is more than or equal to 1.
In one embodiment, the phase allocator comprises:
the first D trigger and the second D trigger are sequentially connected with the clock in series, and the output end of the second D trigger outputs a first frequency division signal;
the input end of the NOT gate is connected with the output end of the second D trigger, and the output end outputs a second frequency division signal;
The first NOR gate, two input ends are connected with output end of the first D flip-flop and output end of the second D flip-flop separately, the output end outputs the third frequency division signal;
and the two input ends of the second NOR gate are respectively connected with the output end of the first D trigger and the output end of the NOT gate, and the output end outputs a fourth frequency division signal.
In one embodiment, the fixed off-time generator comprises:
an adaptive fixed off-time regulator for generating a current;
A ramp signal generator for generating a ramp signal;
The voltage comparator, the input signal of the first input end is the difference between input voltage and output voltage, namely VIN-VOUT, the second input end couples to adaptive fixed turn-off time regulator and slope signal generator, the output end outputs the comparison signal;
and the pulse generator is used for generating a fixed off-time pulse signal according to the comparison signal.
In an embodiment, the adaptive fixed off-time regulator includes a phase detector, a charge pump, and a transconductance amplifier arranged in series, where an input end of the phase detector is used to obtain a frequency-divided signal output by the phase divider and a comparison signal output by the voltage comparator.
In an embodiment, the ramp signal generator includes a first resistor R1, a second resistor R2, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a first PMOS transistor PM1, a second PMOS transistor PM2, and a capacitor C, wherein:
the first end of the first resistor R1 is connected with the input voltage VIN, the second end of the first resistor R1 is connected with the drain electrode of the first NMOS tube NM1, and the source electrode of the first NMOS tube NM1 is connected with a reference potential;
The source electrode of the first PMOS tube PM1 is connected with the input voltage VIN, the drain electrode of the first PMOS tube PM1 is connected with the drain electrode of the second NMOS tube NM2, the source electrode of the second NMOS tube NM2 is connected with the reference potential, the grid electrode of the second NMOS tube NM2 is connected with the grid electrode of the first NMOS tube NM1, and the grid electrode of the first PMOS tube PM1 is in short circuit with the drain electrode;
the grid electrode of the third NMOS tube NM3 is connected with the drain electrode of the first NMOS tube NM1, the drain electrode is connected with the drain electrode of the first PMOS tube PM1, and the source electrode is connected with the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube;
The first end of the second resistor R2 is connected with the grid electrode of the first NMOS tube NM1 and the grid electrode of the second NMOS tube NM2, the second end of the second resistor R2 is connected with a reference potential, and the resistance value of the second resistor R2 is 1/2 of the resistance value of the first resistor R1;
The source electrode of the second PMOS tube PM2 is connected with the input voltage VIN, the grid electrode of the second PMOS tube PM1 is connected with the grid electrode of the first PMOS tube PM1, the drain electrode of the second PMOS tube PM2 is connected with the first polar plate of the capacitor C, and the second polar plate of the capacitor C is connected with the reference potential;
the grid electrode of the fourth NMOS tube NM4 is connected with a grid electrode control signal, the drain electrode of the fourth NMOS tube NM4 is connected with the drain electrode of the second PMOS tube PM2, and the source electrode of the fourth NMOS tube NM4 is connected with a reference potential;
the ramp signal generator forms a ramp signal according to the current generated by the adaptive fixed off-time regulator, and outputs the ramp signal from the drain of the second PMOS transistor PM2 and the drain of the fourth NMOS transistor NM 4.
In an embodiment, the PWM control circuit further includes an error amplifier, a first input terminal of the error amplifier is connected to the reference voltage, a second input terminal of the error amplifier is connected to the output voltage, and the output terminal outputs the voltage signal after the error amplification.
In one embodiment, the peak current mode PWM controller comprises n PWM comparators and n SR latches, wherein:
the first input end of each PWM comparator is connected with the peak current signal of each power stage, the second input end of each PWM comparator is connected with the voltage signal output by the error amplifier, and the output end of each PWM comparator outputs the PWM comparison signal of each power stage;
The S input end of each SR latch is connected with a fixed turn-off time pulse signal corresponding to each power stage, the R input end of each SR latch is connected with the output end of the PWM comparator, and the Q output end of each SR latch outputs a grid control signal corresponding to each power stage.
In one embodiment, the multiphase DC-DC buck converter includes 4 power stages, the phase distributor outputs 4 divided signals with 90 ° phase distribution according to the clock signal, the fixed off-time generator generates 4 fixed off-time pulse signals Toff 1 to Toff 4 according to the 4 divided signals with 90 ° phase distribution, and the peak current mode PWM controller generates 4 gate control signals for controlling the power stages according to the 4 fixed off-time pulse signals Toff 1 to Toff 4 and peak current signals of the 4 power stages.
The invention has the following beneficial effects:
In the traditional peak current mode PWM control circuit, the current distribution is carried out by using the existing peak current detector and error amplifier, and an integrating circuit and a detecting circuit are not required to be added; the phase allocator may achieve an average phase allocation; the fixed off-time generator can eliminate the slope compensation in peak current mode PWM control and reduce the current mismatch due to the slope compensation.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.
FIG. 1 is a circuit diagram of a single-phase DC-DC buck converter according to the prior art;
FIG. 2 is a schematic diagram of a peak current mode PWM control of a single-phase DC-DC buck converter according to the prior art;
FIG. 3 is a schematic diagram illustrating the average problem of the power stage current output of two DC-DC buck converters according to the prior art;
FIG. 4 is a schematic diagram illustrating the problem of phase-sharing of switching frequency between two DC-DC buck converters according to the prior art;
FIG. 5 is a block diagram of a PWM control circuit based on a multiphase DC-DC buck converter according to the present invention;
FIG. 6 is a block diagram of a PWM control circuit based on a two-phase DC-DC buck converter according to the present invention;
FIG. 7 is a circuit diagram of a phase distributor according to an embodiment of the present invention;
FIG. 8 is a timing diagram of a phase divider generating a divided signal according to an embodiment of the present invention;
FIG. 9 is a circuit diagram of a fixed off-time generator according to an embodiment of the invention;
FIG. 10 is a timing diagram illustrating operation of an adaptive fixed off-time regulator according to an embodiment of the present invention;
FIG. 11 is a circuit diagram of a single channel peak current mode PWM controller according to an embodiment of the present invention;
Fig. 12 is a circuit diagram of an n-channel peak current mode PWM controller according to an embodiment of the present invention.
Detailed Description
In order to make the technical solution of the present invention better understood by those skilled in the art, the technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
Referring to fig. 5, the invention discloses a PWM control circuit based on a multiphase DC-DC buck converter, comprising:
The multi-phase DC-DC buck converter comprises n power stages connected in parallel between an input voltage VIN and an output voltage VOUT, wherein each power stage is a single-phase DC-DC buck converter;
A clock for providing a clock signal;
The phase distributor is connected with the clock and is used for outputting n frequency division signals with evenly distributed phases according to the clock signal;
The fixed turn-off time generators are respectively connected with the phase distributor, and are used for generating n fixed turn-off time pulse (pulse wave) signals Toff 1-Toff n according to the frequency division signals output by the phase distributor;
and the peak current mode PWM controller is connected with the n fixed off-time generators and the multiphase DC-DC buck converter and is used for generating a grid control signal for controlling each power stage according to the n fixed off-time pulse signals Toff 1-Toff n and the peak current signal of each power stage.
As shown in connection with fig. 6, the multiphase DC-DC buck converter is exemplified by two power stages (power stage 1 and power stage 2), comprising two fixed off-time generators (fixed off-time generator 1 and fixed off-time generator 2), respectively, and the peak current mode PWM controller comprises two driving stages (driving stage 1 and driving stage 2). The phase distributor outputs 2 divided signals with evenly distributed phases according to the clock signal, the fixed off time generator can generate 2 fixed off time pulse signals Toff 1 and Toff 2 according to the divided signals output by the phase distributor, and the driving stage 1 and the driving stage 2 in the peak current mode PWM controller can generate grid control signals for controlling the power stage 1 and the power stage 2 according to the fixed off time pulse signals Toff 1 and Toff 2 and peak current signals of each power stage.
In one embodiment of the present invention, four phases (i.e., n=4) are taken as an example, and the corresponding PWM control circuit includes:
The four-phase DC-DC buck converter comprises 4 power stages connected in parallel between an input voltage VIN and an output voltage VOUT, wherein each power stage is a single-phase DC-DC buck converter;
A clock for providing a clock signal;
The phase distributor is connected with the clock and is used for outputting 4 frequency division signals with evenly distributed phases according to the clock signal;
The fixed turn-off time generators are respectively connected with the phase distributor, and are used for generating 4 fixed turn-off time pulse signals Toff 1-Toff 4 according to the frequency division signals output by the phase distributor;
and the peak current mode PWM controller is connected with the 4 fixed off-time generators and the multiphase DC-DC buck converter and is used for generating a grid control signal for controlling each power stage according to the 4 fixed off-time pulse signals Toff 1-Toff 4 and the peak current signal of each power stage.
The reference potential in this embodiment is exemplified by the ground potential (GND).
The structure of the single-phase DC-DC buck converter is shown in fig. 1, and the single-phase DC-DC buck converter comprises a first power tube, a second power tube and a filtering unit, wherein the first power tube is a PMOS tube, the second power tube is an NMOS tube, a source electrode of the first power tube is connected with an input voltage VIN, a source electrode of the second power tube is connected with a reference potential, and a drain electrode of the first power tube is connected with the drain electrode of the second power tube and then is connected with the filtering unit.
The filter unit comprises an inductor Inductor and a Capacitor, wherein the inductor is connected between the drain electrode of the first power tube/the drain electrode of the second power tube and the output voltage VOUT, and the Capacitor is connected between the output voltage VOUT and the reference potential.
The phase distributor comprises a plurality of D flip-flops connected in series with a clock and a plurality of logic gates, wherein the number of the D flip-flops is 2x, and x is more than or equal to 1.
Referring to fig. 7, a circuit diagram of a phase divider in this embodiment is shown, where the phase divider includes 2D flip-flops, 1 not gate and 2 nor gates, and the phase divider includes:
the first D trigger and the second D trigger are sequentially connected with the clock in series, and the output end of the second D trigger outputs a first frequency division signal;
the input end of the NOT gate is connected with the output end of the second D trigger, and the output end outputs a second frequency division signal;
The first NOR gate, two input ends are connected with output end of the first D flip-flop and output end of the second D flip-flop separately, the output end outputs the third frequency division signal;
and the two input ends of the second NOR gate are respectively connected with the output end of the first D trigger and the output end of the NOT gate, and the output end outputs a fourth frequency division signal.
As shown in fig. 8, the phase splitter in the present embodiment can output 4 divided signals with a phase distribution of 90 ° under 4 power stage application conditions.
Referring to fig. 9, the fixed off-time generator in the present embodiment includes:
an adaptive fixed off-time regulator for generating a current;
A ramp signal generator for generating a ramp signal;
The voltage comparator, the input signal of the first input end is the difference between input voltage and output voltage, namely VIN-VOUT, the second input end couples to adaptive fixed turn-off time regulator and slope signal generator, the output end outputs the comparison signal;
And a pulse generator (pulse generator) for generating a fixed off-time pulse signal based on the comparison signal.
Specifically, the adaptive fixed off-time regulator includes a Phase detector (Phase Detection), a Charge Pump (Charge Pump), and a transconductance amplifier (gm) arranged in series, and an input end of the Phase detector is used for obtaining a frequency-divided signal output by the Phase divider and a comparison signal output by the voltage comparator.
The ramp signal generator comprises a first resistor R1, a second resistor R2, a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a first PMOS tube PM1, a second PMOS tube PM2 and a capacitor C, wherein:
the first end of the first resistor R1 is connected with the input voltage VIN, the second end of the first resistor R1 is connected with the drain electrode of the first NMOS tube NM1, and the source electrode of the first NMOS tube NM1 is connected with a reference potential;
The source electrode of the first PMOS tube PM1 is connected with the input voltage VIN, the drain electrode of the first PMOS tube PM1 is connected with the drain electrode of the second NMOS tube NM2, the source electrode of the second NMOS tube NM2 is connected with the reference potential, the grid electrode of the second NMOS tube NM2 is connected with the grid electrode of the first NMOS tube NM1, and the grid electrode of the first PMOS tube PM1 is in short circuit with the drain electrode;
the grid electrode of the third NMOS tube NM3 is connected with the drain electrode of the first NMOS tube NM1, the drain electrode is connected with the drain electrode of the first PMOS tube PM1, and the source electrode is connected with the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube;
The first end of the second resistor R2 is connected with the grid electrode of the first NMOS tube NM1 and the grid electrode of the second NMOS tube NM2, the second end of the second resistor R2 is connected with a reference potential, and the resistance value of the second resistor R2 is 1/2 of the resistance value of the first resistor R1;
The source electrode of the second PMOS tube PM2 is connected with the input voltage VIN, the grid electrode of the second PMOS tube PM1 is connected with the grid electrode of the first PMOS tube PM1, the drain electrode of the second PMOS tube PM2 is connected with the first polar plate of the capacitor C, and the second polar plate of the capacitor C is connected with the reference potential;
the grid electrode of the fourth NMOS tube NM4 is connected with a grid electrode control signal, the drain electrode of the fourth NMOS tube NM4 is connected with the drain electrode of the second PMOS tube PM2, and the source electrode of the fourth NMOS tube NM4 is connected with a reference potential;
The ramp signal generator forms a ramp signal according to the current generated by the adaptive fixed off-time regulator, and outputs the ramp signal from the drain of the second PMOS transistor PM2 and the drain of the fourth NMOS transistor NM 4.
Referring to fig. 10, in this embodiment, a phase detector, a charge pump and a transconductance amplifier are utilized to form an adaptive fixed off-time regulator to generate a current, dynamically adjust the slope of a ramp signal, adjust the off-time to synchronize the switching frequency of each power stage with the frequency-divided signal of the internal clock, and the on-time is determined by a peak current mode (peak current signal).
Referring to fig. 11, the PWM control circuit further includes an error amplifier, a first input terminal of the error amplifier is connected to the reference voltage, a second input terminal of the error amplifier is connected to the output voltage (output terminal voltage feedback, i.e., feedback voltage), the output terminal outputs the voltage signal after the error amplification, and a filter capacitor is disposed between the output terminal of the error amplifier and the reference potential.
Taking a single-channel peak current mode PWM controller as an example, the peak current mode PWM controller comprises 1 PWM comparator and 1 SR latch, wherein a first input end of the PWM comparator is connected with a peak current signal of a power stage, a second input end of the PWM comparator is connected with a voltage signal output by an error amplifier, and an output end of the PWM comparator outputs a PWM comparison signal of the power stage;
The S input end of the SR latch is connected with a fixed turn-off time pulse signal corresponding to the power level, the R input end of the SR latch is connected with the output end of the PWM comparator, and the Q output end of the SR latch outputs a grid control signal corresponding to the power level.
Referring to fig. 12, the peak current mode PWM controller in this embodiment is an n-channel peak current mode PWM controller, which includes n PWM comparators and n SR latches, wherein:
the first input end of each PWM comparator is connected with the peak current signal of each power stage, the second input end of each PWM comparator is connected with the voltage signal output by the error amplifier, and the output end of each PWM comparator outputs the PWM comparison signal of each power stage;
The S input end of each SR latch is connected with a fixed turn-off time pulse signal corresponding to each power stage, the R input end of each SR latch is connected with the output end of the PWM comparator, and the Q output end of each SR latch outputs a grid control signal corresponding to each power stage.
It should be understood that, in this embodiment, four power stages (four-phase DC-DC buck converter) are taken as an example, and in other embodiments, other numbers of power stages are also possible, which will not be described in detail herein.
In the traditional peak current mode PWM control circuit, the current distribution is carried out by using the existing peak current detector and the error amplifier, and the phase distributor is added at the same time, so that the average phase distribution is achieved.
In order to solve the problem of sub-ramp distortion when the duty cycle is greater than 50% in peak current mode PWM control, a ramp compensation signal must be superimposed on the peak current signal, and an error of this signal between channels may cause a great uneven distribution of current between channels. The invention adopts a peak current mode with fixed turn-off time, can eliminate secondary slope distortion without a slope compensation signal, and reduces current mismatch generated by slope compensation.
The invention utilizes the phase detector, the charge pump and the transconductance amplifier to form a self-adaptive fixed turn-off time regulator to generate current, and dynamically regulates the turn-off time to synchronize the switching frequency of each power stage with the frequency division signal of the internal clock, thereby eliminating phase errors caused by errors of the turn-off time generator.
As can be seen from the technical scheme, the invention has the following advantages:
In the traditional peak current mode PWM control circuit, the current distribution is carried out by using the existing peak current detector and error amplifier, and an integrating circuit and a detecting circuit are not required to be added; the phase allocator may achieve an average phase allocation; the fixed off-time generator can eliminate the slope compensation in peak current mode PWM control and reduce the current mismatch due to the slope compensation.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (8)
1. A PWM control circuit based on a multiphase DC-DC buck converter, the PWM control circuit comprising:
The multi-phase DC-DC buck converter comprises n power stages connected in parallel between an input voltage VIN and an output voltage VOUT, wherein each power stage is a single-phase DC-DC buck converter;
A clock for providing a clock signal;
the phase distributor is connected with the clock and is used for outputting n frequency division signals with evenly distributed phases according to the clock signal;
the fixed turn-off time generator is connected with the phase distributor and used for generating n fixed turn-off time pulse signals Toff 1-toffn according to the frequency division signals output by the phase distributor;
The peak current mode PWM controller is connected with the fixed turn-off time generator and the multiphase DC-DC buck converter and is used for generating a grid control signal for controlling each power level according to n fixed turn-off time pulse signals Toff 1-toffn and the peak current signal of each power level;
the PWM control circuit further comprises an error amplifier, wherein a first input end of the error amplifier is connected with a reference voltage, a second input end of the error amplifier is connected with an output voltage, and the output end outputs an error amplified voltage signal;
The peak current mode PWM controller includes n PWM comparators and n SR latches, wherein:
the first input end of each PWM comparator is connected with the peak current signal of each power stage, the second input end of each PWM comparator is connected with the voltage signal output by the error amplifier, and the output end of each PWM comparator outputs the PWM comparison signal of each power stage;
The S input end of each SR latch is connected with a fixed turn-off time pulse signal corresponding to each power stage, the R input end of each SR latch is connected with the output end of the PWM comparator, and the Q output end of each SR latch outputs a grid control signal corresponding to each power stage.
2. The PWM control circuit according to claim 1, wherein the single-phase DC-DC buck converter includes a first power tube, a second power tube, and a filter unit, the first power tube is a PMOS tube, the second power tube is an NMOS tube, a source electrode of the first power tube is connected to the input voltage VIN, a source electrode of the second power tube is connected to a reference potential, and a drain electrode of the first power tube is connected to a drain electrode of the second power tube and then connected to the filter unit.
3. The multiphase DC-DC buck converter based PWM control circuit according to claim 1, wherein the phase allocator includes a number of D flip-flops in series with a clock, and a number of logic gates, the number of D flip-flops being 2x, x being greater than or equal to 1.
4. A multiphase DC-DC buck converter based PWM control circuit according to claim 3, wherein the phase allocator includes:
the first D trigger and the second D trigger are sequentially connected with the clock in series, and the output end of the second D trigger outputs a first frequency division signal;
the input end of the NOT gate is connected with the output end of the second D trigger, and the output end outputs a second frequency division signal;
The first NOR gate, two input ends are connected with output end of the first D flip-flop and output end of the second D flip-flop separately, the output end outputs the third frequency division signal;
and the two input ends of the second NOR gate are respectively connected with the output end of the first D trigger and the output end of the NOT gate, and the output end outputs a fourth frequency division signal.
5. The multiphase DC-DC buck converter based PWM control circuit according to claim 1, wherein the fixed off-time generator includes:
an adaptive fixed off-time regulator for generating a current;
A ramp signal generator for generating a ramp signal;
The voltage comparator, the input signal of the first input end is the difference between input voltage and output voltage, namely VIN-VOUT, the second input end couples to adaptive fixed turn-off time regulator and slope signal generator, the output end outputs the comparison signal;
and the pulse generator is used for generating a fixed off-time pulse signal according to the comparison signal.
6. The multiphase DC-DC buck converter based PWM control circuit according to claim 5, wherein the adaptive fixed off-time regulator includes a phase detector, a charge pump, and a transconductance amplifier arranged in series, and an input of the phase detector is configured to obtain the divided signal output by the phase divider and the comparison signal output by the voltage comparator.
7. The PWM control circuit based on the multiphase DC-DC buck converter according to claim 5, wherein the ramp signal generator includes a first resistor R1, a second resistor R2, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a first PMOS transistor PM1, a second PMOS transistor PM2, and a capacitor C, wherein:
the first end of the first resistor R1 is connected with the input voltage VIN, the second end of the first resistor R1 is connected with the drain electrode of the first NMOS tube NM1, and the source electrode of the first NMOS tube NM1 is connected with a reference potential;
The source electrode of the first PMOS tube PM1 is connected with the input voltage VIN, the drain electrode of the first PMOS tube PM1 is connected with the drain electrode of the second NMOS tube NM2, the source electrode of the second NMOS tube NM2 is connected with the reference potential, the grid electrode of the second NMOS tube NM2 is connected with the grid electrode of the first NMOS tube NM1, and the grid electrode of the first PMOS tube PM1 is in short circuit with the drain electrode;
the grid electrode of the third NMOS tube NM3 is connected with the drain electrode of the first NMOS tube NM1, the drain electrode is connected with the drain electrode of the first PMOS tube PM1, and the source electrode is connected with the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube;
The first end of the second resistor R2 is connected with the grid electrode of the first NMOS tube NM1 and the grid electrode of the second NMOS tube NM2, the second end of the second resistor R2 is connected with a reference potential, and the resistance value of the second resistor R2 is 1/2 of the resistance value of the first resistor R1;
The source electrode of the second PMOS tube PM2 is connected with the input voltage VIN, the grid electrode of the second PMOS tube PM1 is connected with the grid electrode of the first PMOS tube PM1, the drain electrode of the second PMOS tube PM2 is connected with the first polar plate of the capacitor C, and the second polar plate of the capacitor C is connected with the reference potential;
the grid electrode of the fourth NMOS tube NM4 is connected with a grid electrode control signal, the drain electrode of the fourth NMOS tube NM4 is connected with the drain electrode of the second PMOS tube PM2, and the source electrode of the fourth NMOS tube NM4 is connected with a reference potential;
the ramp signal generator forms a ramp signal according to the current generated by the adaptive fixed off-time regulator, and outputs the ramp signal from the drain of the second PMOS transistor PM2 and the drain of the fourth NMOS transistor NM 4.
8. The PWM control circuit of claim 1, wherein the multiphase DC-DC buck converter includes 4 power stages, the phase divider outputs 4 divided signals with 90 ° phase distribution according to the clock signal, the fixed off-time generator generates 4 fixed off-time pulse signals Toff 1-Toff 4 according to the 4 divided signals with 90 ° phase distribution, and the peak current mode PWM controller generates 4 gate control signals for controlling the power stages according to the 4 fixed off-time pulse signals Toff 1-Toff 4 and peak current signals of the 4 power stages.
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| CN105245103A (en) * | 2014-07-01 | 2016-01-13 | 德克萨斯仪器股份有限公司 | DC to DC converter and pwm controller with adaptive compensation circuit |
| CN113517814A (en) * | 2021-08-26 | 2021-10-19 | 上海泰矽微电子有限公司 | BOOST switch converter and minimum closing time control circuit |
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| EP2750276A1 (en) * | 2012-12-28 | 2014-07-02 | Dialog Semiconductor GmbH | Phase lock loop controlled current mode buck converter |
| CN113556039B (en) * | 2021-07-22 | 2022-08-30 | 无锡职业技术学院 | Control system and method of multiphase DC-DC converter |
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| CN105245103A (en) * | 2014-07-01 | 2016-01-13 | 德克萨斯仪器股份有限公司 | DC to DC converter and pwm controller with adaptive compensation circuit |
| CN113517814A (en) * | 2021-08-26 | 2021-10-19 | 上海泰矽微电子有限公司 | BOOST switch converter and minimum closing time control circuit |
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