CN114116582B - Motherboard and electronic equipment - Google Patents
Motherboard and electronic equipmentInfo
- Publication number
- CN114116582B CN114116582B CN202111346435.8A CN202111346435A CN114116582B CN 114116582 B CN114116582 B CN 114116582B CN 202111346435 A CN202111346435 A CN 202111346435A CN 114116582 B CN114116582 B CN 114116582B
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- China
- Prior art keywords
- ddr
- particles
- chip
- interface
- motherboard
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/321—Display for diagnostics, e.g. diagnostic result display, self-test user interface
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Computer Hardware Design (AREA)
- Human Computer Interaction (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a main board and electronic equipment. The mainboard comprises a PCB board, wherein a CPU chip and a DDR circuit which are mutually connected are integrated on the PCB board, a DDR controller is arranged in the CPU chip, the CPU chip is provided with a DDR interface for externally connecting the DDR controller, a signal end of the DDR circuit is directly connected with the DDR interface through a metal wire, the DDR circuit is arranged on the front surface of the PCB board, and a DDR signal test point is arranged at the position of the back surface of the PCB board opposite to the DDR circuit. The invention can test the signal quality of the DDR interface of the CPU chip.
Description
Technical Field
The present invention relates to the field of electronic device boards, and in particular, to a motherboard and an electronic device.
Background
In practical application of a motherboard, many problems are found to be related to DDR (Double DATA RATE SDRAM, double-rate synchronous dynamic random access Memory), but because there are no test points on a Memory bank of the existing motherboard, and DDR particles are ball grid array packages, and solder joints are hidden under DDR particles, so that testing and positioning DDR interface problems, especially when the signal rate of the DDR interface is not up, if an oscilloscope is used to observe actual signal waveforms, an oscilloscope probe cannot approach the actual DDR particle pin positions, and the actual signal waveform quality at the DDR particle pin positions cannot be observed, further because the Memory bank is typically a DIMM (Dual-Inline-Memory-Modules) mode, the Memory bank is connected to a CPU through a DIMM slot connector, and interference introduced by the DIMM slot connector cannot be removed when the signal waveforms are observed by using the oscilloscope. To solve these problems, to better observe the DDR signal quality, find the root cause that affects the DDR signal rate and other problems, it is necessary to propose a new motherboard structure.
Disclosure of Invention
In order to solve the above problems, the present invention provides a motherboard and an electronic device, which are suitable for testing the signal quality of the DDR interface of the CPU chip.
In a first aspect, the present invention provides a motherboard comprising a PCB board on which are integrated a CPU chip and a DDR circuit interconnected, the CPU chip having a DDR controller built therein,
The CPU chip is provided with a DDR interface for externally connecting the DDR controller;
the signal end of the DDR circuit is directly connected with the DDR interface through a metal wire;
and the DDR circuit is arranged on the front surface of the PCB, and the back surface of the PCB is provided with DDR signal test points relative to the DDR circuit.
Optionally, the DDR circuit adopts an RDIMM mode.
Optionally, the DDR circuit includes two sets of DDR particles, an RCD chip, and an SPD chip, wherein,
Each group of DDR particles comprising a plurality of DDR particles, wherein a data signal of each DDR particle is directly connected to the DDR interface;
The RCD chip is used for dividing a group of command and address signals connected with the DDR interface into two groups of identical command and address signals, wherein the two groups of command and address signals are respectively connected with one group of DDR particles, and clock signals and chip selection signals are distributed to the two groups of DDR particles;
The SPD chip is connected with the RCD chip through an SMBUS and is connected to an SMBUS interface of the CPU chip.
Optionally, the two sets of DDR particles include 18 DDR particles in total, one set including 10 DDR particles, 8 DDR particles for transmitting data signals, 2 DDR particles for transmitting ECC signals, and the other set including 8 DDR particles for transmitting data signals.
Optionally, the 18 DDDR particles are designed with a 2Rank design, numbered from 0 to 17 in sequence, all even DDR particles forming a first Rank, all odd DDR particles forming a second Rank;
the first Rank is arranged in a column, the second Rank is arranged in a column, 1 DDR particle positioned in the middle of each column is used for transmitting 8-bit ECC signals, and 8 DDR particles on two sides are used for transmitting 64-bit data signals;
two DDR particles for transmitting 8-bit ECC signals form one group of DDR particles together with 8 DDR particles on one side of the DDR particles, and the other group of DDR particles is formed together with 8 DDR particles on the other side of the DDR particles for transmitting 8-bit ECC signals.
Optionally, the 18 DDDR particles are arranged on the front surface of the PCB, and DDR signal test points are disposed on the back surface of the PCB at positions corresponding to the 18 DDDR particles.
Optionally, the CPU chip is disposed on the front surface of the PCB, and a via hole is disposed beside a pin of the DDR interface, and a back surface of the via hole is used as a DDR interface signal test point.
Optionally, the CPU chip is further provided with the following interfaces, including:
2 PCIe x16 interfaces for connecting 2 PCIe x16 slots;
4 SATA interfaces for connecting to a standard SATA disk;
PCIe x2 interface for connecting one gigabit network chip I350;
2 USB interfaces.
Optionally, a BMC chip is integrated on the PCB, and the BMC chip is interconnected with the CPU chip through an SPI interface, an LPC interface and a USB interface.
In a second aspect, the present invention provides an electronic device, including the motherboard described above.
The mainboard and the electronic equipment provided by the invention are suitable for testing the signal quality of the DDR interface of the CPU chip, and because the DDR circuit is directly integrated on the mainboard and is not connected through a connector, the influence caused by the connector is eliminated, the maximum performance of the DDR interface of the CPU chip is conveniently tested, the signal quality can be better observed by an oscilloscope, and the comparison research of signal testing and performance testing is realized. And meanwhile, the DDR circuit is integrated on the main board, so that the shock resistance is stronger than that of the slot, and the system reliability is higher.
Drawings
FIG. 1 is a schematic view of a motherboard frame structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a motherboard PCB layout according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a motherboard frame structure according to an embodiment of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Some embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
Fig. 1 is a schematic diagram of a frame structure of a motherboard according to an embodiment of the present invention. The motherboard includes a PCB (Printed Circuit Board ), hereinafter referred to as a PCB board. As shown in FIG. 1, a CPU chip and a DDR circuit are integrated on a PCB, a DDR controller is arranged in the CPU chip, wherein the CPU chip is provided with a DDR interface for externally connecting the DDR controller, a signal end of the DDR circuit is directly connected with the DDR interface through a metal wire, the DDR circuit is arranged on the front surface of the PCB, and a DDR signal test point is arranged on the back surface of the PCB opposite to the DDR circuit.
As an implementation manner, the DDR circuit of this embodiment may adopt an RDIMM (REGISTERED DIMM, dual in-line memory module with register) manner. The RDIMM adds a register on the memory bar for transmission, and the register is positioned between the CPU and the DDR particles, so that the parallel transmission distance is reduced, and the parallel transmission effectiveness is ensured. Because of the high register efficiency, the capacity and frequency of RDIMM is more easily increased than unbuffered DIMMs.
Specifically, referring to fig. 1, the rdimm mode DDR circuit includes two sets of DDR particles, 1 RCD chip, and 1 SPD chip. The RCD chip, REGISTERING CLOCK DRIVER, the clock buffer register chip is used for buffering the command and address signals of the DDR controller, dividing the command and address signals from the DDR controller into two parts, and reducing the delay from the command and address signals to DDR particles. The SPD chip, SERIAL PRESENCE DETECT, serial image detecting chip, is one erasable memory with several important information recorded, including basic parameters, such as frequency, capacity, time sequence, etc. and memory module serial number, manufacturer code, etc. The SPD information is generally written into the SPD chip by a manufacturer according to the actual performance of the memory before leaving the factory.
The two sets of DDR particles include 18 DDR particles, which can be denoted as a set and a set B, where the set a includes 10 DDR particles, where 8 DDR particles are used to transmit data signals, and 2 DDR particles are used to transmit ECC (Error Correcting Code, error correction code) signals. Group B includes 8 DDR particles for transmitting data signals. The data signal (including the ECC signal) of each DDR particle is directly connected to the CPU DDR interface without any switching.
A group of command and address signals connected with the DDR interface of the CPU chip are divided into two groups A and B through the RCD chip. The group a command and address signal connections drive the 10 DDR particles of group a. Group B command and address signals connect the 8 DDR particles driving group B. The RCD chip is used for dividing a group of Command and Address signals transmitted by the CPU chip into two groups of identical Command and Address signals, and driving two groups of DDR particles positioned on two sides respectively, so that signal wiring of a DIMM memory bar can be optimized, signal driving capability is enhanced, and DDR interface speed is improved. The data rate of the current DDR4RDIMM memory bank can reach 3200MT/s. In addition, the RCD chip is also used to distribute clock signals and chip select signals to the two sets of DDR particles. Referring to fig. 1, the chip select signal cs0_a and the clock signal CLK0 connect DDR8, DDR10, DDR12, DDR14 and DDR16, the chip select signal csi_a and the clock signal CLK1 connect DDR9, DDR11, DDR13, DDR15 and DDR17, the chip select signal cs0_b and the clock signal CLK2 connect DDR0, DDR2, DDR4 and DDR6, and the chip select signal cs1_b and the clock signal CLK3 connect DDR1, DDR3, DDR5 and DDR7.
In addition, the SPD chip is connected to the RCD chip through an SMBUS (SYSTEM MANAGEMENT Bus ), and is connected to an SMBUS interface of the CPU chip. The DDR particles are configured in such a way, the DDR particles can be directly configured through the DDR interface of the CPU, configuration data can be written into the SPD chip, and the DDR particles are configured through the SPD chip.
Of course, DDR circuitry is not limited to RDIMM. For example, the LRDIMM (Load Reduced DIMM, low-load dual in-line memory module) may be used. Compared with RDIMM, LRDIMM does not use complex registers, but simply buffers, which reduces the power load on the lower motherboard, but has little impact on memory performance. In addition, the LRDIMM memory changes a Register chip on the RDIMM memory into a iMB (isolation Memory Buffer) memory isolation buffer chip, which has the direct advantages of reducing the load of a memory bus and further improving the memory support capacity.
The mainboard provided by the embodiment of the invention is suitable for testing the signal quality of the DDR interface of the CPU chip, and because the DDR circuit is directly integrated on the mainboard and is not connected through a connector, the influence caused by the connector is eliminated, the maximum performance of the DDR interface of the CPU chip is conveniently tested, the signal quality can be better observed by an oscilloscope, and the comparison research of signal testing and performance testing is realized. And meanwhile, the DDR circuit is integrated on the main board, so that the shock resistance is stronger than that of the slot, and the system reliability is higher. The design method for integrating the RCD and the DDR circuit on the main board can also be applied to designs requiring the integrated DDR controller and the DDR particles on the same PCB board, such as system designs with high reliability, such as VPX (VPX is the next generation advanced computing platform standard formulated by VITA organization to meet the requirements of high reliability and high bandwidth in severe environments), CPU chip external DDR designs, FPGA external DDR designs, embedded DDR designs and the like. Namely, the invention is not only applied to the field of testing, but also applied to the design of an actual product system.
Further, the 18 DDR particles are designed by a 2Rank, wherein Rank refers to a unit of 64-bit formed by a plurality of DDR particle data bits, and the unit is selectively accessed through a CS chip selection signal. For an ECC DIMM, a memory Rank has 72 data bits, including 64bits data+8bits ECC. In this embodiment, 18 DDR particles are numbered from 0 to 17, and all even DDR particles form a first Rank, including DDR0, DDR2, DDR4, DDR6, DDR8, DDR10, DDR12, DDR14, DDR16, denoted Rank0, and DDR8 in Rank0 is an ECC particle. All odd DDR particles constitute a second Rank, including DDR1, DDR3, DDR5, DDR7, DDR9, DDR11, DDR13, DDR15, DDR17, denoted Rank1, where DDR9 is an ECC particle.
Specifically to layout and grouping, the first Rank is arranged in one column, the second Rank is arranged in one column, and 1 DDR particle located in the middle of each column is used for transmitting 8-bit ECC signals, and 8 DDR particles on two sides are used for transmitting 64-bit data signals. Specifically, DDR0 and DDR1 transmit data signals DQ [7:0], DDR2 and DDR3 transmit data signals DQ [15:8], DDR4 and DDR5 transmit data signals DQ [23:16], DDR6 and DDR7 transmit data signals DQ [31:24], DDR8 and DDR9 transmit data signals ECC [7:0], DDR10 and DDR11 transmit data signals DQ [39:32], DDR12 and DDR13 transmit data signals DQ [47:40], DDR14 and DDR15 transmit data signals DQ [55:48], DDR16 and DDR17 transmit data signals DQ [63:56].
During grouping, two DDR particles for transmitting 8-bit ECC signals and 8 DDR particles on one side of the DDR particles form an A group DDR particle, and two DDR particles for transmitting 8-bit ECC signals and 8 DDR particles on the other side of the DDR particles form a B group DDR particle. I.e., DDR8-17 are group A and DDR0-7 are group B. The 18 DDDR particles are arranged on the front surface of the PCB, and DDR signal test points are arranged at positions, opposite to the 18 DDR particles, on the back surface of the PCB. The design is convenient for testing the signal quality.
Similarly, the CPU chip is arranged on the front surface of the PCB, and DDR interface signal test points are also arranged at corresponding positions on the back surface of the CPU, so that the quality of signals at the two ends of the test signal transceiver can be conveniently observed by tools such as an oscilloscope. The design method of the test point is DDR particles, the through hole is directly drilled beside the pin of the CPU chip to the back, copper is exposed on the through hole on the back to serve as the test point, thus, the oscilloscope is used for testing the signal quality on the test point, the distance from the oscilloscope probe to the pin of the actual chip is extremely short, and the signal waveform quality at the pin of the chip can be reflected. Fig. 2 shows the layout and test point distribution of a motherboard PCB. FIG. 2 shows the distribution of the CPU, RCD and DDR0-17, wherein the black dots inside the CPU, RCD and DDR0-17 represent signal test points, which are designed according to the pin distribution of the chip.
The above embodiment is 1DPC (1 RCD on 1 DDR circuit, i.e. 1 DDR circuit is connected to one DDR controller on the motherboard), 2Rank design, and may be extended to 2DPC (2 DDR circuits are connected to one DDR controller on the motherboard), i.e. 2DPC,1r design, or 2DPC,2r design.
In addition, referring to fig. 3, the cpu chip is designed with the following interfaces in addition to the DDR interface of the external DDR circuit:
2 PCIe x16 interfaces, which are used for connecting 2 PCIe x16 slots and can be inserted with standard PCIe cards;
4 SATA interfaces for connecting to a standard SATA disk;
PCIe x2 interface, external to one gigabit network chip I350, I350 out of 2 gigabit electrical port network;
and 2 USB interfaces, which integrate and support USB2.0 and USB3.0 standards.
In addition, the motherboard is integrated with a BMC (Baseboard Manager Controller, baseboard management controller) chip, and is used as a management unit of the motherboard, and is interconnected with the CPU through interfaces such as PCIe x1, LPC (Low Pin Count), USB, SPI (SERIAL PERIPHERAL INTERFACE) and the like. The BMC chip comprises the following peripheral interfaces:
And the kilomega RJ45 interface is a remote management interface, and is realized by externally connecting a kilomega PHY chip to a BMC chip. The remote management platform realizes the management of the main board through the gigabit network.
COM interface, serial interface;
VGA interface, display interface, connect display device;
LED port80, which is connected with a nixie tube and displays the CPU state;
FAN control interface, FAN speed is controlled;
SD Card interface, store server log information;
In addition, BMC FW (Firmware) is Firmware of the BMC system itself, and is stored in BMC FW Flash.
The interconnection relationship between the BMC chip and the CPU chip comprises:
SPI interconnection-the CPU BIOS can Switch to connect to the BMC or to the CPU through SPI SW (Switch). When the BIOS firmware is upgraded, the switch is connected to the BMC. And when the power-on is operated normally, switching to the CPU. In this way, the CPU BIOS firmware can be upgraded through the remote management platform, namely the remote management platform sends a new BIOS to the BMC through the gigabit RJ45 interface of the BMC, the BMC rewrites the BIOS chip, then the BMC is switched to the CPU through the SPI SW, and the CPU can be started to use the new BIOS firmware.
LPC interconnection, namely an LPC interface interconnected between the BMC and the CPU is used for transmitting the state information of the starting operation of the CPU, and the state information is displayed through an LED PORT80 connected with the BMC after being transmitted to the BMC. And is also connected to CPLD (Complex Programmable Logic Device ) to inform CPLD of CPU starting running state.
The USB interface is used for realizing the remote virtual machine, namely the remote management platform is connected to the BMC through the BMC gigabit RJ45 network interface and then connected to the CPU through the USB interface of the BMC.
On the other hand, the embodiment of the invention also provides electronic equipment, which comprises the main board of the embodiment.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (10)
1. A motherboard is characterized in that the motherboard comprises a PCB board, a CPU chip and a DDR circuit are integrated on the PCB board, the DDR circuit comprises a plurality of DDR particles, the CPU chip is internally provided with a DDR controller, wherein,
The CPU chip is provided with a DDR interface for externally connecting the DDR controller;
the signal end of the DDR circuit is directly connected with the DDR interface through a metal wire;
and the DDR particles are arranged on the front surface of the PCB, and DDR signal test points are arranged on the back surface of the PCB opposite to the positions of the DDR particles.
2. The motherboard of claim 1, wherein the DDR circuit is implemented by way of RDIMM.
3. The motherboard of claim 2, wherein the DDR circuit further comprises an RCD chip and an SPD chip, wherein,
The plurality of DDR particles are divided into two groups, wherein the data signal of each DDR particle is directly connected to the DDR interface;
The RCD chip is used for dividing a group of command and address signals connected with the DDR interface into two groups of identical command and address signals, wherein the two groups of command and address signals are respectively connected with one group of DDR particles, and clock signals and chip selection signals are distributed to the two groups of DDR particles;
The SPD chip is connected with the RCD chip through an SMBUS and is connected to an SMBUS interface of the CPU chip, and the SPD chip stores configuration data of the DDR particles.
4. The motherboard of claim 3 wherein said two sets of DDR particles include a total of 18 DDR particles, one set including 10 DDR particles, 8 DDR particles for transmitting data signals, 2 DDR particles for transmitting ECC signals, and the other set including 8 DDR particles for transmitting data signals.
5. The motherboard of claim 4, wherein the 18 DDR particles are of a 2 Rank design, numbered sequentially from 0 to 17, all even DDR particles comprising a first Rank, all odd DDR particles comprising a second Rank;
the first Rank is arranged in a column, the second Rank is arranged in a column, 1 DDR particle positioned in the middle of each column is used for transmitting 8-bit ECC signals, and 8 DDR particles on two sides are used for transmitting 64-bit data signals;
two DDR particles for transmitting 8-bit ECC signals form one group of DDR particles together with 8 DDR particles on one side of the DDR particles, and the other group of DDR particles is formed together with 8 DDR particles on the other side of the DDR particles for transmitting 8-bit ECC signals.
6. The motherboard of claim 5, wherein the 18 DDR particles are disposed on a front side of the PCB, and wherein a back side of the PCB is provided with DDR signal test points at positions opposite to the 18 DDR particles.
7. The motherboard of claim 1, wherein the CPU chip is disposed on a front side of the PCB board, and a via is disposed beside a pin of the DDR interface, and a back side of the via is used as a DDR interface signal test point.
8. The motherboard of claim 1, wherein the CPU chip is further provided with an interface comprising:
2 PCIe x16 interfaces for connecting 2 PCIe x16 slots;
4 SATA interfaces for connecting to a standard SATA disk;
PCIe x2 interface for connecting one gigabit network chip I350;
2 USB interfaces.
9. The motherboard of claim 1, wherein a BMC chip is integrated on the PCB, and the BMC chip is interconnected with the CPU chip through an SPI interface, an LPC interface, and a USB interface.
10. An electronic device comprising the motherboard of any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111346435.8A CN114116582B (en) | 2021-11-15 | 2021-11-15 | Motherboard and electronic equipment |
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| CN202111346435.8A CN114116582B (en) | 2021-11-15 | 2021-11-15 | Motherboard and electronic equipment |
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| CN114116582B true CN114116582B (en) | 2025-09-19 |
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| KR20100113667A (en) * | 2009-04-14 | 2010-10-22 | (주)에이젯 | Board for testing graphic ddr memory component |
| CN213365381U (en) * | 2020-11-25 | 2021-06-04 | 海光信息技术股份有限公司 | Main board |
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| JP4786262B2 (en) * | 2005-09-06 | 2011-10-05 | ルネサスエレクトロニクス株式会社 | Interface circuit |
| JP5165404B2 (en) * | 2007-06-06 | 2013-03-21 | ルネサスエレクトロニクス株式会社 | Semiconductor device, semiconductor device manufacturing method and test method |
| CN102802350A (en) * | 2011-05-27 | 2012-11-28 | 鸿富锦精密工业（深圳）有限公司 | Circuit board assembly and test-assisting circuit board thereof |
| CN103176870B (en) * | 2013-03-21 | 2014-12-03 | 中国铁道科学研究院 | Multi-mode information interaction redundancy safety computer platform |
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| CN104572385B (en) * | 2014-12-29 | 2021-04-09 | 中星技术股份有限公司 | Memory fault detection system and method |
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| CN112103265B (en) * | 2019-10-10 | 2022-08-30 | 炬力(珠海)微电子有限公司 | Main control chip, PCB board and electronic equipment |
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| KR20100113667A (en) * | 2009-04-14 | 2010-10-22 | (주)에이젯 | Board for testing graphic ddr memory component |
| CN213365381U (en) * | 2020-11-25 | 2021-06-04 | 海光信息技术股份有限公司 | Main board |
| CN216249224U (en) * | 2021-11-15 | 2022-04-08 | 成都海光集成电路设计有限公司 | Mainboard and electronic equipment |
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