CN114070112B - Neutral point potential fast balance control method of three-level inverter - Google Patents

Abstract

The invention provides a fast balance control method for the neutral point potential of a three-level inverter. The method converts the complex modulation problem into an algebraic problem from an algebraic point of view. On the premise of ensuring the input-output relationship, the midpoint potential balance can be ensured without additional control, and the asymmetry of the capacitance parameters does not affect the effect of the midpoint potential balance.

Description

A Fast Balance Control Method for Neutral Point Potential of Three-level Inverter

technical field

The invention relates to the field of electric energy conversion devices, in particular to a method for quickly balancing the neutral point potential of a three-level inverter.

Background technique

In recent years, three-level inverters have been widely used in high-power applications such as motor drives, active filters, and DC/AC converters. In the research field of three-level inverters, most experts and scholars mainly start from the following two aspects: one is to optimize and innovate the topology of three-level inverters in terms of hardware, which can be divided into Midpoint clamp type, flying capacitor type and cascaded H-bridge type. The neutral point clamping type can be divided into diode neutral point clamping type, active neutral point clamping type and T-type neutral point clamping type. The second is the improvement of its software algorithm, and one of the key points is the research on its modulation strategy.

Among them, the T-type neutral-point clamped three-level inverter has been widely used because of its relatively simple topology and operating mechanism, and its control strategy is not particularly complicated. However, this topology also has an inherent problem: the DC side voltage of this topology is supported by two sets of equivalent capacitors in series, and the potential of the middle point is likely to be unbalanced, which will affect the power supply to a certain extent. If the quality of the output waveform is not properly controlled, it may even happen that the entire DC bus voltage is added to a capacitor, causing damage to the components.

In order to solve the problem of unbalanced midpoint potential, many scholars have conducted research on it and put forward their own schemes from different angles. It can be roughly divided into two categories: hardware measures and software measures. The so-called hardware measures are to add additional hardware to the three-level inverter topology, increase the degree of freedom of control, and maintain the same potential of the upper and lower capacitors. This method needs to add a large number of hardware devices to make the circuit complex, reduce the power density, increase the difficulty of hardware debugging, and increase the cost, so it is generally not recommended. Among software measures, it is common to improve its modulation method.

Contents of the invention

In order to solve the above technical problems, the present invention proposes a fast balance control method for the neutral point potential of a three-level inverter. From an algebraic point of view, the complex modulation problem is transformed into an algebraic problem. On the premise of ensuring the relationship between input and output Under this condition, the midpoint potential balance can be ensured without additional control, and the asymmetry of the capacitance parameters does not affect the midpoint potential balance effect.

A method for quickly balancing the neutral point potential of a three-level inverter, comprising the following steps:

Step 1, taking the T-type three-level inverter as an example, make the capacitance values of the upper and lower busbars equal, and establish the average model of the input and output of the T-type three-level inverter and the switching state of the neutral point potential;

Taking the AC side inductance L as the state variable, write out the state equation of the T-type three-level inverter:

Among them, u _ao , u _bo , u _co are the phase voltages with reference to the middle point o of the upper and lower bus capacitors, u _an , ub _n , u _cn are the phase voltages with reference to the neutral point n of the three-phase AC voltage, e _a , e _b , e _c are the grid voltage, _ia , i _b , _ic are the grid side current, L is the AC side filter inductance,

After taking the average of the switch state for the input and output voltages, the relationship is as follows:

Among them, u ₁ and u ₂ are the voltages of two discrete capacitors on the DC side, and d _ij (i=a,b,c; j=P,N) is the duty cycle of the three-phase upper and lower bridge arm switching devices, satisfying d _iP ≥0,d _iN ≥0,0≤d _iP +d _iN ≤1(i=a,b,c),

After taking the average of the switch state for the midpoint potential, the relationship is as follows:

Step 2, analyze the model, introduce the degrees of freedom m and γ;

Introduce degrees of freedom m and γ _i (i=a,b,c), m is used to ensure that each element meets the physical constraints, γ _i (i=a,b,c) is used to balance the midpoint potential, then each phase P The duty cycle d _ij (i=a,b,c; j=P,N) of state and N state can be written as:

Substituting the above formula into formula (4), the average model of the switching state of the midpoint potential is simplified as:

It can be seen from the above formula that by selecting the value of the degree of freedom γ _i (i=a,b,c), the midpoint potential is balanced,

Step 3, based on the fractional-order sliding mode control theory, determine the value of the degree of freedom γ, prove that the midpoint potential can be balanced in a finite time, and give a calculation formula for the balance time;

Based on the fractional-order sliding mode control theory, the value of the degree of freedom γ _i (i=a,b,c) is shown in formula (10),

Substituting Equation (10) into Equation (7) can obtain the final average model of the midpoint potential switch state,

For the system represented by formula (11), the Lyapunov function is selected as:

Deriving it, and substituting formula (11) into:

Thus there are:

make:

Because ε>0,0<α<1, then c>0,0<η<1, that is, there are real numbers c>0 and 0<η<1, so that V(t) is upper positive definite sum /> at /> Semi-negative definite, finite convergence time maximum t _{z_max} satisfies:

Where t _{z_max} represents the maximum time required for the error to converge to zero, Indicates the difference between the upper and lower capacitor voltages on the DC side in the initial state;

Step 4, analyze the working conditions when the upper and lower busbar capacitances are not equal;

When the capacitance of the upper and lower busbars is asymmetrical, the midpoint potential can still be balanced,

Prove that "when the capacitance is asymmetric, the midpoint potential can still be balanced":

When the upper and lower capacitance values on the DC bus side are not equal, that is, when C ₁ ≠ C ₂ , the average model of the switching state of the neutral point current can be expressed as:

make:

Substitute formula (18) into formula (17):

Comparing Equation (19) and Equation (11), it can be seen that when C ₁ ≠ C ₂ , the finite time convergence is still satisfied, therefore, when the capacitance parameters are asymmetrical, the neutral point potential can also be quickly balanced;

Step 5, determine the range of the degree of freedom m, and select the value of m;

m is used to ensure that each element satisfies the physical constraints in the steady state. In the steady state, that is, when the midpoint potential has been balanced, it can be known from equations (7) and (10):

Then the expression of the duty cycle is simplified to:

According to the requirements that the input and output terminals cannot be short-circuited or disconnected and the limitations of physical implementation, the duty cycle must meet the following constraints:

Substituting formula (21) into formula (22), the value range of m can be obtained as follows:

In order to reduce the number of switches, here take At this time, the T-type three-level inverter is in the linear modulation region;

Step 6, determine the range of zero-sequence voltage, and select the value of zero-sequence voltage;

Determine the range of zero sequence voltage:

in

Simplify the inequality (24):

-u ₁ +max{u _an ,u _bn ,u _cn }≤u _on ≤u ₂ +min{u _an ,u _bn ,u _cn } (25)

Take here where, />

Step 7, substituting each variable into the expression of the duty cycle, and then obtaining the switching sequence of all power switch tubes of the T-type three-level inverter;

Substituting the values of m and γ into equation (6), the final expression of each duty cycle can be obtained:

Among them, in one switching period, the duty cycle is distributed, and then the switching sequence of all power switch tubes of the T-type three-level inverter is obtained. When d=d _iP (i=a,b,c), it represents Only open the switching tube of the upper bridge arm of the i phase; when d=d _iN (i=a, b, c), it represents only the switching tube of the lower bridge arm of the i phase; when d=d _iO (i=a ,b,c), it means that only the two switch tubes connected to the neutral point of phase i are turned on.

As a further improvement of the present invention: in step 3, the concept of nonlinear system finite time stability, consider the following system:

Where: f: U ₀ ×R→R ⁿ is continuous at U ₀ ×R, U ₀ is an open neighborhood of the origin x=0,

For the considered system (8), based on the finite-time stability theory of nonlinear control systems, the following lemmas are given:

Lemma 1: Consider the nonlinear system (8), assuming that there exists a neighborhood defined at the origin The smooth function V(x) on , and there are real numbers c>0 and 0<η<1, so that V(x) in /> upper positive definite sum /> exist semi-negative definite, then the origin of system (8) is stable in finite time, and the rest time depends on the initial value x(0)=x ₀ , and its upper bound is: />

Among them: x ₀ is any point in an open neighborhood of the origin, if And V(x) is radially unbounded, that is, when ||x||→+∞, V(x)→+∞, then the origin of system (8) is globally finite-time stable.

As a further improvement of the present invention: in step 3, because ε>0,0<α<1, then c>0,0<η<1, that is, there are real numbers c>0 and 0<η<1, so that V( t) at upper positive definite sum /> at /> Negative semi-definite, so the nonlinear system (11) satisfies the condition of Lemma 1.

As a further improvement of the present invention: in step 3, it can be seen from Lemma 1 that the system (11) converges in a finite time, and the maximum value t _{z_max} of the finite convergence time satisfies:

Compared with prior art, the beneficial effect of the present invention is:

The neutral point potential rapid balance control method of the three-level inverter based on algebraic operation proposed by the present invention converts the complex modulation problem into an algebraic operation problem from the algebraic point of view, reduces the modulation complexity, and selects the degree of freedom The values of m and γ, under the premise of satisfying the physical constraints, realize the rapid balance of the neutral point potential. The method is simple and universal, and it can guide the proposal of modulation strategies for other power electronic converters.

Description of drawings

Fig. 1 is the schematic diagram of topology structure and control circuit hardware of the embodiment of the present invention;

Fig. 2 is the working principle of the topology of the embodiment of the present invention;

Fig. 3 is a system structure diagram of an embodiment of the present invention;

Fig. 4 is the simulation waveform diagram a of the steady-state power grid voltage, current, output line voltage and midpoint potential when the system is in the unit power factor and non-unit power factor two working conditions when the upper and lower capacitances are equal in the embodiment of the present invention;

Fig. 5 is a simulation waveform diagram b of the steady-state power grid voltage, current, output line voltage and midpoint potential when the system is in the unit power factor and non-unit power factor working conditions when the upper and lower capacitances are equal in the embodiment of the present invention;

Fig. 6 is a balance process diagram a of the midpoint potential when the upper and lower capacitances are equal but the initial voltages are not equal according to the embodiment of the present invention;

Fig. 7 is the balance process diagram b of the midpoint potential when the upper and lower capacitances are equal but the initial voltages are not equal according to the embodiment of the present invention;

Fig. 8 is a balance process diagram of the midpoint potential when the upper and lower capacitances and initial voltages are not equal according to an embodiment of the present invention.

FIG. 9 is a parameter diagram of a grid-connected simulation platform system of a T-type three-level inverter in an embodiment of the present invention.

Detailed ways

In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will be described in detail in conjunction with the accompanying drawings and specific embodiments:

The invention provides a fast balance control method for neutral point potential of a three-level inverter. The method converts complex modulation problems into algebra problems from an algebraic point of view. Under the premise of ensuring the relationship between input and output, the midpoint potential balance can be ensured without additional control, and the asymmetry of the capacitance parameters does not affect the effect of the midpoint potential balance.

A method for quickly balancing the neutral point potential of a three-level inverter, comprising the following steps:

Step 1, taking the T-type three-level inverter as an example, make the capacitance values of the upper and lower busbars equal, and establish the average model of the input and output of the T-type three-level inverter and the switching state of the neutral point potential;

Taking the AC side inductance L as the state variable, write out the state equation of the T-type three-level inverter:

Among them, u _ao , u _bo , u _co are the phase voltages with reference to the middle point o of the upper and lower bus capacitors, u _an , u _bn , u _cn are the phase voltages with reference to the neutral point n of the three-phase AC voltage, e _a , e _b , e _c are the grid voltage, i _a , i _b , _ic are the grid side current, L is the AC side filter inductance, after taking the average of the input and output voltages, the relationship is as follows:

Among them, u ₁ and u ₂ are the voltages of two discrete capacitors on the DC side, and d _ij (i=a,b,c; j=P,N) is the duty cycle of the three-phase upper and lower bridge arm switching devices, satisfying d _iP ≥0,d _iN ≥0,0≤d _iP +d _iN ≤1(i=a,b,c),

After taking the average of the switch state for the midpoint potential, the relationship is as follows:

Step 2, analyze the model, introduce the degrees of freedom m and γ;

Introduce degrees of freedom m and γ _i (i=a,b,c), m is used to ensure that each element meets the physical constraints, γ _i (i=a,b,c) can be used to balance the midpoint potential, then each phase The duty cycle d _ij (i=a,b,c; j=P,N) of P state and N state can be written as:

Substituting the above formula into formula (4), the average model of the switching state of the midpoint potential is simplified as:

It can be seen from the above formula that by selecting the value of the degree of freedom γ _i (i=a,b,c), the midpoint potential is balanced,

Step 3, based on the fractional-order sliding mode control theory, determine the value of the degree of freedom γ, prove that the midpoint potential can be balanced in a finite time, and give a calculation formula for the balance time;

Based on the fractional-order sliding mode control theory, the value of the degree of freedom γ _i (i=a,b,c) is shown in formula (10),

Substituting Equation (10) into Equation (7) can obtain the final average model of the midpoint potential switch state,

For the system represented by formula (11), the Lyapunov function is selected as:

Deriving it, and substituting formula (11) into:

Thus there are:

make:

Because ε>0,0<α<1, then c>0,0<η<1, that is, there are real numbers c>0 and 0<η<1, so that V(t) is upper positive definite sum /> at /> Semi-negative definite, finite convergence time maximum t _{z_max} satisfies:

Where t _{z_max} represents the maximum time required for the error to converge to zero, Indicates the difference between the upper and lower capacitor voltages on the DC side in the initial state;

Step 4, analyze the working conditions when the upper and lower busbar capacitances are not equal;

When the capacitance of the upper and lower busbars is asymmetrical, the midpoint potential can still be balanced,

Prove that "when the capacitance is asymmetric, the midpoint potential can still be balanced":

When the upper and lower capacitance values on the DC bus side are not equal, that is, when C ₁ ≠ C ₂ , the average model of the switching state of the neutral point current can be expressed as:

make:

Substitute formula (18) into formula (17):

Comparing Equation (19) and Equation (11), it can be seen that when C ₁ ≠ C ₂ , the finite time convergence is still satisfied, therefore, when the capacitance parameters are asymmetrical, the neutral point potential can also be quickly balanced;

Step 5, determine the range of the degree of freedom m, and select the value of m;

m is used to ensure that each element satisfies the physical constraints in the steady state. In the steady state, that is, when the midpoint potential has been balanced, it can be known from equations (7) and (10):

Then the expression of the duty cycle is simplified to:

According to the requirements that the input and output terminals cannot be short-circuited or disconnected and the limitations of physical implementation, the duty cycle must meet the following constraints:

Substituting formula (21) into formula (22), the value range of m can be obtained as follows:

In order to reduce the number of switches, here take At this time, the T-type three-level inverter is in the linear modulation region;

Step 6, determine the range of zero-sequence voltage, and select the value of zero-sequence voltage;

Determine the range of zero sequence voltage:

in

Simplify the inequality (24):

-u ₁ +max{u _an ,u _bn ,u _cn }≤u _on ≤u ₂ +min{u _an ,u _bn ,u _cn } (25)

Take here where, />

Step 7, substituting each variable into the expression of the duty cycle, and then obtaining the switching sequence of all power switch tubes of the T-type three-level inverter;

Substituting the values of m and γ into equation (6), the final expression of each duty cycle can be obtained:

Among them, in one switching period, the duty cycle is distributed, and then the switching sequence of all power switch tubes of the T-type three-level inverter is obtained. When d=d _iP (i=a,b,c), it represents Only open the switching tube of the upper bridge arm of the i phase; when d=d _iN (i=a, b, c), it represents only the switching tube of the lower bridge arm of the i phase; when d=d _iO (i=a ,b,c), it means that only the two switch tubes connected to the neutral point of phase i are turned on.

A case is described below.

In order to verify the effectiveness of the proposed neutral point potential rapid balance control method based on algebraic operations for three-level inverters, a T-type three-level inverter grid-connected simulation platform was built. The system parameters are shown in Figure 9.

FIG. 1 is a schematic diagram of topology structure and control circuit hardware of an embodiment of the present invention. Including the following five parts: AC power grid 1, three-phase bridge arm 2, neutral point three-way bidirectional switch 3, DC side upper and lower capacitors 4, DC power supply 5; the midpoint of the three-phase bridge arm is connected to the power grid through a filter inductor, and the three The midpoint of the phase bridge arm is connected to the neutral point of the upper and lower capacitors on the DC side through a bidirectional switch. The hardware part of the control circuit includes a controller 7 , a drive circuit 8 , and a corresponding sampling conditioning circuit 6 . The left part of the sampling circuit 6 is responsible for sampling and conditioning the voltage and current on the grid side, and the right part of the sampling circuit 6 is responsible for sampling and conditioning the voltages across the upper and lower capacitors C ₁ and C ₂ on the DC side. The controller 7 is responsible for calculation and processing, and transmits the PWM control signals of each switch tube to the drive circuit 8, so as to drive each switch to turn it on or off.

Fig. 2 is the working principle of the topology of the embodiment of the present invention. It is stipulated that the current flowing to the grid is the positive direction of the current, the current is greater than zero, and the negative direction of the current flowing out of the grid is less than zero. In one switching cycle, the T-type three-level inverter has three operating states: Take phase A as an example, the first operating state: when d=d _aP , the upper bridge arm switch S _ap is turned on, and the bidirectional switch S _ao and the switch S _an of the lower bridge arm is turned off, at this time the output voltage u _ao =u ₁ , corresponding to the P state, when the current i _a >0, the current path at this time is the path (1) in Figure 2, when the current i When _a <0, the current path at this time is the path (2) in Figure 2; the second working state: when d=d _ao , the bidirectional switch S _ao is turned on, the upper bridge arm switch S _ap and the lower bridge arm switch S _an is turned off, at this time the output voltage u _ao = 0, corresponding to the O state, when the current _ia > 0, the current path at this time is the path (3) in Figure 2, when the current _ia < 0, this The current path is the path (4) in Figure 2; the third working state: when d=d _an , the lower bridge arm switch S _an is turned on, the bidirectional switch S _ao and the upper bridge arm switch S _ap are turned off, and the When the output voltage is u _ao =-u ₂ , corresponding to the N state, when the current i _a >0, the current path at this time is the path (5) in Figure 2, and when the current i _a <0, the current current at this time The path is path (6) in Fig. 2 .

Fig. 3 is a system structure diagram of the embodiment of the present invention. The state equation of the T-type three-level inverter is shown in formula (1). Considering the parasitic resistance r of the inductor, the new state equation can be obtained as:

After performing dq transformation on it, we can get:

The model design control scheme for the above T-type three-level inverter: Let D and Q be the outputs of the d-axis and q-axis current loops respectively. When the PI compensation network is used:

Define D and Q as:

D＝u _{d0_ref} +ωL _f i _q -u _d

Q＝u _{q0_ref} -ωL _f i _d -u _q (30)

Then the expression of the voltage reference value under dq coordinates is:

Perform dq inverse transformation on it to get the voltage reference values u _{a_ref} , u _{b_ref} , u _{c_ref} in the three-phase coordinate system, that is, the initial modulation wave. In order to improve the DC side voltage utilization rate, it is necessary to superimpose zero on the initial modulation wave sequence component u _o to get new modulation waves u ^* _{a_ref} , u ^* _{b_ref} , u ^* _{c_ref} .

in,

In order to satisfy the constraint of the duty cycle in the steady state, let the value of the degree of freedom m be:

Based on the fractional-order sliding mode control theory, the midpoint potential deviation converges in a finite time, and the value of the degree of freedom γ _i (i=a,b,c) is shown in formula (33),

The duty cycle of each phase and state is calculated from the degrees of freedom m and γ _i (i=a, b, c), as shown in formula (34).

In one switching cycle, the duty cycle is distributed, and then the switching sequences of all power switching tubes of the T-type three-level inverter are obtained.

Figure 4 and Figure 5 are the simulation waveform diagrams of the steady-state grid voltage, current, output line voltage and midpoint potential under the unit power factor and non-unity power factor conditions when the upper and lower capacitances are equal. Before t=0.09s, the grid current leads the voltage by π/6; after t=0.09s, the grid current lags the voltage by π/6. Combining Figure 4 and Figure 5, it can be seen that whether it is a unit power factor or a non-unit power factor, the grid current is subject to a given, the output line voltage presents a three-level characteristic, and the midpoint potential always fluctuates within 0.3V. This proves that the present invention can well suppress the fluctuation of the midpoint potential.

FIG. 6 and FIG. 7 are balance process diagrams of the midpoint potential when the upper and lower capacitances are equal but the initial voltages are not equal in the embodiment of the present invention. Assuming that there is a 50V deviation in the initial state of the capacitor voltage on the DC side, as shown in Figure 5, when the convergence coefficient ε=1, α=0.5, the time for the error to converge to zero is about 0.008s, as shown in Figure 6, when the convergence coefficient When ε=2, α=0.6, the time for the error to converge to zero is about 0.0035s. In summary, it can be seen that the convergence time of the system can be changed by adjusting the value of the convergence coefficient, and this convergence time is always less than the theoretical maximum value calculated by formula (16).

Fig. 8 is a balance process diagram of the midpoint potential when the upper and lower capacitances and initial voltages are not equal according to an embodiment of the present invention. When the upper and lower capacitors are not equal (C ₁ =600μF, C ₂ =400μF), there will be a relatively large voltage deviation between the two ends of the upper and lower capacitors in the initial state, and the magnitude depends on the difference in capacitance. It can be seen from Figure 8 that under this working condition, this deviation will quickly converge to zero, and the convergence time is about 0.017s, which is also within the theoretical range. In summary, the asymmetry of capacitance parameters will not affect the midpoint potential balance effect.

The above description is a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications can also be made. It should be regarded as the protection scope of the present invention.

Claims (4)

1. a neutral point potential quick balance control method of a three-level inverter, is characterized in that: comprise the following steps: Step 1, for the T-type three-level inverter, make the capacitance values of the upper and lower busbars equal, and establish the average model of the input and output of the T-type three-level inverter and the switching state of the neutral point potential; Taking the AC side inductance L as the state variable, write out the state equation of the T-type three-level inverter: Among them, u _ao , u _bo , u _co are the phase voltages with reference to the middle point o of the upper and lower busbar capacitors, u _an , u _bn , u _cn are the phase voltages with reference to the neutral point n of the three-phase AC voltage, e _a , e _b , e _c are the grid voltage, _ia , i _b , _ic are the grid side current, L is the AC side filter inductance, After taking the average of the switch state for the input and output voltages, the relationship is as follows: Among them, u ₁ and u ₂ are the voltages of two discrete capacitors on the DC side, and d _ij (i=a,b,c; j=P,N) is the duty cycle of the three-phase upper and lower bridge arm switching devices, satisfying d _iP ≥0,d _iN ≥0,0≤d _iP +d _iN ≤1(i=a,b,c), After taking the average of the switch state for the midpoint potential, the relationship is as follows: Step 2, analyze the model, introduce the degrees of freedom m and γ; Introduce degrees of freedom m and γ _i (i=a,b,c), m is used to ensure that each element meets the physical constraints, γ _i (i=a,b,c) is used to balance the midpoint potential, then each phase P The duty cycle d _ij (i=a,b,c; j=P,N) of state and N state can be written as: Substituting the above formula into formula (4), the average model of the switching state of the midpoint potential is simplified as: It can be seen from the above formula that by selecting the value of the degree of freedom γ _i (i=a,b,c), the midpoint potential is balanced, Step 3, based on the fractional-order sliding mode control theory, determine the value of the degree of freedom γ, prove that the midpoint potential can be balanced in a finite time, and give a calculation formula for the balance time; Based on the fractional-order sliding mode control theory, the value of the degree of freedom γ _i (i=a,b,c) is shown in formula (10), Substituting Equation (10) into Equation (7) can obtain the final average model of the midpoint potential switch state, For the system represented by formula (11), the Lyapunov function is selected as: Deriving it, and substituting formula (11) into: Thus there are: make: Because ε>0,0<α<1, then c>0,0<η<1, that is, there are real numbers c>0 and 0<η<1, so that V(t) is upper positive definite sum /> at /> half negative definite, The finite convergence time maximum value t _{z_max} satisfies: Where t _{z_max} represents the maximum time required for the error to converge to zero, Indicates the difference between the upper and lower capacitor voltages on the DC side in the initial state; Step 4, analyze the working conditions when the upper and lower busbar capacitances are not equal; When the capacitance of the upper and lower busbars is asymmetrical, the midpoint potential can still be balanced, Prove that "when the capacitance is asymmetric, the midpoint potential can still be balanced": When the upper and lower capacitance values on the DC bus side are not equal, that is, when C ₁ ≠ C ₂ , the average model of the switching state of the neutral point current can be expressed as: make: Substitute formula (18) into formula (17): Comparing Equation (19) and Equation (11), it can be seen that when C ₁ ≠ C ₂ , the finite time convergence is still satisfied. Therefore, when the capacitance parameters are asymmetrical, the neutral point potential can also be quickly balanced; Step 5, determine the range of the degree of freedom m, and select the value of m; m is used to ensure that each element satisfies the physical constraints in the steady state. In the steady state, that is, when the midpoint potential has been balanced, it can be known from equations (7) and (10): Then the expression of the duty cycle is simplified to: According to the requirements that the input and output terminals cannot be short-circuited or disconnected and the limitations of physical implementation, the duty cycle must meet the following constraints: Substituting formula (21) into formula (22), the value range of m can be obtained as follows: In order to reduce the number of switches, here take At this time, the T-type three-level inverter is in the linear modulation region; Step 6, determine the range of zero-sequence voltage, and select the value of zero-sequence voltage; Determine the range of zero sequence voltage: in Simplify the inequality (24): -u ₁ +max{u _an ,u _bn ,u _cn }≤u _on ≤u ₂ +min{u _an ,u _bn ,u _cn } (25) Take here where, /> Step 7, substituting each variable into the expression of the duty cycle, and then obtaining the switching sequence of all power switch tubes of the T-type three-level inverter; Substituting the values of m and γ into equation (6), the final expression of each duty cycle can be obtained: Among them, in one switching period, the duty cycle is distributed, and then the switching sequence of all power switch tubes of the T-type three-level inverter is obtained. When d=d _iP (i=a,b,c), it represents Only open the switching tube of the upper bridge arm of the i phase; when d=d _iN (i=a, b, c), it represents only the switching tube of the lower bridge arm of the i phase; when d=d _iO (i=a ,b,c), it means that only the two switch tubes connected to the neutral point of phase i are turned on. 2. The neutral point potential quick balance control method of a kind of three-level inverter according to claim 1 is characterized in that: in step 3, the concept of nonlinear system finite time stability considers the following system: Where: f: U ₀ ×R→R ⁿ is continuous at U ₀ ×R, U ₀ is an open neighborhood of the origin x=0, For the considered system (8), based on the finite-time stability theory of nonlinear control systems, the following lemmas are given: Lemma 1: Consider the nonlinear system (8), assuming that there exists a neighborhood defined at the origin The smooth function V(x) on , and there are real numbers c>0 and 0<η<1, so that V(x) in /> upper positive definite sum /> at /> semi-negative definite, then the origin of system (8) is stable in finite time, and the rest time depends on the initial value x(0)=x ₀ , and its upper bound is: Among them: x ₀ is any point in an open neighborhood of the origin, if And V(x) is radially unbounded, that is, when ||x||→+∞, V(x)→+∞, then the origin of system (8) is globally finite-time stable. 3. The neutral point potential quick balance control method of a kind of three-level inverter according to claim 2, is characterized in that: In step 3, because ε>0,0<α<1, then c>0,0<η<1, that is, there are real numbers c>0 and 0<η<1, so that V(t) is upper positive definite sum /> at /> Negative semi-definite, so the nonlinear system (11) satisfies the condition of Lemma 1. 4. The neutral point potential quick balance control method of a kind of three-level inverter according to claim 3, is characterized in that: In step 3, it can be known from Lemma 1 that the system (11) converges in a finite time, and the maximum value t _{z_max} of the finite convergence time satisfies: