CN103943136B - Memory circuit and operation method thereof - Google Patents

Abstract

The present invention discloses a memory circuit and an operation method thereof, wherein the memory circuit has a word line driver and a control circuit, wherein the word line driver receives a first voltage reference signal, a second voltage reference signal and an input signal, and the word line driver has an output terminal coupled to a word line. The control circuit inputs the input signal to the input terminal of the word line driver to be set to not select the word line. For example, during a write operation, a word line is not selected to indicate that the word line is not written, while another word line is selected to perform writing. During an operation in which one word line is not selected and another word line is selected, the word line is discharged through a p-type transistor and an n-type transistor of the word line driver.

Description

A kind of memory circuit and its operation method

technical field

The present invention relates generally to a memory integrated circuit, and more particularly to a word line driver for a memory integrated circuit.

Background technique

A memory integrated circuit accesses memory cells with a word line driven by a word line driver. With the trend towards reduced chip size and tighter power requirements, a two-transistor (2T) wordline driver becomes another option.

However, it is well known that the gate dielectric layer of the transistor of the 2T word line driver is subjected to a large electric field stress. For example, the 2T wordline driver designed in US Patent Office Publication No. 2011/0149675 requires a negative input bias to turn on the p type transistor. If a 2T wordline driver is designed without a negative input bias, the p-type transistor of the 2T wordline driver will not have long enough time to discharge the wordline to ground.

Contents of the invention

The present invention relates generally to a memory integrated circuit, and more particularly to a word line driver for a memory integrated circuit.

An aspect of the present invention provides a memory circuit. The memory circuit includes a word line driver and a control circuit. The word line driver receives a first voltage reference signal, a second voltage reference signal and an input signal. The word line driver has an output end coupled to a word line. The control circuit is configured to deselect the word line by applying the input signal to the input terminal of the word line driver. For example, during a write operation, the word line is not selected to indicate a word line not to be written, and another word line is selected to be written. As discussed below, by sharing the same voltage polarity, voltage stress on transistors (eg, p-type transistors of word line drivers) is reduced.

Another aspect of the present invention provides a method for operating a memory as described below.

A word line driver receives a first voltage reference signal, a second voltage reference signal and an input signal. The word line driver has an output end coupled to a word line. And the word line is not selected by applying the input signal to the input terminal of the word line driver. Wherein the input signal has at least one of a selected value and a non-selected value, and the selected value and the non-selected value have a same voltage polarity during a writing operation.

Another aspect of the invention provides a memory circuit. The memory circuit includes a word line driver with a first p-type transistor and a first n-type transistor and a control circuit. The first p-type transistor has a first current output terminal for receiving a first voltage reference signal. The first n-type transistor has a second current output terminal for receiving a second voltage reference signal. Wherein the first p-type transistor and the first n-type transistor are electrically coupled together as a first complementary metal oxide semiconductor (CMOS) inverter. The first complementary metal oxide semiconductor (CMOS) inverter has a first input terminal for receiving an input signal, and the first complementary metal oxide semiconductor (CMOS) inverter has a first output terminal coupled to Inline.

The wordline driver is configured to receive any one of the plurality of deselect signals sufficient to deselect the corresponding one of the wordlines. The control circuit is configured not to select the word line by applying the first voltage reference signal to the first current output terminal of the first p-type transistor, and the control circuit is configured not to select the word line by applying the A signal is input to the first input terminal of the first complementary metal-oxide-semiconductor (CMOS) inverter.

The first voltage reference signal has at least one of a first reference value and a second reference value, and the first reference value is greater than the second reference value. The input signal has at least one of a selected value and a non-selected value, and the selected value and the non-selected value have the same voltage polarity as the first reference voltage during a writing operation.

Various examples of these aspects are discussed below

According to an embodiment of the present invention, during an operation in which the word line is not selected and another word line is selected, the control circuit prevents the word line from being discharged only through a p-type transistor of the word line driver. Discharging through a p-type transistor is slower than through an n-type transistor with transistors of similar size. Word lines that are not selected allow faster discharge by preventing discharge through only the p-type transistor.

According to another embodiment of the present invention, the input signal has at least one select value (for example, used to indicate that the word line will be written) and a non-select value (for example, used to indicate that the word line will not be written) one of them. The select value and the deselect value have a same voltage polarity during a write operation.

According to another embodiment of the present invention, the first voltage reference signal is received from a general word line. The global wordline selects or deselects a plurality of wordlines located close to each other.

According to another embodiment of the present invention, the word line is not selected in response to the control circuit applying the first voltage reference signal to a first current delivery terminal of the first p-type transistor of the word line driver.

According to another embodiment of the present invention, the word line is selected in response to the control circuit applying the input signal having a selection value for turning on the first p-type transistor of the word line driver and The first n-type transistor of the word line driver. By controlling the input signal (signal PP shown in FIG. 1 ) to track the threshold voltage of the NMOS transistor, excessive leakage current is prevented when both the p-type transistor and the n-type transistor are turned on. Next, ensure that the NMOS conduction state maintains leakage at the high margin that accounts for the target specification.

According to another embodiment of the present invention, the word line is selected in response to the control circuit applying the input signal, the input signal has a selected value, the selected value is smaller than the first voltage reference signal, and larger than the first voltage reference signal Two voltage reference signals. Unlike common inverters, the input voltage is equal to the reference voltage received by either inverter.

According to another embodiment of the present invention, the word line is selected to have a writing voltage which is lower than the first voltage reference signal and higher than the second voltage reference signal. This results from the intermediate value of the input voltage of the inverter.

According to another embodiment of the present invention, the word line is charged to a write voltage in response to the word line driver receiving a first selection value of a first selection signal and a second selection value of a second selection signal. Select a value. The word line is selected to perform a program operation on one or more memory cells coupled to the at least one word line. If either or both select signals have a deselect value, the word line is not selected. The word line is not selected to perform a program operation on one or more memory cells not coupled to the word line.

According to another embodiment of the present invention, successive operations of changing a wordline voltage of the wordline are separated by a time sufficient to discharge the wordline.

During a read operation, the word line is at a stable voltage level. When both PMOS and NMOS are turned on, the voltage level of the word line is determined by the threshold voltages of the PMOS and NMOS transistors, and the two threshold voltages are different according to temperature and process. Therefore, it is difficult to define an accurate read word line voltage level. In addition, although read operations are less stressed than write operations, we can still use them for read or erase operations if necessary.

The invention discloses various embodiments of the various aspects.

Description of drawings

1 is a circuit diagram showing an example of a 2T word line driver including an inverter according to the present invention. The 2T word line driver includes an n-type transistor and a p-type transistor. During a write operation, the input terminal of the inverter receives a positive voltage. voltage to discharge the word line coupled to the inverter output.

FIG. 2 is a depth cross-sectional view showing nodes of the 2T word line driver of FIG. 1 .

Fig. 3 is the block diagram showing the array of 2T word line driver of Fig. 1, receives signal from the node of a plurality of lines in the 2T word line driver array, makes signal select specific 2T word line driver to drive specific word line in subsequent array word line.

FIG. 4 is a table showing an example of read bias configurations for nodes of the 2T word line driver of FIG. 1 .

FIG. 5 is a table showing another example of write bias configurations for nodes of the 2T word line driver of FIG. 1 .

6 is a block diagram showing an example of an array of 2T wordline drivers, the selected wordline is being charged, and the adjacent unselected wordline is capacitively coupled to the selected wordline to pass the 2T The n-type transistor or the p-type transistor of the inverter of the word line driver is discharged.

7 is a voltage versus time diagram showing three arrays of the 2T wordline driver of FIG. The selected word line discharges at different rates depending on which transistor is being discharged.

Figure 8 is a simplified diagram showing an array of 2T wordline drivers, the selected wordline is being charged, and the adjacent unselected wordline is capacitively coupled to the selected wordline, mainly through the 2T wordline The n-type transistor of the inverter of the driver discharges.

9 is a voltage versus time diagram showing three arrays of the 2T wordline driver of FIG. The selected word line is discharged primarily through the n-type transistor of the inverter of the 2T word line driver.

FIG. 10 is a voltage versus time graph showing word line address signals and word line voltages, wherein there is no delay during successive transfers of multiple word line addresses.

11 is a graph of voltage versus time for word line address signals and word line voltages, where there is a delay during successive transfers of multiple word line addresses.

FIG. 12 is a circuit diagram showing an overall word line driver.

FIG. 13 is a block diagram showing an integrated circuit including a memory array using the improved 2T word line driver described above.

FIG. 14 is a circuit diagram showing an example of a 2T word line driver including an n-type transistor and a p-type transistor that is turned on by receiving a negative gate voltage.

15 is a circuit diagram showing an example of a 2T word line driver including an n-type transistor and a depleted p-type transistor, the p-type transistor being turned on by receiving a non-positive gate voltage.

FIG. 16 is a depth cross-sectional view showing a 2T word line driver with 5 voltage nodes.

FIG. 17 is a table showing an example of the bias configuration of the five voltage nodes of the 2T word line driver of FIG. 1 .

FIG. 18 is a table showing another example of the bias configuration of the five voltage nodes of the 2T wordline driver of FIG. 2 .

FIG. 19 is a table showing yet another example of a bias configuration for a 2T word line driver with a typical negative voltage.

Fig. 20 is a block diagram showing an array of 2T word line drivers, 5 nodes in the 2T word line driver array receive signals from a plurality of word lines, so that the signal selects a specific 2T word line driver to drive a specific node in the subsequent array of word lines word line.

21 is a block diagram showing an array of 2T wordline drivers of FIG. 7 showing an example of address configuration to select a particular 2T wordline driver and not select another 2T wordline driver from the array based on two separate address lines.

Figure 22 is a block diagram showing positive and negative backup pumps driving an array of 2T word line drivers.

FIG. 23 is a block diagram showing the positive and negative backup pumps of an array of 2T wordline drivers comprising an integrated circuit for memory arrays of the improved 2T wordline drivers described above.

[Description of main component symbols]

1309: State machine circuit

1305: bus

1301: Column Decoder/Word Line Driver

1308: Bias Configuration Supply Voltage

1311: data input line

1315: data output line

1306: Sense Amplifier/Data Input Structure

1303: row decoder

1300: memory array

1350: integrated circuit

1009: State machine circuit

1005: bus

1001: Column Decoder/Word Line Driver

1008: Bias Configuration Supply Voltage

1011: Data input line

1015: Data output line

1006: Sense Amplifier/Data Input Structure

1003: row decoder

1000: memory array

1050: integrated circuit

detailed description

1 is a circuit diagram showing an example of a 2T word line driver including an inverter according to the present invention. The 2T word line driver includes an n-type transistor and a p-type transistor. During a write operation, the input terminal of the inverter receives a positive voltage. voltage to discharge the word line coupled to the inverter output.

A 2T wordline driver is coupled to a wordline of the memory array. Transistor MP0 is a p-type transistor. Transistor XM1 is an n-type transistor. Both transistors have a source and a drain as current sinks, and a gate. The gate of the p-type transistor MP0 and the gate of the n-type transistor XM1 are electrically connected to each other, and are electrically connected to the signal PP, and the signal PP selects a specific word line controlled by a specific word line driver for two address signals one of them. The drain of the p-type transistor MP0 and the drain of the n-type transistor XM1 are electrically connected to each other and electrically connected to the word line WL driven by the word line driver. The source of the p-type transistor MP0 is electrically connected to the signal GWL, which is the other of two address signals selecting a specific word line controlled by a specific word line driver. The source of the n-type transistor XM1 is electrically connected to the signal NVSSLWL. The signal NVSS is electrically connected to the p-well region (p-well) of the n-type transistor XM1. The p-well region (p-well) of the n-type transistor XM1 is formed in the n-well region (n-well) of the p-type transistor MP0.

FIG. 2 is a depth cross-sectional view showing nodes of the 2T word line driver of FIG. 1 . As shown in the figure, the p-well implant layer PWI (p-well implant) is located in the n-well diffusion layer NWD (n-well diffusion). The n-well diffusion layer NWD (n-well diffusion) is formed in the p-type substrate. The n-type transistor XM1 is formed in the p-well implant layer PWI (p-wellimplant). The p-type transistor MP0 is formed in an n-well diffusion layer NWD (n-well diffusion).

FIG. 3 is a block diagram showing an array of 2T word line drivers of FIG. 1 . Multiple lines of signals select a particular 2T wordline driver to drive a particular wordline in the subsequent array of wordlines. The preceding array of overall wordline drivers select adjacent groups of wordline drivers via signal lines GWL[63:0]. As shown, each global wordline signal (eg, GWL[0], GWL[1], . . . , GWL[63]) selects a group of 8 wordline drivers. In each group of wordline drivers, the signal PP[7:0] selects a specific wordline driver.

Therefore, a row-specific wordline driver shares the same signal GWL but has a different signal PP. A column-specific wordline driver shares the same signal PP but has a different signal GWL. The subsequent array of word lines (not shown) is controlled by the output signal (WL[511:0]) of the 2T word line driver. Another embodiment has a different number of signals and number of elements controlled by the signals.

This example address configuration selects a particular 2T wordline driver from the array and deselects another 2T wordline driver based on multiple separate address lines. Both the signal PP and the signal GWL select a specific word line corresponding to a specific word line driver.

FIG. 4 is a table showing an example of read bias configurations for nodes of the 2T word line driver of FIG. 1 .

During a read operation, the word line is not selected by applying a reference signal of 0V as the signal GWL. And by applying a high positive voltage (HV) reference signal as the signal PP, the word line is not selected. The word line is selected by applying a high positive voltage (HV) reference signal as signal GWL and by applying a negative voltage (-V) as signal PP.

FIG. 5 is a table showing another example of write bias configurations for nodes of the 2T word line driver of FIG. 1 .

During a write operation, a reference signal of 0V is applied as the signal GWL to deselect the word line. And by applying a high positive voltage (HV) reference signal as the signal PP, the word line is not selected. The word line is selected by applying a reference signal of a high positive voltage (HV) as the signal GWL, and by applying a positive voltage (+V) as the signal PP.

One configuration in which the word line driver does not select the voltage is to apply a reference signal of 0V as the signal GWL, and apply a reference signal of positive voltage (+V) as the signal PP. This voltage configuration simultaneously turns on the n-type transistor to discharge the word line to NVSS (eg, 0V), and turns on the p-type transistor to discharge the word line to GWL (eg, 0V).

In the configuration where the wordline driver does not select the voltage, a high positive voltage (HV) reference signal is applied as the signal PP to discharge the wordline through the n-type transistor.

6 is a block diagram showing an example of an array of 2T wordline drivers, the selected wordline is being charged, and the adjacent unselected wordline is capacitively coupled to the selected wordline to pass the 2T The n-type transistor or the p-type transistor of the inverter of the word line driver is discharged.

The word line drivers WLD0 to WLD7 control the corresponding word lines WL0 to WL7. Adjacent word lines are capacitively coupled together such that a change in voltage on a particular word line causes a change in voltage on an adjacent word line. Therefore, when a particular wordline is selected during an operation (eg, during a write operation), adjacent wordlines are not selected to cancel the capacitive coupling of the selected wordline.

7 is a voltage versus time diagram showing three arrays of the 2T wordline driver of FIG. The selected word line discharges at different rates depending on which transistor is being discharged.

During an operation (eg, during a write operation), word line WL3 is selected. Accordingly, the word line driver WLD3 charges the word line WL3 to a high positive voltage (HV) through the p-type transistor of the word line driver WLD3. Due to capacitive coupling, the voltages of adjacent word lines WL2 and WL4 also increase. The word line WL4 is discharged through the n-type transistor of the word line driver WLD4. The word line WL2 is discharged through the p-type transistor of the word line driver WLD2. At a given gate width, p-type transistors are inefficient compared to n-type transistors. Therefore, the instant of word line WL2 being discharged through the p-type transistor is longer than the instant of word line WL4 being discharged through the n-type transistor.

Figure 8 is a simplified diagram showing an array of 2T wordline drivers, the selected wordline is being charged, and the adjacent unselected wordline is capacitively coupled to the selected wordline, mainly through the 2T wordline The n-type transistor of the inverter of the driver discharges.

9 is a voltage versus time diagram showing three arrays of the 2T wordline driver of FIG. The selected word line is discharged primarily through the n-type transistor of the inverter of the 2T word line driver.

Similar to FIG. 6 and FIG. 7 , during an operation (eg, during a write operation), the word line WL3 is selected. However, compared with FIG. 6 and FIG. 7 , adjacent word lines WL2 and WL4 are discharged through respective n-type transistors. Therefore, the instants of the word lines WL2 and WL4 are relatively short.

FIG. 10 is a voltage versus time graph showing wordline address signals and wordline voltages, where there is no delay during successive transfers of multiple wordline addresses.

The voltage versus time graph of the word line address voltage shows that the word line address is not delayed during successive transfers. The voltage versus time graph of word line voltage shows that selected word lines are charged during an operation (eg, during a write operation) before unselected word lines have sufficient time to fully discharge.

11 is a graph of voltage versus time for word line address signals and word line voltages, where there is a delay during successive transfers of multiple word line addresses.

The voltage vs. time graph of the word line address voltage shows that the word line address has no delay during transfer. The voltage versus time graph of the word line voltage shows that the unselected word lines have sufficient time to discharge before the selected word lines are charged during an operation (eg, during a write operation). For example, the n-type transistor of the word line driver (eg, n-type transistor XM1 of FIG. 1 ) can help the p-type transistor of the word line driver (eg, p-type transistor MP0 of FIG. 1 ) to discharge unselected word lines.

FIG. 12 is a circuit diagram showing an overall word line driver, such as an example of generating the signal GWL in FIG. 2 or FIG. 3 .

The n-type transistor MN2 has a gate coupled to the signal XR; and two current supply terminals coupled to the signal INB and the node IN0.

The p-type transistor MP3 has a gate coupled to the signal XR; and two current supply terminals coupled to the power supply VDD and the node IN0.

The p-type transistor MP2 has a gate coupled to the signal IN (inversion of the signal IN); and two current supply terminals coupled to the power supply VDD and the node IN0.

The n-type transistor MN0 has a gate coupled to the signal WLVD; and two current supply terminals coupled to the node IN0 and the node GWLB.

The p-type transistor MP0 has a gate coupled to the node GWL; and two current supply terminals coupled to the power supply AVXP and the node GWLB.

The p-type transistor MP1 has a gate coupled to the node GWLB (inversion of the signal GWL); and two current supply terminals coupled to the power supply AVXP and the node GWL.

The p-type transistors MP0 and MP1 have a base coupled to the power supply AVX.

The n-type transistor MN1 has a gate coupled to the node IN0 ; and two current supply terminals coupled to the node GWL power AVXP and the power NVSSWL. The n-type transistor MN1 also has a base coupled to the power source NVSS and a well region coupled to the power source AVX.

FIG. 13 is a block diagram showing an integrated circuit including a memory array using the improved 2T word line driver described above.

Integrated circuit 1350 includes a memory array 1300 . A word line (or column) and block selection decoder 1301 is coupled and electrically transmitted to a plurality of word lines and selection lines 1302 arranged in the memory array 1300 along columns. A bit line (or row) decoder and driver 1303 are coupled and electrically transmitted to a plurality of bit lines 1304, and arranged in the memory array 1300 along a row, for reading data and writing data to the memory cells of the memory array 1300 . The address passes through bus 1305 to word line decoder and driver 1301 and bit line decoder 1303 . Block 1306 of the sense amplifier and data input structure, including current sources for read, write and erase modes, is coupled to bit line decoder 1303 via bus 1307 . Data is provided from the input/output terminals of the integrated circuit 1350 through the data input line 1311 to the block 1306 of the data input structure. Data provided from block 1306 of the sense amplifier, via data output line 1315 to an input/output of integrated circuit 1350 or to another data destination internal or external to integrated circuit 1350 . The state machine circuit 1309 controls the bias configuration supply voltage 1308 . State machine circuit 1309 applies positive voltages to word line drivers that are not selected during an operation, such as during a write operation. The state machine circuit 1309 also prevents unselected word lines from discharging only through the p-type transistors of the word line drivers.

FIG. 14 is a circuit diagram showing an example of a 2T word line driver including an n-type transistor and a p-type transistor that is turned on by receiving a negative gate voltage.

One 2T word line driver corresponds to one word line of the memory array.

Transistor MP0 is a p-type transistor. Transistor NP0 is an n-type transistor. Both transistors have a source and a drain as current sinks, and a gate. The gate of the p-type transistor MP0 and the gate of the n-type transistor NP0 are electrically connected to each other, and are electrically connected to the signal PP, and the signal PP selects a specific word line controlled by a specific word line driver for two address signals one of them. The drain of the p-type transistor MP0 and the drain of the n-type transistor NP0 are electrically connected to each other and electrically connected to the word line WL driven by the word line driver. The source of the p-type transistor MP0 is electrically connected to the signal GWL, which is the other of two address signals selecting a specific word line controlled by a specific word line driver. The source of the n-type transistor NP0 is electrically connected to the signal NVS. The signal NVS is electrically connected to the p-well region (p-well) of the n-type transistor NP0. The p-well region (p-well) of the n-type transistor NP0 is formed in the n-well region (n-well) of the p-type transistor MP0. The n-well region is electrically connected to the signal NWD.

15 is a circuit diagram showing an example of a 2T word line driver including an n-type transistor and a depleted p-type transistor, the p-type transistor being turned on by receiving a non-positive gate voltage. Figure 15 is similar to Figure 14. However, the symbol of the p-type transistor MP0 indicates a depletion type rather than an enhancement type. Therefore, the depletion p-type transistor MP0 in FIG. 15 is turned on when the gate is 0V, and the enhancement p-type transistor MP0 in FIG. 14 is turned off when the gate is 0V. More specifically, the depletion-type p-type transistor MP0 in FIG. 15 is turned on when the gate is 0V and a negative voltage, and is turned off when the gate is in a certain positive voltage range, and it is a transition between the gate is 0V and this positive voltage range Expect. The enhanced p-type transistor MP0 in FIG. 14 is turned off when the gate is 0V and a positive voltage, and turned on when the gate is in a certain negative voltage range, and there is a transition period between the gate being 0V and the negative voltage range.

FIG. 16 is a depth cross-sectional view showing a 2T word line driver with 5 voltage nodes. The p-well region implant layer PWI (p-well implant) is located in the n-well region diffusion layer NWD (n-well diffusion). The n-well diffusion layer NWD (n-welldiffusion) is formed in the p-type substrate. The n-type transistor NP0 is formed in the p-well implant layer PWI (p-wellimplant). The p-type transistor MP0 is formed in an n-well diffusion layer NWD (n-well diffusion).

FIG. 17 is a table showing an example of the bias configuration of the five voltage nodes of the 2T word line driver of FIG. 1 . Bias configurations are classified into read or write bias configurations and erase bias configurations. Bias configurations are further divided into word line selection and non-selection bias configurations.

Both the signal PP and the signal GWL are address signals, and the address signal selects or deselects a specific word line corresponding to a specific word line driver. Both the signal PP and the signal GWL must select a specific word line corresponding to a specific word line driver. Deselection occurs when neither signal PP nor signal GWL selects a particular wordline corresponding to a particular wordline driver. Therefore, two unselected bias configurations are shown in the read or write bias configurations.

In the first unselected read or write bias configuration, signal GWL is deselected. A negative signal PP turns off n-type transistor NP0 and turns on p-type transistor MP0. The p-type transistor MP0 is electrically connected to the signal GWL to the unselected word line WL.

In the first unselected read or write bias configuration, signal GWL is deselected. A positive signal AVXP turns on n-type transistor NP0 and turns off p-type transistor MP0. The n-type transistor NP0 is electrically connected to the signal NVS to the unselected word line WL.

FIG. 18 is a table showing another example of the bias configuration of the five voltage nodes of the 2T wordline driver of FIG. 15 . This table is similar to Figure 17. However, in the read or write bias configuration, the signal PP of both the select bias configuration and the first non-select read or write bias configuration is 0V instead of −2V. The table of FIG. 18 corresponds to the 2T word line driver of FIG. 15 with the depletion p-type transistor MP0 instead of the enhancement p-type transistor. Therefore, a signal PP of 0V is sufficient to turn on the p-type transistor MP0. Compared with the table in FIG. 17 , it corresponds to the 2T word line driver with enhancement p-type transistor MP0 in FIG. 14 , which requires a negative voltage, such as -2V, to turn on the p-type transistor MP0 .

FIG. 19 is a table showing yet another example of a bias configuration for a 2T word line driver with a typical negative voltage.

These signals also have node abbreviations and associated voltage ranges explained below:

AVXRD: read word line WL voltage level

AVXHV: write word line WL voltage level

AVXEV: erase word line WL voltage level

AVXNV: -1~-3V output from the negative backup pump

NV: -8～-11V for erasing

AVXP: word line WL power supply

GWL: Global Word Line Power Node

PP: Pass PMOS gate signal

NVS: negative voltage source

Fig. 20 is a block diagram showing an array of 2T word line drivers, 5 nodes in the 2T word line driver array receive signals from a plurality of word lines, so that the signal selects a specific 2T word line driver to drive a specific node in the subsequent array of word lines word line.

As shown in Figure 20, the 2T word line driver array has 64 rows, the same row shares the same signal GWL, but has different signals PP; there are 8 word line driver columns, the same column shares the same signal PP, but has different signals Signal GWL.

21 is a block diagram showing an array of 2T wordline drivers of FIG. 20 showing an example of address configuration to select a particular 2T wordline driver and not select another 2T wordline driver from the array based on two separate address lines.

Both the signal PP and the signal GWL must select a specific word line corresponding to a specific word line driver. The 2T word line driver array shown in FIG. 20 selects the word line driver in the upper left corner with signals PP[0] and GWL[0], and the word line corresponding to this word line driver. All other wordline drivers (and their corresponding wordlines) are deselected.

Figure 22 is a block diagram showing positive and negative backup pumps driving an array of 2T word line drivers.

Signal STBPMPEN enables or disables the backup pump. A positive standby pump generates signal AVXRD. A negative standby pump generates signal AVXNV. If the read mode does not have enough time to generate a negative voltage, the negative backup pump is used to turn on the p-type transistor MP0. In other words, if the p-type transistor MP0 is depleted, no negative backup pump is needed. An address signal on the address bus is decoded by LWLPPDEC, which performs local word line pre-decoding and generates signals PP[7:0].

23 is a block diagram showing the positive and negative backup pumps for an array of 2T wordline drivers comprising integrated circuits for memory arrays using the improved 2T wordline drivers described above.

FIG. 23 shows a block diagram of IC 1050 including memory array 1000 . A word line (or column) and block selection decoder 1001 is coupled and electrically transmitted to a plurality of word lines and selection lines 1002 arranged in the memory array 1000 along columns. A bit line (or row) decoder and driver 1003 are coupled and electrically transmitted to a plurality of bit lines 1004, and arranged in the memory array 1000 along a row, for reading data and writing data to the memory cells of the memory array 1000 . The address passes through bus 1005 to word line decoder and driver 1001 and bit line decoder 1003 . Block 1006 of the sense amplifier and data input structure, including current sources for read, write and erase modes, is coupled to bit line decoder 1003 via bus 1007 . Data is provided from the input/output terminals of the integrated circuit 1050 through the data input line 1011 to the block 1006 of the data input structure. Data provided from block 1006 of the sense amplifier, via data output line 1015 to an input/output of integrated circuit 1050 or to another data destination internal or external to integrated circuit 1050 . The state machine circuit and modified frequency circuit 1009 control the bias configuration supply voltage 1008 .

To sum up, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (22)

1. a kind of memory circuitry, including：

One word line driver, to receive a first voltage reference signal, a second voltage reference signal and an input signal, The word line driver has an output end, and the output end is coupled to one first wordline；And

One control circuit, by applying the input signal to the input of the word line driver be arranged to not select this first Wordline；

Wherein, first wordline be not selected and another wordline it is selected one operation during, first wordline passes through simultaneously One first p-type transistor of the word line driver and the electric discharge of one first n-type transistor.

2. memory circuitry according to claim 1, wherein being not selected in first wordline and another wordline is selected During the operation selected, the control circuit prevents first wordline from only being discharged by a p-type transistor of the word line driver.

3. memory circuitry according to claim 1, the wherein input signal are not selected with an at least selective value and one Value one of them, the selective value and this not selective value during the operation have an identical polarity of voltage.

4. memory circuitry according to claim 1, wherein the first voltage reference signal are received from an overall wordline, The overall wordline selection or not position a plurality of wordline close to each other.

It is to react on the control circuit 5. memory circuitry according to claim 1, wherein first wordline are not selected Apply the first voltage reference signal to one first electric current delivery end of first p-type transistor of the word line driver.

It is to react on the control circuit to apply 6. memory circuitry according to claim 1, wherein first wordline are chosen Plus the input signal, the input signal have a selective value to turn on the word line driver first p-type transistor and First n-type transistor of the word line driver.

It is to react on the control circuit to apply 7. memory circuitry according to claim 1, wherein first wordline are chosen Plus the input signal, the input signal is with a selective value, and the selective value is less than one first ginseng of the first voltage reference signal Value is examined, and more than one second reference value of the second voltage reference signal.

8. memory circuitry according to claim 1, wherein first wordline are selected to have a write-in voltage, this is write Enter one first reference value that voltage is less than the first voltage reference signal, and more than one the 3rd ginseng of the second voltage reference signal Examine value.

It is to react on 9. memory circuitry according to claim 1, wherein first wordline are charged to a write-in voltage The word line driver receives a first choice value of a first choice signal and one second selective value of one second selection signal.

10. memory circuitry according to claim 1, wherein changing the continuous operation of a word line voltage of first wordline Separated by time enough with first wordline of discharging.

11. a kind of method for operating memory, including：

A first voltage reference signal, a second voltage reference signal and an input signal are received using a word line driver, Wherein the word line driver has an output end, and the output end is coupled to one first wordline；And

By applying the input signal to the input of the word line driver not select first wordline, wherein, this first Wordline is not selected and during the selected operation of another wordline, first wordline passes through the one the of the word line driver simultaneously One p-type transistor and the electric discharge of one first n-type transistor.

12. method according to claim 11, wherein being not selected in first wordline and another wordline is selected During the operation, control circuit prevents first wordline from only being discharged by a p-type transistor of the word line driver.

13. method according to claim 11, the wherein input signal have an at least selective value and one not selective value its One of, the selective value and this not selective value during the operation have an identical polarity of voltage.

14. method according to claim 11, wherein the first voltage reference signal are received from an overall wordline, this is total Body wordline selects or does not select position a plurality of wordline close to each other.

It is to react on control circuit application 15. method according to claim 11, wherein first wordline are not selected The first voltage reference signal to first p-type transistor of the word line driver one first electric current delivery end.

It is to react on control circuit application to be somebody's turn to do 16. method according to claim 11, wherein first wordline are chosen Input signal, the input signal has first p-type transistor and the word of a selective value to turn on the word line driver First n-type transistor of line drive.

It is to react on control circuit application to be somebody's turn to do 17. method according to claim 11, wherein first wordline are chosen Input signal, the input signal has a selective value, and the selective value is less than one first reference value of the first voltage reference signal, And more than one the 3rd reference value of the second voltage reference signal.

18. method according to claim 11, wherein first wordline are selected to have a write-in voltage, write-in electricity Pressure is less than one first reference value of the first voltage reference signal, and more than one the 3rd reference of the second voltage reference signal Value.

It is to react on the word 19. method according to claim 11, wherein first wordline are charged to a write-in voltage Line drive receives a first choice value of a first choice signal and one second selective value of one second selection signal.

20. method according to claim 11, wherein changing the continuous operation of a word line voltage of first wordline by foot The enough time is separated with first wordline of discharging.

21. a kind of memory circuitry, including：

One word line driver, including：

One first p-type transistor, with one first current output terminal to receive a first voltage reference signal；And

One first n-type transistor, with one second current output terminal to receive a second voltage reference signal；

Wherein first p-type transistor and first n-type transistor is electrically coupled together as one first complementary metal oxide Thing semiconductor (CMOS) inverter, the first CMOS (CMOS) inverter has a first input end To receive an input signal, the first CMOS (CMOS) inverter has one first output end coupling It is connected to one first wordline；And

One control circuit, by apply the first voltage reference signal to first p-type transistor the first current output terminal with It is arranged to not select first wordline, wherein the first voltage reference signal has at least one first reference value and one second ginseng One of value is examined, first reference value is more than second reference value；And

The control circuit is arranged to not select first wordline, by applying the input signal to the first complementary metal oxygen The first input end of compound semiconductor (CMOS) inverter；

Wherein, first wordline be not selected and another wordline it is selected one operation during, first wordline passes through simultaneously One first p-type transistor of the word line driver and the electric discharge of one first n-type transistor.

22. memory circuitry according to claim 21, the wherein input signal are not selected with an at least selective value and one Select value one of them, the selective value and this not selective value during the operation have and first with reference to electricity value the identical electricity of identical one Press polarity.