CN103853226B - Fixed current generating circuit and fixed current generating method - Google Patents

Abstract

The invention discloses a fixed current generating circuit and a related fixed current generating method, which are applied to a chip, wherein the chip comprises a first current generating circuit and a second current generating circuit, the second current generating circuit comprises a transistor and an adjustable resistor, and the fixed current generating method comprises the following steps: connecting an external resistor to the first current generating circuit so that the first current generating circuit generates a first current by using the external resistor; generating a second current using the second current generating circuit; the resistance value of the adjustable resistor is adjusted according to the first current and the second current, so that the second current is substantially equal to the first current and is used as a fixed current used in the chip.

Description

Fixed current generating circuit and fixed current generating method

technical field

The present invention relates to a fixed current generating circuit, in particular to a fixed current generating circuit and a related fixed current generating method which uses a calibrated resistance inside a chip to generate a fixed current.

Background technique

Generally, a precision current source is required inside the chip to provide a fixed current for the components to use. However, because the resistance value inside the chip may not be very accurate, the way to realize the precision current source is usually to use an energy band Gap voltage (bandgapvoltage) plus an external resistor to generate. As mentioned above, since an additional external resistor is required, additional cost will be added on the chip-related design.

Contents of the invention

Therefore, one of the objects of the present invention is to provide a fixed current generating circuit and a related fixed current generating method, which can use the calibrated resistance inside the chip to generate a fixed current without requiring an additional correction circuit to solve the above problems question.

According to an embodiment of the present invention, a fixed current generating circuit disposed in a chip includes a first current generating circuit, a second current generating circuit, a current mirror, a switch module and a correction circuit, wherein the first The current generating circuit includes a first transistor, wherein the first transistor is coupled to a contact of the chip, and during a chip testing stage, the contact is used to connect an external resistor for the first current generating circuit to generate a first transistor. A current; the second current generating circuit includes a second transistor and an adjustable resistance, and is used to generate a second current; the switch module is coupled to the first current generating circuit, the second current generating circuit and the Between the current mirrors, and for selectively connecting the first current generating circuit and the second current generating circuit to the current mirror, so that the current mirror replicates the first current or the second current; the correction The circuit is coupled to the current mirror, and is used for adjusting the resistance value of the adjustable resistor according to the first current and the second current copied by the current mirror, so that the second current is substantially equal to the first current , and the second current is used as a fixed current in the chip.

According to another embodiment of the present invention, a fixed current generating method applied in a chip is disclosed, wherein the chip includes a first current generating circuit and a second current generating circuit, and the second current generating circuit includes a transistor and An adjustable resistor, the fixed current generating method includes: connecting an external resistor to the first current generating circuit, so that the first current generating circuit uses the external resistor to generate a first current; using the second current generating circuit to generate a second current; adjust the resistance value of the adjustable resistor according to the first current and the second current, so that the second current is substantially equal to the first current, and the second current serves as the A fixed current used in the chip.

Description of drawings

FIG. 1 is a schematic diagram of a constant current generating circuit according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a fixed current generating circuit generating a first current and a corresponding first digital code during a chip testing phase.

FIG. 3 is a schematic diagram of a second current and a corresponding second digital code generated by the fixed current generating circuit during a chip testing phase.

FIG. 4 is a flowchart of a method for generating a constant current according to an embodiment of the invention.

Wherein, the reference signs are explained as follows:

100 fixed current generating circuit

102 operational amplifier

110 first current generating circuit

120 second current generating circuit

130 current mirror

140 correction circuit

142 sending circuit

144 receiving circuit

146 digital signal processor

148 electronic fuse

M1, M2 transistors

Rext external resistor

Rc adjustable resistance

SW1_1, SW1_2, SW2_1, SW2_2 switches

N1, N2 endpoints

400~406 steps

detailed description

Certain terms are used in the specification and subsequent patent claims to refer to particular elements. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. The scope of this specification and subsequent patent claims does not use the difference in name as the way to distinguish components, but the difference in function of the components as the criterion for distinguishing. The "comprising" mentioned throughout the specification and subsequent claims is an open term, so it should be interpreted as "including but not limited to". In addition, the term "coupled" here includes any direct and indirect electrical connection means. Therefore, if it is described in the text that a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device. The second device, or indirectly electrically connected to the second device through other devices or connection means.

Please refer to FIG. 1 , which is a schematic diagram of a constant current generating circuit 100 according to an embodiment of the present invention. As shown in Figure 1, the fixed current generating circuit 100 is used to generate a fixed current Ic, and includes an operational amplifier 102, a first current generating circuit 110, a second current generating circuit 120, a current mirror 130, and a switch module (In this embodiment, the switch module includes switches SW1_1, SW1_2, SW1_3, SW1_4) and a calibration circuit 140, wherein the first current generating circuit 110 includes a transistor M1, and the second current generating circuit 120 includes a transistor M2 and a The adjustable resistor Rc, the calibration circuit 140 includes a sending circuit 142 , a receiving circuit 144 and a digital signal processor 146 , wherein the digital signal processor 146 includes a plurality of electrical fuses (Electrical fuses, Efuses) 148 .

In this embodiment, the fixed current generating circuit 100 is located in a chip, and the contact N1 shown in FIG. The first current generating circuit 110 generates a first current; in addition, the contact N2 shown in FIG. 1 is a signal output contact of the chip, which is used to transmit the signal output by the sending circuit 142 to the outside of the chip through the contact N2.

In an embodiment of the present invention, the chip used by the fixed current generating circuit 100 is a network chip, and the sending circuit 142 and the receiving circuit 144 are themselves an Analog Front End (AFE) circuit of the chip. In addition, the sending circuit 142 itself can use a digital-to-analog converter (Digital-to-Analog Converter, DAC) for actual use, and is used to receive network data from the digital signal processor 146, and process the received network data It is transmitted to a transmission line outside the chip through the contact N2; in addition, the receiving circuit 144 itself can use an analog-to-digital converter (Analog-to-Digital Converter, ADC) for practical use, and is used to receive network data from the contact N2, and convert the The received network data is converted from analog to digital and sent to the digital signal processor 146 for subsequent processing.

In a chip testing stage, please refer to FIG. 2 , firstly, the fixed current generating circuit 100 is first connected to the external resistor Rext through the contact N1, the switches SW1_1 and SW1_2 are turned on under the control of the control signal V _C1 , and the switches SW2_1 and SW2_2 Then it is in a non-conducting state under the control of the control signal V _C2 , wherein the control signals V _C1 and V _C2 can be generated by the digital signal processor 146 or other sources. At this time, since the anode of the operational amplifier 102 is connected to a bandgap voltage Vbg, the first current generating circuit 110 will generate a first current I ₁ with a current value (Vbg/Rext), and the current mirror 130 replicates the first current _I1 to generate a replicated current IBX. Afterwards, the transmitting circuit 142 converts the replica current IBX into a first voltage value Vox according to a reference data Di given by the digital signal processor 146, wherein the reference data Di is used to determine when the transmitting circuit 142 converts the replica current IBX to The ratio of the first voltage value Vox; afterward, the receiving circuit 144 converts the first voltage value Vox into a first digital code Dox, and the first digital code Dox is then sent to the digital signal processor 146 and stored therein.

Next, after the first digital code _Dox is stored in the digital signal processor 146, please refer to FIG. The control of _C2 is turned on. At this time, since the anode of the operational amplifier 102 is connected to a bandgap voltage Vbg, the second current generating circuit 120 will generate a second current I ₂ with a current value (Vbg/Rc), and the current mirror 130 replicates the second current _I2 to generate a replicated current IBC. Afterwards, the sending circuit 142 converts the replica current IBC into a second voltage value Voc according to the reference data Di given by the digital signal processor 146, and the receiving circuit 144 then converts the second voltage value Voc into a second digital code Doc , and the second digital code Doc is then sent to the digital signal processor 146 and stored therein.

Next, since the first digital code Dox and the second digital code Doc stored in the digital signal processor 146 are used to represent the magnitudes of the first current _I1 and the second current _I2 respectively, the digital signal processor 146 can be based on The first digital code Dox and the second digital code Doc generate a correction code Dcc to adjust the resistance value of the adjustable resistor Rc, so that the current generated by the second current generating circuit 120 can be as close as possible to the first current generating circuit 110 the resulting current. For example, the digital signal processor 146 can determine the correction code Dcc from a comparison table according to the code value or difference value between the first digital code Dox and the second digital code Doc to adjust the resistance value of the adjustable resistor Rc or the digital signal processor 146 can continuously generate different correction codes Dcc to adjust the resistance value of the adjustable resistor Rc, so that the current I ₂ generated by the second current generating circuit 120 is the same as the corresponding second digital code Doc The change is continued until the second digital code Doc is very close to the first digital code Dox.

Through the above adjustment, the resistance value of the adjustable resistor Rc will be very close to the resistance value of the external resistor Rext, therefore, the current _I2 generated by the second current generating circuit 120 will also be very close to the current generated by the first current generating circuit 110 I ₁ , at this time, the digital signal processor 146 will use the electronic fuse 148 to record the correction code Dcc at this time. Therefore, in the subsequent use of the chip, since the correction code Dcc has been fixed by the electronic fuse 148, the adjustable resistance The resistance value of Rc is also fixed, and the chip can use the second current generating circuit 120 to generate a required fixed current Ic. Since there is no need to use an external resistor for subsequent use, subsequent manufacturing costs can be reduced.

In addition, since the correction circuit 140 in the fixed current generating circuit 100 is implemented by the sending circuit 142 and the receiving circuit 144 of the chip itself, there is no need to add an additional correction circuit in the chip, which can save the cost of chip design and production. .

However, it should be noted that although in the embodiment shown in FIG. 2 , the calibration circuit 140 is implemented by the sending circuit 142 and the receiving circuit 144 of the chip itself, the present invention is not limited thereto. In other embodiments of the present invention, the correction circuit 140 can also be an independent correction circuit in the chip, and can have other types of designs instead of using the sending circuit 142 and receiving circuit 144 of the chip itself. These design changes All should belong to the category of the present invention.

Please refer to FIG. 4. FIG. 4 is a flow chart of a method for generating a fixed current according to an embodiment of the present invention. Referring to FIGS.

Step 400: Provide a chip, wherein the chip includes a first current generating circuit and a second

A current generating circuit, the second current generating circuit includes a transistor and an adjustable resistance;

Step 402: Connect an external resistor to the first current generating circuit, so that the first current generating circuit uses the external resistor to generate a first current;

Step 404: using the second current generating circuit to generate a second current;

Step 406: Adjust the resistance value of the adjustable resistor according to the first current and the second current, so that the second current is substantially equal to the first current, and the second current is used in the chip a fixed current.

To briefly summarize the present invention, in the fixed current generating circuit and related fixed current generating method of the present invention, the resistance value of an adjustable resistor inside the chip is calibrated to be close to the resistance value of an external resistor, so that the chip can use the internal correction A reliable constant current is generated by a subsequent resistor. Since no external resistor is required, subsequent manufacturing costs can be reduced indeed. In addition, the correction circuit in the fixed current generating circuit of the present invention can be implemented by using the sending circuit and receiving circuit of the chip itself, so there is no need to design an additional correction circuit to further save the cost of chip design and manufacturing.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the patent claims of the present invention shall fall within the scope of the present invention.

Claims (11)

1. A fixed current generating circuit, which is arranged in a chip and includes: A first current generating circuit, comprising a first transistor, wherein the first transistor is coupled to a contact of the chip, and during a chip testing stage, the contact is used to connect an external resistor for the first current The generating circuit generates a first current; A second current generating circuit, including a second transistor and an adjustable resistor, used to generate a second current; a current mirror; a switch module, coupled between the first current generating circuit, the second current generating circuit and the current mirror, for selectively connecting the first current generating circuit and the second current generating circuit to the current mirror, so that the current mirror replicates either the first current or the second current; and a correction circuit, coupled to the current mirror, for adjusting the resistance value of the adjustable resistor according to the first current and the second current copied by the current mirror, so that the second current is as close as possible to the the first current, and the second current is used as a fixed current in the chip; Among them, the correction circuit includes: a sending circuit, used to receive the first current copied by the current mirror to generate a first voltage value, and receive the second current copied by the current mirror to generate a second voltage value; a receiving circuit, coupled to the transmitting circuit, for receiving the first voltage value to generate a first digital code, and receiving the second voltage value to generate a second digital code; and A digital signal processor, coupled to the receiving circuit, includes a plurality of electronic fuses, and the digital signal processor controls the plurality of electronic fuses to generate a correction code according to the first digital code and the second digital code, And the correction code is used to adjust the resistance value of the adjustable resistor. 2. The fixed current generating circuit as claimed in claim 1, wherein the calibration circuit comprises an analog front-end circuit of the chip. 3. The fixed current generating circuit as claimed in claim 1, wherein during the chip testing stage, the switch module connects the first current generating circuit to the current mirror, and makes the second current generating circuit not connected to the current mirror. a current mirror, and the correction circuit receives the first current copied by the current mirror; and the switch module further connects the second current generating circuit to the current mirror, and makes the first current generating circuit not connected to the current mirror, and the correction circuit receives the second current copied by the current mirror; and the correction circuit adjusts the resistance value of the adjustable resistor according to the first current and the second current copied by the current mirror, so that The second current is as close as possible to the first current. 4. The fixed current generating circuit as claimed in claim 1, wherein the chip is a network chip, and the sending circuit and the receiving circuit are circuits for sending and receiving network-related signals in the network chip, respectively. 5. The fixed current generating circuit as claimed in claim 1, wherein the digital signal processor determines a correction code from a comparison table according to the difference between the first digital code and the second digital code, so as to adjust the possible Adjust the resistance value of the resistor. 6. The fixed current generating circuit as claimed in claim 4, wherein the sending circuit is a digital-to-analog converter for receiving network data from the digital signal processor. 7. The fixed current generating circuit as claimed in claim 1, further comprising an operational amplifier, the positive pole of the operational amplifier is connected to a bandgap voltage, and the negative pole of the operational amplifier is coupled to the first current generating circuit through the switch module , the second current generating circuit. 8. The fixed current generating circuit as claimed in claim 7, the switch module comprising: a first switch, coupled between the first current generating circuit and the current mirror; a second switch, coupled between the second current generating circuit and the current mirror; a third switch, coupled between the negative pole of the operational amplifier and the first current generating circuit; The fourth switch is coupled between the negative pole of the operational amplifier and the second current generating circuit. 9. A method for generating a fixed current, applied in a chip, wherein the chip includes a first current generating circuit and a second current generating circuit, the second current generating circuit includes a transistor and an adjustable resistor, the fixed Current generation methods include: connecting an external resistance to the first current generating circuit, so that the first current generating circuit uses the external resistance to generate a first current; using the second current generating circuit to generate a second current; Adjusting the resistance value of the adjustable resistor according to the first current and the second current, so that the second current is as close as possible to the first current, and the second current is used as a fixed current in the chip current; Wherein, the step of adjusting the resistance value of the adjustable resistor according to the first current and the second current so that the second current is as close as possible to the first current includes: receiving the first current to generate a first voltage value; receiving the first voltage value to generate a first digital code; receiving the second current to generate a second voltage value; receiving the second voltage value to generate a second digital code; and Adjusting the resistance value of the adjustable resistor according to the first digital code and the second digital code includes: controlling a plurality of electronic fuses in the chip according to the first digital code and the second digital code to generate a a correction code, and the correction code is used to adjust the resistance value of the adjustable resistor. 10. The fixed current generating method as claimed in claim 9, wherein the step of generating the first voltage value, the first digital code, the second voltage value and the second digital code comprises: An analog front-end circuit of the chip is used to generate the first voltage value, the first digital code, the second voltage value and the second digital code. 11. The fixed current generating method as claimed in claim 10, wherein the step of generating the first voltage value, the first digital code, the second voltage value and the second digital code comprises: using a transmitting circuit of the chip to receive the first current to generate the first voltage value, and receive the second current to generate the second voltage value; using a receiving circuit of the chip to receive the first voltage value to generate the first digital code, and receive the second voltage value to generate the second digital code; Wherein the chip is a network chip, and the sending circuit and the receiving circuit are circuits for sending and receiving network related signals in the network chip respectively.