CN103840004A - Fin type field effect transistor with SiGeSn source drain and forming method thereof - Google Patents

Abstract

The invention provides a fin field effect transistor with SiGeSn source and drain and its forming method. Wherein the method comprises the following steps: providing a substrate; forming a Ge fin structure on the substrate; forming a gate stack or dummy gate on the Ge fin structure; forming a source region and a drain region on both sides of the gate stack or dummy gate The Ge fin-shaped structure is exposed at the opening position; atoms, molecules, ions or plasma containing both Si and Sn elements are implanted into the Ge fin-shaped structure to form a SiGeSn layer at the opening position. The fin field effect transistor forming method of the present invention can form a FinFET with a SiGeSn source and drain, and the SiGeSn source and drain have a thinner thickness and better crystal quality, so the transistor has good electrical performance, and the method is simple and easy to implement, low cost low pros.

Description

Fin field effect transistor with SiGeSn source and drain and method of forming same

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a fin field effect transistor with SiGeSn source and drain and a forming method thereof.

Background technique

Metal-oxide-semiconductor field-effect transistors (MOSFETs) have served the integrated circuit industry for over forty years. People have invented a variety of ingenious techniques to make the feature size shrink continuously, but it has not changed its basic structure. However, the integrated circuit design window, including performance, dynamic power consumption, static power consumption, and device tolerances, has shrunk to the point where a new transistor structure has to be invented. As the gate length continues to shrink, the transfer characteristics (I _ds -V _gs ) of MOSFETs degrade, mainly in two aspects. One is that the sub-threshold slope becomes larger and the threshold voltage decreases, that is, the MOS device cannot be turned off well by reducing the gate electrode voltage V _gs . On the other hand, both the subthreshold slope and the threshold voltage are particularly sensitive to changes in gate length, that is, the process tolerance of MOS devices becomes very poor, and this phenomenon is called the short channel effect.

On the one hand, in order to effectively suppress the short channel effect, the researchers proposed a device structure that enables the semiconductor channel to exist only very close to the gate, eliminating all leakage channels away from the gate. Since the semiconductor channel is thin enough at this time, its shape looks like a fish's fin (Fin), so researchers vividly call it a fin field effect transistor (FinFET). FinFET devices can greatly enhance the control ability of the gate to the channel, effectively suppress the short channel effect, and make it have the advantages of large drive current, small off-state current, high device switching ratio, low cost, and high transistor density. Fin materials can be processed using cheap bulk Si substrates or silicon-on-insulator substrates (SOI).

On the other hand, with the continuous shrinking of the device size, the low mobility of Si material has become the main factor restricting the device performance. In order to continuously improve the performance of devices, channel materials with higher mobility must be used. The main technical solutions currently being studied are: using Ge or SiGe materials as channel materials for PMOSFET devices, and III-V compound semiconductor materials as channel materials for NMOSFET devices. Ge has four times the hole mobility of Si. With the deepening of research, technical difficulties in Ge and SiGe trench MOSFETs have been overcome one by one. In Ge or SiGe MOSFET devices, in order to introduce uniaxial compressive strain in the Ge or SiGe channel, the strained Ge _1-x Sn _x (GeSn) alloy can be filled in the source and drain regions, so that the strained GeSn through the source and drain can be in the channel The introduction of uniaxial compressive strain into the channel greatly improves the performance of the Ge or SiGe channel, especially when the channel length is at the nanometer scale. The Ge-compatible GeSn alloy is a group IV semiconductor material and has good compatibility with the complementary metal-oxide-semiconductor (CMOS) process of silicon. However, it is very difficult to directly grow high-quality and high-Sn-content GeSn alloys. First, the equilibrium solid solubility of Sn in Ge is less than 1% (about 0.3%); second, the surface energy of Sn is smaller than that of Ge, and surface segregation is very easy to occur; third, Ge and α-Sn have a large crystal frame mismatch (14.7%). In order to suppress the surface segregation of Sn and increase the content of Sn, a certain amount of Si can be doped during material growth to form a SiGeSn layer. The lattice constant of Si is smaller than that of Ge, and the lattice constant of Sn is larger than that of Ge. By doping Si in GeSn alloy, the stability of GeSn alloy can be improved.

When growing SiGeSn materials, the commonly used method is molecular beam epitaxy (MBE). Among them, the process of growing SiGeSn material in the existing MBE process is: first epitaxially grow a layer of SiGe buffer layer on the substrate, and then epitaxially grow SiGeSn thin film. This method can obtain SiGeSn thin films with better crystal quality, but the equipment is expensive, the growth process is time-consuming, and the cost is high, which will be limited in large-scale production. Some people also use chemical vapor deposition (CVD) to grow SiGeSn films, but the SiGeSn films produced are of poor quality, poor thermal stability, Sn is easy to segregate, and is not suitable for semiconductor devices. Moreover, in the FinFET structure, it is generally necessary to use the method of selective area formation to form SiGeSn in the source and drain regions. In theory, chemical vapor deposition can be used to selectively grow SiGeSn thin films. However, the current method is not suitable for the non-selective growth of SiGeSn alloys. Poor stability, Sn is easy to segregate, its selective growth process is immature, and the cost is high.

Contents of the invention

The present invention aims at at least to a certain extent to solve the above-mentioned problems of difficulty in forming SiGeSn films with good quality and high production costs in the source and drain of FinFETs. Therefore, the purpose of the present invention is to provide a simple and low-cost fin field effect transistor with SiGeSn source and drain and its forming method.

To achieve the above object, the method for forming a fin field effect transistor with SiGeSn source and drain according to an embodiment of the present invention may include the following steps: providing a substrate; forming a Ge fin structure on the substrate; A gate stack or a dummy gate is formed on the fin structure; openings for a source region and a drain region are formed on both sides of the gate stack or dummy gate, and the Ge fin structure is exposed at the position of the opening; The structure implants atoms, molecules, ions or plasma containing both Si and Sn elements to form a SiGeSn layer at the position of the opening.

The method according to the embodiment of the present invention can form a FinFET with SiGeSn source and drain, the thickness of the SiGeSn source and drain is relatively thin, and the crystal quality is good, so the transistor has good electrical performance, and the method has the advantages of simplicity and low cost .

Optionally, the method for forming a fin field effect transistor with a SiGeSn source and drain according to an embodiment of the present invention also has the following technical features:

In an example of the present invention, the method further includes: before forming the openings of the source region and the drain region, forming gate spacers on both sides of the gate stack or the dummy gate.

In an example of the present invention, it further includes: after forming the SiGeSn layer, removing the dummy gate, and forming a gate stack in the dummy gate region.

In an example of the present invention, the substrate is a Si substrate, a Ge substrate, a Si-on-insulator substrate, a Ge-on-insulator substrate, or a Si substrate with a Ge surface.

In one example of the present invention, the Ge fin structure is formed on the substrate by a selective epitaxial process.

In an example of the present invention, the Ge fin structure is formed on the substrate by photolithography and etching process, wherein the surface layer of the substrate is made of Ge material.

In an example of the present invention, the substrate whose surface layer is made of Ge material is a Ge substrate, a Ge-on-insulator substrate, or a Si substrate with a Ge surface.

In an example of the present invention, the implantation method includes ion implantation.

In an example of the present invention, the ion implantation includes plasma source ion implantation and plasma immersion ion implantation.

In an example of the present invention, the injection method includes magnetron sputtering.

In an example of the present invention, during the implantation process using the magnetron sputtering, a negative bias voltage is applied to the substrate.

In an example of the present invention, it further includes removing the Si—Sn thin film formed on the SiGeSn layer by the magnetron sputtering.

In one example of the present invention, the Si-Sn film is removed by cleaning with a solution having a high etching selectivity to SiGeSn and Si-Sn.

In an example of the present invention, the substrate is heated during the implantation, and the heating temperature is 100-600°C.

In an example of the present invention, it further includes, after the implantation, annealing the SiGeSn layer, and the annealing temperature is 100-600°C.

In an example of the present invention, the SiGeSn layer is a strained SiGeSn layer.

In an example of the present invention, the strained SiGeSn layer has a thickness of 0.5-100 nm.

In an example of the present invention, the atomic percentage of Sn in the strained SiGeSn layer is less than 20%.

To achieve the above object, a fin field effect transistor with a SiGeSn source and drain according to an embodiment of the present invention includes: a substrate; a Ge fin-shaped channel region formed on the substrate; a gate stack structure above the Ge fin-shaped channel region; and a SiGeSn source and drain formed on both sides of the Ge fin-shaped channel region.

The fin field effect transistor with SiGeSn source and drain according to the embodiment of the present invention has the advantage of good electrical performance.

Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and comprehensible from the description of the embodiments in conjunction with the following drawings, wherein:

1 is a flowchart of a method for forming a fin field effect transistor with SiGeSn source and drain according to the first embodiment of the present invention;

2 to 5b are schematic diagrams of the specific process of the forming method shown in FIG. 1;

6 is a flowchart of a method for forming a fin field effect transistor with SiGeSn source and drain according to the second embodiment of the present invention;

7 to 11b are schematic diagrams of the specific process of the forming method shown in FIG. 6 .

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

In the present invention, unless otherwise clearly specified and limited, a first feature being "on" or "under" a second feature may include direct contact between the first and second features, and may also include the first and second features Not in direct contact but through another characteristic contact between them. Moreover, "above", "above" and "above" the first feature on the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature. "Below", "beneath" and "under" the first feature to the second feature include that the first feature is directly below and obliquely below the second feature, or simply means that the first feature has a lower level than the second feature.

According to the first embodiment of the present invention, the method for forming a fin field effect transistor with a SiGeSn source and drain may adopt a gate-first process, as shown in FIG. 1 , and may include the following steps:

S11. Providing a substrate.

Specifically, the substrate may be a Si substrate, a Ge substrate, a Si-on-insulator substrate, a Ge-on-insulator substrate, a Si substrate with a Ge surface, and the like.

S12. Forming a Ge fin structure on the substrate.

Specifically, a Ge fin structure 10 is formed on a substrate 00 , referring to FIG. 2 .

In one embodiment of the present invention, the Ge fin structure 10 may be formed on the substrate 00 by a selective epitaxial process. At this time, the Ge fin-shaped structure 10 is not originally possessed by the substrate 00, but is epitaxially produced. Therefore, the selection range of the substrate 00 is wide, and can be Si substrate, Ge substrate, Si-on-insulator substrate, and Si-on-insulator substrate. Ge substrate, Si substrate with Ge surface, etc.

In another embodiment of the present invention, the Ge fin structure 10 may be formed on the substrate 00 by photolithography and etching processes, wherein the substrate 00 is a substrate whose surface layer is made of Ge material. At this time, the Ge fin structure 10 is what the substrate 00 originally had, rather than being formed later, so the selection range of the substrate 00 is relatively narrow, and it can be a Ge substrate, a Ge-on-insulator substrate, or a Si substrate with a Ge surface. Substrate etc.

S13. Forming a gate stack on the Ge fin structure.

Specifically, a gate dielectric material and a gate material are sequentially deposited on the Ge fin structure 10, and a patterned gate stack 20 including a gate dielectric layer 20a and a gate layer 20b is formed by photolithography and etching processes. Referring to FIG. 3a and FIG. 3b, FIG. 3a is a schematic perspective view, and FIG. 3b is a cross-sectional view along the direction of the channel.

S14. Forming openings for the source region and the drain region on both sides of the gate stack, exposing the Ge fin structure at the opening position.

Preferably, gate spacers 30 may be further formed on both sides of the gate stack 20 to define openings of the source region and the drain region. The gate spacer 30 can reduce device leakage. The specific process is as follows: after the above steps, the dielectric material required for the gate spacer is first deposited, and then through a suitable dry etching process, the gate spacer 30 is formed on both sides of the patterned gate stack, and at the same time, the source region and the drain An opening is formed above the region, and the Ge fin structure 10 is exposed at the position of the opening. Referring to FIG. 4a and FIG. 4b , wherein FIG. 4a is a schematic perspective view, and FIG. 4b is a cross-sectional view along the channel direction.

S15. Implanting atoms, molecules, ions or plasma containing both Si and Sn elements into the Ge fin structure to form a SiGeSn layer at the opening position.

Specifically, atoms, molecules, ions or plasma containing both Si and Sn elements can be implanted into the Ge fin structure 10 to transform the surface layer or all of the Ge fin structure 10 exposed at the opening position into the target SiGeSn layer 40 . The SiGeSn layer 40 serves as the source and drain of the FinFET. Referring to FIG. 5a and FIG. 5b, FIG. 5a is a perspective view, and FIG. 5b is a cross-sectional view along the direction of the channel.

According to the method for forming a FinFET according to the first embodiment of the present invention, a fin-shaped field effect transistor with SiGeSn as the source and drain regions can be obtained, and the SiGeSn layer in the source and drain regions is thinner and of better quality, and the method is simple and easy to implement, The advantage of low cost.

The method for forming a FinFET with SiGeSn source and drain according to the second embodiment of the present invention may adopt a gate-last process, as shown in FIG. 6 , and may include the following steps:

S21. Providing a substrate.

Specifically, the substrate may be a Si substrate, a Ge substrate, a Si-on-insulator substrate, a Ge-on-insulator substrate, a Si substrate with a Ge surface, and the like.

S22. Forming a Ge fin structure on the substrate.

Specifically, a Ge fin structure 10 is formed on the substrate 00 , referring to FIG. 7 .

In one embodiment of the present invention, the Ge fin structure 10 may be formed on the substrate 00 by a selective epitaxial process. At this time, the Ge fin-shaped structure 10 is not originally possessed by the substrate 00, but is epitaxially produced. Therefore, the selection range of the substrate 00 is wide, and can be Si substrate, Ge substrate, Si-on-insulator substrate, and Si-on-insulator substrate. Ge substrate, Si substrate with Ge surface, etc.

In another embodiment of the present invention, the Ge fin structure 10 may be formed on the substrate 00 by photolithography and etching processes, wherein the substrate 00 is a substrate whose surface layer is made of Ge material. At this time, the Ge fin structure 10 is what the substrate 00 originally had, rather than being formed later, so the selection range of the substrate 00 is relatively narrow, and it can be a Ge substrate, a Ge-on-insulator substrate, or a Si substrate with a Ge surface. Substrate etc.

S23. Forming a dummy gate on the Ge fin structure.

Specifically, the dummy gate 50 is formed on the region of the predetermined gate stack of the Ge fin structure 10 . Referring to FIG. 8a and FIG. 8b, FIG. 8a is a schematic perspective view, and FIG. 8b is a cross-sectional view along the direction of the channel.

S24. Forming openings for the source region and the drain region on both sides of the dummy gate, exposing the Ge fin structure at the opening position.

Specifically, gate spacers 30 may be further formed on both sides of the dummy gate 50 to define openings of the source region and the drain region. The gate spacer 30 can reduce device leakage. The specific process is as follows: after the above steps, the dielectric material required for the gate sidewall is first deposited, generally a dielectric material different from the dummy gate material is used, and then through a suitable dry etching process, the patterned dummy gate 50 is formed. A gate spacer 30 is formed on the side, and an opening is formed above the source region and the drain region, and the Ge fin structure 10 is exposed at the opening position. Referring to FIG. 9a and FIG. 9b, FIG. 9a is a schematic perspective view, and FIG. 9b is a cross-sectional view along the direction of the channel.

S25. Implanting atoms, molecules, ions or plasma containing both Si and Sn elements into the Ge fin structure to form a SiGeSn layer at the opening position.

Specifically, atoms, molecules, ions or plasma containing both Si and Sn elements can be implanted into the Ge fin structure 10 to transform the surface layer or all of the Ge fin structure 10 exposed at the opening position into the target SiGeSn layer 40 . The SiGeSn layer 40 serves as the source and drain of the FinFET. Referring to FIG. 10a and FIG. 10b, FIG. 10a is a schematic perspective view, and FIG. 10b is a cross-sectional view along the channel direction.

S26 . The dummy gate is removed, and a gate stack is formed in the dummy gate region.

Specifically, the dummy gate 50 may be removed by wet chemical etching or a combination of dry etching and wet chemical etching, and the gate dielectric material and gate material may be deposited in sequence, and then photolithography and etching processes are performed to form a patterned, A gate stack 20 including a gate dielectric layer 20a and a gate layer 20b. So far, a FinFET with SiGeSn source and drain regions has been formed. Referring to FIG. 11a and FIG. 11b , wherein FIG. 11a is a schematic perspective view, and FIG. 11b is a cross-sectional view along the channel direction.

According to the method for forming the FinFET in the second embodiment of the present invention, a fin-shaped field effect transistor with SiGeSn as the source and drain regions can also be obtained, and the SiGeSn layer in the source and drain regions is thinner and of better quality. The advantage of low cost.

In the methods for forming the FinFET according to the above two embodiments of the present invention, the surface of the original Ge layer is modified by using an implantation process. That is, atoms, molecules, ions or plasma containing both Si and Sn elements are implanted into the original Ge layer. By controlling the appropriate temperature and implantation dose, the implanted Sn element does not diffuse significantly, so that the crystal lattice can be made Sn atoms will not gather to form Sn precipitates, and maintain the metastable state of the SiGeSn alloy without segregation. In this way, a SiGeSn layer with a thinner thickness and better quality can be obtained, which has the advantages of simplicity and low cost. In the existing SiGeSn formation methods, the MBE method requires expensive equipment and ultra-high vacuum, the process is complicated and the cost is high; the CVD method is not yet fully mature, because the growth temperature is high, so SiGeSn in a metastable state often undergoes Sn element depletion. Segregation affects the crystal quality of the SiGeSn layer, and its equipment and gas source are relatively expensive, so the cost is also high.

It should be noted that, during the implantation process, only the surface layer of the original Ge fin structure can be changed into a SiGeSn layer, or all of it can be changed into a SiGeSn layer. Specifically, when the source and drain of the FinFET need to form a thicker SiGeSn layer, ions or plasma containing both Si and Sn elements can be implanted. Ions and plasmas have high energy and can be implanted to a certain depth. When the source and drain of the FinFET need to form a thinner SiGeSn layer, not only the SiGeSn layer can be formed by implanting ions or plasma, but also the SiGeSn layer can be formed by implanting Sn atoms or molecules containing both Si and Sn elements.

In an example of the present invention, the method of implantation can adopt ion implantation, that is: an ion beam (including ions or plasma) with a certain energy and containing Si and Sn elements is incident into the Ge layer and stays in the Ge layer. In the Ge layer, part or all of the Ge layer is converted into a SiGeSn alloy. The implantation depth is changed by changing the energy of the ion beam, the higher the ion beam energy, the deeper the implantation. During the implantation process, a variable voltage can be used to obtain a variable ion beam energy, so that the Sn/Si elements are more uniformly distributed within a certain range. Specifically, in addition to conventional ion implantation, ion implantation also includes plasma source ion implantation and plasma immersion ion implantation, that is, plasma-based ion implantation. During plasma-based ion implantation, the Ge layer is annihilated in the plasma containing both Si and Sn elements, and the positive ions containing Sn/Si elements are accelerated under the action of an electric field, shot to the surface of the Ge layer and injected into the Ge layer. Through plasma-based ion implantation, it is easy to achieve a very high implantation dose, that is, it is easy to obtain a SiGeSn layer with a Sn content of 1% to 20%, which has high production efficiency and low cost, and is less affected by the surface shape. , that is, non-planar Ge surfaces can also be implanted uniformly. Among them, plasma immersion ion implantation is a preferred implantation method, because plasma immersion ion implantation is less affected by the shape of the substrate, and the implantation is more uniform. Implantation on a non-planar structure such as a Ge fin structure can obtain relatively smooth parts in various parts. The effect of uniform implantation makes the SiGeSn thin film uniformly formed in the entire source and drain regions, so that the electrical performance of the channel can be improved to the greatest extent. Ion implantation can form a thicker SiGeSn layer, and the higher the implantation energy, the thicker the SiGeSn layer. Preferably, the thickness of the SiGeSn layer is 0.5-100 nm.

In an example of the present invention, magnetron sputtering can be used as the implantation method. During magnetron sputtering, Ar ions are accelerated to the cathode Si-Sn composite target under the action of an electric field, and bombard the target surface with high energy to cause sputtering of the target. The sputtered particles are mainly atoms with a small amount of ions. By adjusting the process parameters such as electric field voltage and vacuum degree, the sputtered particles have higher energy and shoot to the Ge layer at a higher speed, and some particles can be injected into the Ge layer to form a metastable SiGeSn alloy. Optionally, during the process of implanting the Ge layer by magnetron sputtering, a negative bias voltage, such as -40 to -120V, is applied to the substrate, which can make some of the sputtered particles have higher energy, which is beneficial to the The implantation can be deeper into the Ge surface layer, for example, it can be as deep as several nanometers. It should be noted that, since more materials are sputtered during magnetron sputtering, usually a Si—Sn thin film is further formed after the SiGeSn layer is formed. Therefore, after magnetron sputtering, the Si—Sn film formed on the SiGeSn layer by magnetron sputtering also needs to be removed. For example, the Si-Sn thin film may be removed and the SiGeSn layer may be exposed by cleaning with a solution having a high etch selectivity to SiGeSn and Si-Sn. Common cleaning solutions include dilute hydrochloric acid, dilute sulfuric acid, dilute nitric acid. The thickness of the remaining SiGeSn layer after cleaning is 0.5-20 nm, preferably, the thickness of the SiGeSn layer is 0.5-10 nm.

In an example of the present invention, the heating temperature in the implantation process can be controlled between 100-600°C, preferably 150-450°C. The film quality obtained in this temperature range is better. If the temperature is too low, the damage caused by implantation cannot be repaired, and the quality of the SiGeSn layer is poor; if the temperature is too high, the Sn in the SiGeSn layer will diffuse seriously, and the solid solubility of Sn in Ge is very low (atomic Percentage 0.3%), Sn in the SiGeSn layer is easy to precipitate to form Sn precipitates.

In an example of the present invention, the SiGeSn layer may also be strengthened by annealing after the SiGeSn layer is formed. The annealing temperature range is 100-600°C, preferably 150-450°C. If the temperature is too low, the damage caused by implantation cannot be repaired, and the quality of the SiGeSn layer is poor; Precipitate to form Sn precipitate. It should be pointed out that if the gate-first process is used, the gate dielectric may not be able to withstand a high temperature above 450°C. At this time, the heating temperature and annealing temperature in the implantation process can be controlled below 400°C.

In one example of the invention, the SiGeSn layer is a strained SiGeSn layer. The thickness of the strained SiGeSn layer is 0.5-100 nm. Preferably 10-40nm. The atomic percent content of Sn in the strained SiGeSn layer is less than 20%. It should be noted that the higher the Sn content in the fully strained SiGeSn layer, the greater the strain, and correspondingly its thickness should be reduced below the relaxation critical thickness in order to maintain full strain. The higher the Sn content in the strained SiGeSn layer, the thinner its critical thickness. When the Si content is 20% and the Sn content is 15%, the strain degree of the fully strained SiGeSn film on Ge is about 1.5%. At this time, the critical thickness of the strained SiGeSn layer is about 30nm, which is the SiGeSn thickness of the source and drain regions of the FinFET at this time. It should not exceed 30nm; and when the Si content is 20% and the Sn content is 10%, the strain degree is about 0.8%, and the critical thickness can reach more than 100nm, indicating that the SiGeSn thickness of the source and drain regions of the FinFET can reach 100nm and the SiGeSn layer is still Stay fully strained.

It should be further explained that when the SiGeSn layer is a strained SiGeSn layer, the heating temperature in the implantation process and the annealing temperature in the annealing process need to match the material properties of the strained SiGeSn layer. For example, a strained SiGeSn layer with 10-15% Sn content is required in common FinFET semiconductor devices. By adding Si, the 10-15% SiGeSn layer is basically stable at 450°C, so the substrate temperature in the above-mentioned implantation process under this Sn content And the annealing temperature in the annealing process needs not to exceed 450°C.

The present invention also proposes a fin field effect transistor with SiGeSn source and drain, which is formed by any of the methods disclosed above, including: a substrate; a Ge fin-shaped channel region formed on the substrate; a gate stack structure above the Ge fin-shaped channel region; and a SiGeSn source and drain formed on both sides of the Ge fin-shaped channel region. The source and drain regions of the fin field effect transistor have thinner and better quality SiGeSn layers, and have the advantages of good electrical performance and low cost.

It should be noted that the FinFET with SiGeSn source and drain can be formed by any method disclosed above, but is not limited thereto.

In order to make those skilled in the art understand the present invention better, set forth specific embodiment as follows:

Firstly, prepare the Si substrate, and wash it with acetone, absolute ethanol, deionized water and hydrofluoric acid in sequence for future use.

Second, a Ge fin structure is formed on the Si substrate by a selective epitaxial process. Specifically, a silicon nitride mask can be deposited on the Si substrate first, and then through photolithography and etching processes, openings are formed in the mask, and through a selective epitaxy process, the positions of the openings on the top surface of the Si substrate are selectively The Ge fin-shaped structure is epitaxially grown, and the thickness of the Ge fin-shaped structure is controlled so that the thickness of the Ge fin-shaped structure is greater than the thickness of the mask layer and a fin-shaped structure is formed.

Next, gate dielectric material HfO ₂ and gate material TaN/TiAl/TiN are deposited on the Ge fin structure, and then a patterned HfO ₂ /TaN/TiAl/TiN gate is obtained through photolithography and etching processes. stack and form openings above the source and drain regions.

Then, deposit the gate sidewall material. Silicon nitride can be used as the gate sidewall material. Through a dry etching process, gate sidewalls are formed on both sides of the gate stack, and openings are formed above the source and drain regions. The Ge fin-shaped structure is exposed. The size of the opening at this time is smaller than the size of the opening when there is no gate spacer.

Finally, the plasma immersion ion implantation process is used to inject plasma containing both Si and Sn elements into the substrate. At this time, the substrate heating temperature is 100-200°C, the implantation voltage is 10-25KeV, and the implantation dose of Si and Sn They are about 1×10 ¹⁷ /cm ² and 8×10 ¹⁶ /cm ² , respectively. After the implantation is completed, a 15-30nm thick strained SiGeSn layer is formed on the surface of the Ge fin structure at the source and drain openings, and the Sn content is about 15%. Further, by ion implantation, heavily doped source and drain structures can be formed. Perform annealing treatment on the substrate after the ion implantation, the annealing temperature is 200-300° C., so as to further strengthen the SiGeSn layer.

At this time, a FinFET device whose source region and drain region are made of SiGeSn material is obtained.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be construed as limitations to the present invention. Variations, modifications, substitutions, and modifications to the above-described embodiments are possible within the scope of the present invention.

Claims (19)

1. a method for forming a fin field effect transistor with SiGeSn source and drain, is characterized in that, comprises the following steps: provide the substrate; forming a Ge fin structure over the substrate; forming a gate stack or dummy gate over the Ge fin structure; forming openings for a source region and a drain region on both sides of the gate stack or dummy gate, exposing the Ge fin structure at the position of the opening; Atoms, molecules, ions or plasma containing both Si and Sn elements are implanted into the Ge fin structure to form a SiGeSn layer at the opening position. 2. the method for forming the fin field effect transistor with SiGeSn source and drain as claimed in claim 1, is characterized in that, also comprises: Before forming the openings of the source region and the drain region, gate spacers are formed on both sides of the gate stack or the dummy gate. 3. The forming method of the fin field effect transistor with SiGeSn source and drain as claimed in claim 1 or 2, is characterized in that, also comprises: After forming the SiGeSn layer, the dummy gate is removed, and a gate stack is formed in the dummy gate region. 4. the formation method of the fin field effect transistor with SiGeSn source and drain as described in any one of claim 1-3, it is characterized in that, described substrate is Si substrate, Ge substrate, Si substrate on insulator , Ge-on-insulator substrate, Si substrate with Ge surface. 5. The method for forming a fin field effect transistor having a SiGeSn source and drain as claimed in any one of claims 1 to 3, wherein the Ge fin is formed on the substrate by a selective epitaxy process. structure. 6. The method for forming a fin field effect transistor with a SiGeSn source and drain as claimed in any one of claims 1-3, wherein the Ge The fin structure, wherein the surface layer of the substrate is made of Ge material. 7. the formation method of the fin field effect transistor with SiGeSn source and drain as claimed in claim 6 is characterized in that, the substrate that described surface layer is Ge material is Ge substrate, Ge substrate on insulator, or has Ge substrate. surface of the Si substrate. 8 . The method for forming a fin field effect transistor with SiGeSn source and drain according to claim 1 , wherein the implantation method includes ion implantation. 9 . The method for forming a fin field effect transistor with SiGeSn source and drain according to claim 8 , wherein the ion implantation comprises plasma source ion implantation and plasma immersion ion implantation. 10. The method for forming a fin field effect transistor with SiGeSn source and drain according to any one of claims 1-3, characterized in that the injection method comprises magnetron sputtering. 11 . The method for forming a fin field effect transistor with SiGeSn source and drain according to claim 10 , characterized in that, during the implantation process using the magnetron sputtering, a negative bias voltage is applied to the substrate. 12. The method for forming a fin field effect transistor with SiGeSn source and drain as claimed in claim 10 or 11, further comprising, removing the Si- Sn film. 13. the method for forming the fin field effect transistor with SiGeSn source and drain as claimed in claim 12, is characterized in that, utilizes SiGeSn and Si-Sn to have the solution cleaning of high corrosion selectivity ratio to remove described Si-Sn thin film . 14. The method for forming a fin field effect transistor with a SiGeSn source and drain as claimed in any one of claims 1-3, wherein the substrate is heated during the implantation, and the heating temperature is 100- 600°C. 15. The method for forming a fin field effect transistor with a SiGeSn source and drain according to any one of claims 1-3, further comprising, after the implantation, annealing the SiGeSn layer at an annealing temperature of 100-600°C. 16. The method for forming a fin field effect transistor with SiGeSn source and drain according to any one of claims 1-3, wherein the SiGeSn layer is a strained SiGeSn layer. 17 . The method for forming a fin field effect transistor with SiGeSn source and drain according to claim 16 , wherein the strained SiGeSn layer has a thickness of 0.5-100 nm. 18 . The method for forming a fin field effect transistor with SiGeSn source and drain as claimed in claim 16 , wherein the atomic percentage of Sn in the strained SiGeSn layer is less than 20%. 19. A fin field effect transistor with SiGeSn source and drain, characterized in that it comprises: Substrate; Ge fin-shaped channel regions formed over the substrate; a gate stack structure formed over the Ge fin-shaped channel region; and A SiGeSn source and drain are formed on both sides of the Ge fin-shaped channel region.

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