CN103839834B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a semiconductor device and its manufacturing method. An object of the present invention is to provide a semiconductor device including a thin film transistor having excellent electrical characteristics and high reliability, and a method of manufacturing the semiconductor device without unevenness. The gist of the present invention is to use an oxide semiconductor film containing In, Ga, and Zn as the semiconductor layer, and include an inverted staggered type (bottom gate structure) in which a buffer layer is provided between the semiconductor layer and the source electrode layer and the drain electrode layer. thin film transistor. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn having a carrier concentration higher than that of the semiconductor layer between the source electrode layer and the drain electrode layer and the semiconductor layer.

Description

Semiconductor device and manufacturing method thereof

This application is a divisional application with the filing date of "July 30, 2009", the application number of "200910160557.0", and the title of "semiconductor device and its manufacturing method".

technical field

One aspect of the present invention relates to a semiconductor device including a circuit including a thin film transistor (hereinafter referred to as TFT) using an oxide semiconductor film for a channel formation region, and a method for manufacturing the same. For example, one aspect of the present invention relates to an electronic device mounted using an electro-optical device typified by a liquid crystal display panel and a light-emitting display device including an organic light-emitting element as components.

Note that in this specification, a semiconductor device refers to all devices that can function using semiconductor characteristics. Electro-optical devices, semiconductor circuits, and electronic equipment are all semiconductor devices.

Background technique

In recent years, active research and development has been conducted on an active matrix type display device (liquid crystal display device, light emitting display device, electrophoretic display device) in which each display device arranged in a matrix A switching element composed of a thin film transistor (TFT) is provided in the pixel. In an active matrix display device, a switching element is provided for each pixel (or each dot), and when the pixel density is increased compared with a simple matrix type display device, low-voltage driving can be performed, which is advantageous.

In addition, techniques for manufacturing thin-film transistors (TFTs) and the like by using an oxide semiconductor film in a channel formation region and applying them to electronic and optical devices have attracted attention. For example, a TFT using ZnO as an oxide semiconductor film and a TFT using InGaO ₃ (ZnO) _m as an oxide semiconductor film can be mentioned. Patent Document 1, Patent Document 2, and the like disclose techniques in which such a TFT formed using an oxide semiconductor film is formed on a light-transmitting substrate and used as a switching element of an image display device or the like.

[Patent Document 1] Japanese Patent Application Publication No. 2007-123861

[Patent Document 2] Japanese Patent Application Publication No. 2007-96055

A thin film transistor using an oxide semiconductor film in a channel formation region is required to have a high operating speed, a relatively simple manufacturing process, and sufficient reliability.

When forming a thin film transistor, a low-resistance metal material is used as the source electrode layer and the drain electrode layer. In particular, when manufacturing a display device that performs large-area display, the problem of signal delay due to resistance of wiring appears significantly. Therefore, it is preferable to use a metal material with a low resistance value as the material of the wiring and the electrode. On the other hand, when a thin film transistor structure is adopted in which the source electrode layer and the drain electrode layer made of a metal material having a low resistance value are in direct contact with the oxide semiconductor film, there is a concern that the contact resistance may increase. The phenomenon that Schottky junctions are formed at the contact surfaces of the source electrode layer and the drain electrode layer and the oxide semiconductor film is considered to be one of the causes of the increase in contact resistance.

In addition, there is a concern that capacitance will be formed at the portion where the source electrode layer and the drain electrode layer are in direct contact with the oxide semiconductor film, and the frequency characteristic (referred to as f characteristic) will be lowered, thereby hindering the high-speed operation of the thin film transistor.

Contents of the invention

One of the problems of one aspect of the present invention is to provide a thin film transistor using an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn), in which the source electrode and drain electrode and the oxide semiconductor film are reduced. The contact resistance of the layer is also provided, and its fabrication method is also provided.

Another object of one aspect of the present invention is to improve the operating characteristics and reliability of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn.

Another object of one aspect of the present invention is to reduce unevenness in electrical characteristics of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn. In particular, in a liquid crystal display device, if the unevenness among the individual elements is large, there is a possibility that display unevenness due to the unevenness of the TFT characteristics may occur.

In addition, in a display device having a light-emitting element, there is also concern that when the on-current (I _On ) unevenness is large, unevenness in luminance occurs on the display screen. As described above, one aspect of the present invention aims to solve at least one of the above-mentioned problems.

The gist of one aspect of the present invention is to use an oxide semiconductor layer containing In, Ga, and Zn as the semiconductor layer, and include an inverted staggered type (bottom electrode layer) in which a buffer layer is provided between the semiconductor layer and the source electrode layer and the drain electrode layer. gate structure) thin film transistors.

In this specification, a semiconductor layer formed using an oxide semiconductor film containing In, Ga, and Zn is also referred to as an "IGZO semiconductor layer".

The source electrode layer and the IGZO semiconductor layer need to be in ohmic contact. Furthermore, it is preferable to reduce this contact resistance as much as possible. Likewise, the drain electrode layer and the IGZO semiconductor layer need to be in ohmic contact. Furthermore, it is preferable to reduce this contact resistance as much as possible.

Then, an ohmic contact is formed by intentionally providing a buffer layer having a carrier concentration higher than that of the IGZO semiconductor layer between the source electrode layer and the drain electrode layer and the IGZO semiconductor layer.

As the buffer layer, an oxide semiconductor film containing In, Ga, and Zn having n-type conductivity is used. The buffer layer may contain an n-type impurity element. As impurity elements, for example, magnesium, aluminum, titanium, scandium, yttrium, zirconium, hafnium, boron, thallium, germanium, tin, lead, etc. can be used. When the buffer layer is made of magnesium, aluminum, titanium, etc., the oxygen barrier effect and the like are exhibited, and the oxygen concentration of the semiconductor layer can be kept in an optimum range by heat treatment after film formation, etc.

This buffer layer serves as an n ⁺ layer and may also be called a drain or source region.

One mode of the semiconductor device of the present invention includes a thin film transistor formed with: a gate electrode; a gate insulating film covering the gate electrode; an IGZO semiconductor layer on the gate electrode via the gate insulating film; The channel protective layer in the region where the channel forming region overlaps; the source electrode layer and the drain electrode layer on the IGZO semiconductor layer; and the buffer layer between the semiconductor layer and the source electrode layer and the drain electrode layer, wherein the carrier layer of the buffer layer The carrier concentration is higher than that of the IGZO semiconductor layer, and the IGZO semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer via the buffer layer.

In the above structure, a second buffer layer having a carrier concentration higher than that of the semiconductor layer and lower than that of the buffer layer may be provided between the semiconductor layer and the buffer layer. The second buffer layer serves as the n ^- layer.

An oxide semiconductor film (IGZO film) containing In, Ga, and Zn has a characteristic that hole mobility increases as the carrier concentration increases. Therefore, the relationship between the carrier concentration and the hole mobility of the oxide semiconductor film containing In, Ga, and Zn is as shown in FIG. 29 . In one aspect of the present invention, it is preferable that the carrier concentration range (channel concentration range 1) of the IGZO film suitable for the channel of the semiconductor layer is lower than 1×10 ¹⁷ atoms/cm ³ (more preferably 1× 10 ¹¹ atoms/cm ³ or more), and the carrier concentration range of the IGZO film suitable for the buffer layer (buffer layer concentration range 2) is 1×10 ¹⁸ atoms/cm ³ or more (1×10 ²² atoms/cm ³ or less) . When an IGZO film is used as the semiconductor layer, the carrier concentration of the IGZO film is a value at room temperature in a state where no source, drain, and gate voltages are applied.

When the carrier concentration range of the channel IGZO film exceeds the above-mentioned range (channel concentration range 1), there is a possibility that the thin film transistor will be normally on.

Note that the carrier concentration and hole mobility of the IGZO film can be obtained from the Hall effect measurement. As an example of the Hall effect measuring device, a specific resistance/Hall measuring system ResiTest8310 (manufactured by TOYO Corporation, Japan) can be cited. The specific resistance/Hall measurement system ResiTest8310 can perform AC (AC) Hall measurement, that is, change the direction and magnitude of the magnetic field at a certain period, and only detect the Hall electromotive voltage (Hall electromotive voltage) generated in the sample synchronously. ). Hall voltage can also be detected for materials with low mobility and high resistivity.

In the above structure, the source electrode layer and the drain electrode layer preferably contain titanium. For example, when a multilayer film in which a titanium film, an aluminum film, and a titanium film are stacked is used, low resistance is achieved and hillocks are less likely to be generated in the aluminum film.

Since the structure of the thin film transistor according to one aspect of the present invention is a structure in which a channel protection layer is provided, it is possible to protect the region of the IGZO semiconductor layer on the side opposite to the surface contacting the gate insulating film, that is, the so-called back channel protection layer. Resists damage during the process (reduction in film thickness, oxidation, etc. due to plasma and etchant during etching), and improves the reliability of semiconductor devices.

One mode of the manufacturing method of the semiconductor device of the present invention includes the following steps: forming a gate electrode layer on the substrate; forming a gate insulating film on the gate electrode layer; forming an IGZO semiconductor layer on the gate insulating film; A channel protective layer is formed in the overlapping area of the channel formation area on the layer; a pair of buffer layers with n-type conductivity are formed on the IGZO semiconductor layer; and a source electrode layer and a drain electrode layer are formed on the buffer layer. Wherein, a pair of buffer layers having n-type conductivity is formed using an oxide semiconductor layer containing In, Ga, and Zn, and the carrier concentration of the buffer layer is higher than that of the IGZO semiconductor layer, and the IGZO semiconductor layer layer, the source electrode layer and the drain electrode layer are electrically connected via the buffer layer.

In addition, when the gate insulating film, the semiconductor film, and the channel protective layer are continuously formed without being exposed to the atmosphere, not only the productivity is improved, but also the atmospheric components that do not generate water vapor and the like can be formed and The contamination of the stack interface caused by impurity elements and dust suspended in the medium can reduce the unevenness of the characteristics of the thin film transistor.

In other words, when the gate insulating film, the oxide semiconductor film containing In, Ga, and Zn as the semiconductor film, and the insulating film as the channel protective layer are continuously formed without being exposed to the atmosphere, not only the productivity is improved, but also the formation of Since there is no contamination of the lamination interface caused by atmospheric components such as water vapor, impurity elements suspended in the atmosphere, and dust, it is possible to reduce the unevenness of the characteristics of the thin film transistor.

The continuous film formation in this specification refers to the following state: in a series of processes from the first film formation process performed by the sputtering method to the second film formation process performed by the sputtering method, the substrate to be processed is placed The atmosphere is always controlled as a vacuum or an inert gas atmosphere (nitrogen atmosphere or rare gas atmosphere) without contact with a polluted atmosphere such as the air. By performing continuous film formation, it is possible to form a film while preventing moisture or the like from reattaching to the cleaned substrate to be processed.

The scope of continuous film formation in this specification includes the case where a series of processes from the first film formation step to the second film formation step are performed in the same processing chamber.

In addition, the scope of continuous film formation in this specification also includes when a series of processes from the first film formation process to the second film formation process are performed in different processing chambers, after the first film formation process is completed, the process is performed without contact. The second film formation is carried out by transporting the substrate between the processing chambers in the atmosphere.

Note that the scope of continuous film formation in this specification also includes a substrate transfer process, alignment process, slow cooling process, or temperature required for the second process between the first film forming process and the second film forming process. In the case of the process of heating or cooling the substrate, etc.

However, the scope of continuous film formation in this specification does not include the case where there is a process using a liquid such as a cleaning process, wet etching, and resist formation between the first film forming process and the second film forming process.

In addition, by forming the gate insulating film, semiconductor layer, and channel protective layer under an oxygen atmosphere (or oxygen 90% or more, rare gas (argon, etc.) 10% or less), the reduction in reliability due to degradation can be reduced , The shift of the normally-on state side of the thin film transistor characteristics, etc. In addition, it is preferable to form the buffer layer having n-type conductivity under a rare gas (such as argon) atmosphere.

One mode of the manufacturing method of the semiconductor device of the present invention includes the following steps: forming a gate electrode layer on the substrate; forming a gate insulating film on the gate electrode layer; forming an IGZO semiconductor layer on the gate insulating film; A channel protective layer is formed in the overlapping area of the channel formation region on the layer; and a pair of buffer layers with n-type conductivity are formed on the IGZO semiconductor layer; a source electrode layer and a drain electrode layer are formed on the buffer layer. Wherein, a pair of buffer layers having n-type conductivity is formed using an oxide semiconductor layer containing In, Ga, and Zn, and the carrier concentration of the buffer layer is higher than that of the IGZO semiconductor layer, and the IGZO semiconductor layer layer, the source electrode layer and the drain electrode layer are electrically connected through a buffer layer, and a gate insulating film, a semiconductor layer, and a channel protective layer are continuously formed without being exposed to the atmosphere.

One aspect of the semiconductor device of the present invention is a thin film transistor formed with: a gate electrode; a gate insulating film covering the gate electrode; a semiconductor layer on the gate electrode via the gate insulating film; The channel protective layer in the overlapping region of the channel formation region; the source electrode layer and the drain electrode layer on the semiconductor layer; the buffer layer between the semiconductor layer and the source electrode layer and the drain electrode layer. Wherein, the semiconductor layer and the buffer layer include an oxide semiconductor including indium, gallium, and zinc, and the carrier concentration of the buffer layer is higher than that of the semiconductor layer, and the semiconductor layer and the source electrode layer and the drain electrode layer electrically connected through the buffer layer.

One aspect of the semiconductor device of the present invention is the semiconductor device in which the buffer layer contains n-type impurities.

One aspect of the semiconductor device of the present invention is a semiconductor device wherein the carrier concentration of the semiconductor layer is lower than 1×10 ¹⁷ atoms/cm ³ , and the carrier concentration of the buffer layer is 1×10 ¹⁸ atoms/cm 3 ³ or more.

One aspect of the semiconductor device of the present invention is a semiconductor device in which a second layer having a carrier concentration higher than that of the semiconductor layer and lower than that of the buffer layer is included between the semiconductor layer and the buffer layer. Second buffer layer.

One aspect of the semiconductor device of the present invention is the semiconductor device wherein the source electrode layer and the drain electrode layer contain titanium.

Another aspect of the disclosed invention is a method of manufacturing a semiconductor device, comprising the steps of: forming a gate electrode layer on a substrate; forming a gate insulating film on the gate electrode layer; forming a semiconductor layer on the gate insulating film ; forming a channel protective layer in a region overlapping with the channel forming region on the semiconductor layer; and forming a pair of buffer layers with n-type conductivity on the semiconductor layer; forming a source electrode layer and a drain electrode layer on the buffer layer. Wherein, the semiconductor layer and the buffer layer having n-type conductivity are formed using an oxide semiconductor layer containing In, Ga, and Zn, and the carrier concentration of the buffer layer is higher than that of the semiconductor layer, and the semiconductor layer It is electrically connected to the source electrode layer and the drain electrode layer through the buffer layer.

Another aspect of the disclosed invention is a method of manufacturing a semiconductor device, comprising the steps of: forming a gate electrode layer on a substrate; forming a gate insulating film on the gate electrode layer; forming a semiconductor layer on the gate insulating film ; forming a channel protective layer in the region overlapping with the channel forming region on the semiconductor layer; and forming a buffer layer with n-type conductivity on the semiconductor layer; forming a source electrode layer and a drain electrode layer on the buffer layer. Among them, the semiconductor layer and the buffer layer are formed using an oxide semiconductor layer containing indium, gallium, and zinc, and the carrier concentration of the buffer layer is higher than that of the semiconductor layer, and the semiconductor layer, the source electrode layer, and the leakage current The electrode layers are electrically connected via a buffer layer, and a gate insulating film, a semiconductor layer, and a channel protective layer are successively formed without being exposed to the atmosphere.

Another aspect of the disclosed invention is a method of manufacturing a semiconductor device in which a gate insulating film, a semiconductor layer, and a channel protective layer are formed by a sputtering method.

Another aspect of the disclosed invention is a method of manufacturing a semiconductor device, wherein a gate insulating film, a semiconductor layer, and a channel protective layer are formed in an oxygen atmosphere.

Another aspect of the disclosed invention is a method of manufacturing a semiconductor device in which the buffer layer is formed under a rare gas atmosphere.

Another aspect of the disclosed invention is a method of manufacturing a semiconductor device, wherein the carrier concentration of the semiconductor layer is lower than 1×10 ¹⁷ atoms/cm ³ , and the carrier concentration of the buffer layer is 1×10 ¹⁸ atoms/cm ³ or more.

Another aspect of the disclosed invention is a method of manufacturing a semiconductor device, wherein the buffer layer is formed of magnesium, aluminum, or titanium.

According to one aspect of the present invention, a thin film transistor having a small photocurrent, a small parasitic capacitance, and a high on/off ratio can be obtained, and a thin film transistor having excellent dynamic characteristics (f characteristics) can also be manufactured. Therefore, it is possible to provide a semiconductor device including a thin film transistor with high electrical characteristics and high reliability.

Description of drawings

1A and 1B are diagrams illustrating a semiconductor device according to one embodiment of the present invention;

2A to 2D are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention;

3A1 to 3D are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention;

4A to 4D are diagrams illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention;

5A and 5B are diagrams illustrating a semiconductor device according to one embodiment of the present invention;

6A and 6B are diagrams illustrating a semiconductor device according to one embodiment of the present invention;

7A and 7B are diagrams illustrating a semiconductor device according to one embodiment of the present invention;

FIG. 8 is a diagram illustrating a semiconductor device according to one embodiment of the present invention;

FIG. 9 is a schematic top view of a multi-chamber manufacturing device;

10A and 10B are diagrams illustrating a block diagram of a display device;

FIG. 11 is a diagram illustrating a structure of a signal line driving circuit;

FIG. 12 is a timing chart illustrating the operation of the signal line driving circuit;

FIG. 13 is a timing chart illustrating the operation of the signal line driving circuit;

FIG. 14 is a diagram illustrating the structure of a shift register;

FIG. 15 is a diagram illustrating the connection structure of the flip-flop shown in FIG. 14;

16A and 16B are diagrams illustrating a liquid crystal display device to which an embodiment of the present invention is applied;

FIG. 17 is a diagram illustrating an electronic paper to which an embodiment of the present invention is applied;

18A and 18B are diagrams illustrating a light-emitting display device to which one mode of the present invention is applied;

FIG. 19 is a diagram illustrating a light-emitting display device to which an embodiment of the present invention is applied;

20A to 20C are diagrams illustrating a light-emitting display device to which one embodiment of the present invention is applied;

21A and 21B are diagrams illustrating a light-emitting display device to which one mode of the present invention is applied;

22A1, 22A2 and 22B are diagrams illustrating a liquid crystal display device to which one mode of the present invention is applied;

FIG. 23 is a diagram illustrating a liquid crystal display device to which an embodiment of the present invention is applied;

24A and 24B are diagrams illustrating an electronic device to which an embodiment of the present invention is applied;

FIG. 25 is a diagram illustrating an electronic device to which an embodiment of the present invention is applied;

26A and 26B are diagrams illustrating an electronic device to which an embodiment of the present invention is applied;

FIG. 27 is a diagram illustrating an electronic device to which an embodiment of the present invention is applied;

FIG. 28 is a diagram illustrating an electronic device to which an embodiment of the present invention is applied;

FIG. 29 is a graph illustrating the relationship between carrier concentration and hole mobility.

detailed description

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following descriptions, and those skilled in the art can easily understand the fact that the manner and details can be changed into various forms without departing from the spirit and spirit of the present invention. scope. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below. Note that, in the structure of the present invention described below, the same reference numerals are commonly used in different drawings to denote the same parts or parts having the same functions, and repeated description thereof will be omitted.

Embodiment 1

In this embodiment mode, a thin film transistor and its manufacturing process will be described with reference to FIGS. 1A and 1B and FIGS. 2A to 2D .

1A and 1B show a thin-film transistor having a bottom-gate structure in this embodiment mode. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along A1-A2 in FIG. 1A. In the thin film transistor shown in FIGS. 1A and 1B, a gate electrode 101 is formed on a substrate 100, a gate insulating film 102 is formed on the gate electrode 101, and a gate insulating film 102 is formed on the gate electrode 101 via the gate insulating film 102. In the amorphous oxide semiconductor layer 103 serving as a channel formation region, a channel protective layer 106 is formed in a region overlapping with the channel formation region of the amorphous oxide semiconductor layer 103, and a channel protective layer 106 is formed on the amorphous oxide semiconductor layer 103. The buffer layers 104a and 104b are in contact with the buffer layers 104a and 104b, and source and drain electrode layers 105a and 105b are formed.

By using an oxide semiconductor containing In, Ga, and Zn as the semiconductor layer 103, a buffer having a carrier concentration higher than that of the semiconductor layer 103 is intentionally provided between the source and drain electrode layers 105a, 105b and the semiconductor layer 103. Layers 104a, 104b form ohmic contacts.

Buffer layers 104a, 104b are formed using an oxide semiconductor containing In, Ga, and Zn having n-type conductivity. In addition, the buffer layer may contain an n-type impurity element. As impurity elements, for example, magnesium, aluminum, titanium, scandium, yttrium, zirconium, hafnium, boron, thallium, germanium, tin, lead, etc. can be used. The oxygen concentration of the semiconductor layer 103 can be kept in an optimum range by making the buffer layer contain magnesium, aluminum, titanium, etc., to exhibit an oxygen barrier effect, and by heat treatment after film formation, etc.

The buffer layers 104a, 104b are used as n ⁺ layers, which may also be referred to as drain regions or source regions.

A method of manufacturing the thin film transistor shown in FIGS. 1A and 1B will be described with reference to FIGS. 2A to 2D . First, the gate electrode 101 , the gate insulating film 102 , the semiconductor film 133 , and the channel protective layer 106 are formed over the substrate 100 (see FIG. 2A ).

As the substrate 100, in addition to an alkali-free glass substrate such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass manufactured by a fusion method or a float method, and a ceramic substrate, A plastic substrate or the like having heat resistance capable of withstanding the processing temperature in this manufacturing process is used. In addition, a substrate in which an insulating film is provided on the surface of a metal substrate such as a stainless steel alloy can also be applied. In the case where the substrate 100 is a mother glass, as the size of the substrate, the first generation (320mm×400mm), the second generation (400mm×500mm), the third generation (550mm×650mm), the fourth generation ( 680mm×880mm or 730mm×920mm), the fifth generation (1000mm×1200mm or 1100mm×1250mm), the sixth generation (1500mm×1800mm), the seventh generation (1900mm×2200mm), the eighth generation (2160mm×2460mm), the The ninth generation (2400mm×2800mm, 2450mm×3050mm), the tenth generation (2950mm×3400mm), etc.

In addition, an insulating film serving as a base film may also be formed on the substrate 100 . As the base film, a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon oxynitride film may be formed by a CVD method, a sputtering method, or the like.

The gate electrode 101 is formed of a metal material. As the metal material, aluminum, chromium, titanium, tantalum, molybdenum, copper, and the like are used. A preferable example of the gate electrode is formed of aluminum or a laminated structure of aluminum and a barrier metal. As the barrier metal, high-melting-point metals such as titanium, molybdenum, and chromium are used. A barrier metal is preferably provided in order to prevent hillocking and oxidation of the aluminum.

The gate electrode is formed with a thickness of not less than 50 nm and not more than 300 nm. By setting the thickness of the gate electrode to 300 nm or less, it is possible to prevent cracking of semiconductor films and wirings formed later. In addition, by setting the thickness of the gate electrode to be 150 nm or more, the resistance of the gate electrode can be reduced, and a larger area can also be achieved.

Note that since a semiconductor film and wiring are formed on the gate electrode 101, it is preferable to process the end portion thereof into a tapered shape in order to prevent cracking. In addition, although not shown, this step can simultaneously form the wiring connected to the gate electrode and the capacitor wiring.

The gate electrode 101 can be formed by a sputtering method, a CVD method, a plating method, a printing method, or a conductive nanopaste of silver, gold, copper, or the like. In addition, the gate electrode may be formed by ejecting liquid droplets including conductive particles and the like by an inkjet method and firing them.

Note that here, as shown in FIG. 2A, a laminate of an aluminum film and a molybdenum film is formed as a conductive film on a substrate by a sputtering method, and a resist formed using the first photomask in this embodiment mode is used. A mask is used to etch the conductive film formed on the substrate, thereby forming the gate electrode 101 .

In this embodiment mode, an example in which a multilayer film in which two insulating films are stacked is used as the gate insulating film 102 is shown. The first insulating film 102a and the second insulating film 102b can be formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film with a thickness of 50 nm to 150 nm, respectively. Here, a method in which a silicon nitride film or a silicon nitride oxide film is formed as the first gate insulating film 102 a and a silicon oxide film or a silicon oxynitride film is formed as the second gate insulating film 102 b is stacked. Note that instead of forming the gate insulating film in two layers, the gate insulating film may be formed in a single layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. In addition, a three-layer gate insulating film may also be formed.

By forming the first gate insulating film 102a using a silicon nitride film or a silicon oxynitride film, the adhesion between the substrate and the first gate insulating film 102a is improved, and when a glass substrate is used as the substrate, it is possible to prevent the Impurities of the substrate diffuse into the oxide semiconductor film, and oxidation of the gate electrode 101 can be prevented. In other words, it is possible to improve the electrical characteristics of a thin film transistor to be formed later while preventing film peeling. In addition, when the thicknesses of the first gate insulating film 102 a and the second gate insulating film 102 b are respectively 50 nm or more, it is possible to cover the unevenness of the gate electrode 101 , which is preferable.

Here, the silicon oxynitride film refers to a film whose composition contains more oxygen than nitrogen, and its concentration range includes 55 atomic % to 65 atomic % of oxygen, 1 atomic % to 20 atomic % of nitrogen, 25 atomic % % to 35 atomic % of Si, and 0.1 atomic % to 10 atomic % of hydrogen. In addition, the silicon oxynitride film refers to a film whose composition contains more nitrogen than oxygen, and its concentration range includes 15 atomic % to 30 atomic % of oxygen, 20 atomic % to 35 atomic % of nitrogen, 25 atomic % to 35 atomic % Si, and 15 atomic % to 25 atomic % hydrogen.

In addition, as the second gate insulating film 102 b in contact with the semiconductor layer 103 , for example, silicon oxide, aluminum oxide, magnesium oxide, aluminum nitride, yttrium oxide, or hafnium oxide can be used.

The first gate insulating film 102a and the second gate insulating film 102b can be formed by a CVD method, a sputtering method, or the like. Here, as the first gate insulating film 102a, a silicon nitride film is formed by plasma CVD.

In particular, it is preferable to continuously form the second gate insulating film 102b and the semiconductor film 133 in contact with the semiconductor film 133 . By continuous formation, it is possible to form a lamination interface that does not generate contamination by atmospheric components such as water vapor, impurity elements suspended in the atmosphere, and dust, so that unevenness in characteristics of thin film transistors can be reduced.

In an active matrix type display device, electrical characteristics of thin film transistors constituting a circuit are important, and the electrical characteristics affect the performance of the display device. In particular, a threshold voltage (Vth) is important in electrical characteristics of a thin film transistor. Even when the field effect mobility is high and the threshold voltage value is high, or even if the field effect mobility is high and the threshold voltage value is negative, control as a circuit is difficult. When a thin film transistor with a high threshold voltage value and a large absolute value of the threshold voltage value is used, there is a concern that the switching function as the thin film transistor cannot be performed in a state where the driving voltage is low, which may become a load. In addition, when the threshold voltage value is negative, it easily becomes a so-called normally-on state in which a current is generated between the source electrode and the drain electrode even if the gate voltage is 0V.

In the case of using an n-channel thin film transistor, it is preferable to use a transistor in which a channel is formed and leakage current starts to be generated only when a positive voltage is applied to a gate voltage. The following transistors are unsuitable thin film transistors for circuits: transistors that do not form a channel unless the driving voltage is increased; transistors that form a channel even in a negative voltage state to generate leakage current. Therefore, even in a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn, it is preferable to form a channel with a positive threshold voltage whose gate voltage is as close to 0 V as possible.

It is considered that the threshold voltage of a thin film transistor greatly affects the interface of the semiconductor layer, that is, the interface between the semiconductor layer and the gate insulating film. Therefore, by forming these interfaces in a clean state, the electrical characteristics of the thin film transistor can be improved and the complication of the manufacturing process can be prevented, thereby realizing a thin film transistor with mass productivity and high performance.

In particular, if moisture exists at the interface between the oxide semiconductor layer and the gate insulating film, problems such as degradation of electrical characteristics of the thin film transistor, non-uniformity of threshold voltage, and tendency to become normally-on may be caused. Such hydrogen compounds can be removed by successively forming an oxide semiconductor layer and a gate insulating film.

Therefore, by continuously forming a gate insulating film and an oxide semiconductor film by sputtering under reduced pressure without exposure to the atmosphere, a thin film transistor having a high-quality interface, low leakage current, and high current drive capability can be realized.

In addition, it is preferable to form the gate insulating film and the oxide semiconductor film containing In, Ga, and Zn under an oxygen atmosphere (or 90% or more of oxygen, and 10% or less of a rare gas (argon, etc.)).

As such, when continuous film formation is performed by the sputtering method, the productivity is improved and the reliability of the thin film interface is stabilized. In addition, by forming the gate insulating film and the semiconductor layer under an oxygen atmosphere and making them contain a lot of oxygen, it is possible to reduce reliability reduction due to degradation, and a phenomenon in which the thin film transistor becomes a normally-on state.

In addition, it is preferable to form the insulating film to be the channel protective layer 106 continuously after forming the semiconductor film. By performing continuous film formation, atmospheric components that do not generate water vapor, impurity elements suspended in the atmosphere, and the like can be formed in the region of the semiconductor film on the opposite side of the surface contacting the gate insulating film, that is, the so-called back channel. The contamination of the stack interface caused by dust can reduce the unevenness of the characteristics of the thin film transistor.

As a continuous film-forming method, a multi-chamber sputtering apparatus having a plurality of film-forming chambers, a sputtering apparatus having a plurality of targets, or a pulsed laser deposition (PLD) apparatus may be used.

In the case of forming silicon oxide as the insulating film, silicon oxide (artificial quartz) or single crystal silicon can be used as a target and formed by a high-frequency sputtering method or a reactive sputtering method.

Note that here, a silicon oxide film is formed as the second-layer gate insulating film 102b in contact with the semiconductor film using a multi-chamber sputtering apparatus equipped with a single crystal silicon target and a semiconductor film target so as not to be exposed to the atmosphere. A semiconductor film and a silicon oxide film to be a channel protective layer are successively formed.

The semiconductor layer 103 is formed of an amorphous oxide semiconductor film. As the amorphous oxide semiconductor film, a composite oxide of an element selected from indium, gallium, aluminum, zinc, and tin can be used. For example, indium oxide (IZO) containing zinc oxide, an oxide (IGZO) containing In, Ga, and Zn, or an oxide (ZTO) composed of zinc oxide and tin oxide can be cited as examples.

As for the oxide composed of indium oxide, gallium oxide, and zinc oxide, the degree of freedom in the composition ratio of metal elements is high, and it is used as a semiconductor layer in a wide range of mixing ratios. For example, indium oxide containing 10% by weight of zinc oxide, a material in which indium oxide, gallium oxide, and zinc oxide are mixed in an equimolar ratio, and the abundance ratio of metal elements in the film are In:Ga:Zn=2.2 :2.2:1.0 oxide.

The oxide semiconductor film 133 used for the semiconductor layer 103 is formed to have a thickness of not less than 2 nm and not more than 200 nm, preferably not less than 20 nm and not more than 150 nm. Furthermore, when oxygen vacancies in the film increase, the carrier concentration increases and thin film transistor characteristics are impaired, so a composition that suppresses oxygen vacancies is employed.

The amorphous oxide semiconductor film 133 can be formed by a reactive sputtering method, a pulsed laser deposition method (PLD method), or a sol-gel method. Among the gas phase methods, the PLD method is suitable from the viewpoint of easy control of the composition of materials and the like, and the sputtering method as described above is suitable from the viewpoint of mass productivity. Here, as an example of a method of forming the semiconductor film 133 , a method using an oxide (IGZO) containing In, Ga, and Zn will be described.

Mix indium oxide (In ₂ O ₃ ), gallium oxide (Ga ₂ O ₃ ) and zinc oxide (ZnO) in an equimolar ratio, using a sintered target with a diameter of 8 inches, at a position 170mm away from the target The substrate was disposed, and DC (Direct Current) sputtering was performed at an output of 500 W to form the semiconductor film 133 . A semiconductor film with a thickness of 50 nm was formed under the condition that the pressure of the processing chamber was 0.4 Pa and the gas composition ratio was Ar/O ₂ 10/5 sccm. It is preferable to set the oxygen partial pressure at the time of film formation higher than the film formation conditions of a transparent conductive film such as indium tin oxide (ITO), and control the oxygen concentration of the film formation atmosphere to suppress oxygen vacancies. In addition, dust can be reduced by using a pulse direct current (DC) power supply, and the film thickness distribution of the semiconductor layer is also uniform, which is preferable.

Note that plasma treatment may also be performed on the semiconductor layer 103 . By performing plasma treatment, damage caused by etching of the semiconductor layer 103 can be restored. The plasma treatment is preferably performed under an O ₂ , N ₂ O atmosphere, or an oxygen-containing N ₂ , He, or Ar atmosphere. Alternatively, it may be performed under an atmosphere in which Cl ₂ or CF ₄ is added to the atmosphere described above. Note that plasma treatment is preferably performed without bias.

Note that in this embodiment mode, a multi-chamber sputtering apparatus including a target for an oxide semiconductor film and a target for single crystal silicon is used so as not to expose the second gate insulating film 102b formed in the previous step to A semiconductor film is formed thereon in an atmospheric manner. In the next step, an insulating film to be the channel protective layer 106 is formed on the semiconductor film so that the formed semiconductor film is not exposed to the atmosphere.

As shown in FIG. 2A , a channel protection layer 106 is formed using an insulating film in a region overlapping the channel formation region of the semiconductor layer 103 . As the insulating film used as the channel protective layer 106 , an inorganic material (silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, etc.) can be used. In addition, one of photosensitive or non-photosensitive organic materials (organic resin materials) (polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, etc.) can also be used. A film composed of one or more kinds, or a laminate of these films, etc. In addition, silicones can also be used.

The insulating film to be the channel protective layer 106 can be formed by a vapor phase growth method such as a plasma CVD method and a thermal CVD method, or a sputtering method. In addition, a coating method such as a wet spin coating method can also be used. Alternatively, the insulating film may be selectively formed by a droplet discharge method, a printing method (patterning method such as a screen printing method or an offset printing method), or the like.

Note that here, a multi-chamber sputtering apparatus including a single crystal silicon target and an oxide semiconductor film target is used to form a trench so that the oxide semiconductor film 133 formed in the preceding process is not exposed to the atmosphere. silicon oxide film for the protective layer 106.

Next, the silicon oxide film formed on the semiconductor film 133 is selectively etched using the resist mask formed using the second photomask in this embodiment to form a channel protective layer as shown in FIG. 2A. 106.

Next, the oxide semiconductor film 133 formed on the gate insulating film is etched using the resist mask formed using the third photomask in this embodiment mode to form the semiconductor layer 103 .

Note that as a method of etching the oxide (IGZO) film containing In, Ga, and Zn, a wet etching method can be utilized. An organic acid such as citric acid or oxalic acid can be used as an etchant. For example, as an oxide (IGZO) film containing In, Ga, and Zn with a thickness of 50 nm, etching can be performed for 150 seconds using ITO07N (manufactured by Kanto Chemical Co., Ltd.).

The pair of buffer layers 104a, 104b formed on the amorphous oxide semiconductor film is formed using an oxide semiconductor film containing In, Ga, and Zn having n-type conductivity.

In addition, an oxide semiconductor film containing In, Ga, and Zn having n-type conductivity may be doped with a different type of metal and used. Examples of the dopant include magnesium, aluminum, titanium, scandium, yttrium, zirconium, hafnium, boron, thallium, germanium, tin, lead, and the like. By making the buffer layer contain magnesium, aluminum, titanium, etc., the oxygen barrier effect and the like are exhibited, and by heat treatment after film formation, etc., the oxygen concentration of the semiconductor layer can be kept in an optimum range.

In one aspect of the present invention, it is preferable that the carrier concentration range (channel concentration range 1) of the semiconductor layer is lower than 1×10 ¹⁷ atoms/cm ³ (more preferably 1×10 ¹¹ atoms/cm ³ or more). ), and the carrier concentration range of the IGZO film suitable for the buffer layer (buffer layer concentration range 2) is above 1×10 ¹⁸ atoms/cm ³ (more preferably below 1×10 ²² atoms/cm ³ ). In addition, a second buffer layer serving as an n-layer having a carrier concentration higher than that of the semiconductor layer and lower than that of the buffer layer may be provided between the semiconductor layer and the buffer layer.

Because the carrier concentration of the buffer layers 104a and 104b is higher than that of the semiconductor layer composed of oxides (IGZO) containing In, Ga, and Zn, and their conductivity is superior, they are compatible with the source electrode layer and the drain electrode layer. Compared with the case where the layers 105a and 105b are directly bonded to the semiconductor layer 103, the contact resistance can be reduced. Furthermore, by sandwiching the buffer layers 104a and 104b between the junction interfaces between the source and drain electrode layers 105a and 105b and the semiconductor layer 103, the electric field concentrated at the junction interface can be relaxed.

Note that, as shown in FIG. 2B , patterning may be performed so that the buffer layer overlaps part of the channel protective layer 106 so that the buffer layers 104 a and 104 b reliably cover the semiconductor layer 103 .

The oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity used as the buffer layers 104a and 104b is preferably formed with a thickness of 2 nm or more and 100 nm or less.

The oxide semiconductor films containing In, Ga, and Zn having an n-type conductivity used as the buffer layers 104a and 104b can be formed by sputtering or pulsed laser deposition (PLD).

Note that here, the resist mask formed using the fourth photomask in this embodiment mode is used, and the n-type conductive layer containing In, Ga, and The oxide semiconductor film of Zn is dry-etched or wet-etched to form the buffer layers 104a and 104b.

The source electrode layer and the drain electrode layer 105a, 105b are made of a conductive film, and the same material as that of the gate electrode 101 can be used. In particular, however, the layer which is in contact with the buffer layers 104a, 104b is preferably a titanium film. As specific examples of the conductive film, a single titanium film, a laminated film of a titanium film and an aluminum film, or a three-layer structure in which a titanium film, an aluminum film and a titanium film are laminated in this order may also be used.

Here, as shown in FIG. 2C, a three-layer laminated film composed of a titanium film, an aluminum film, and a titanium film is formed on the buffer layers 104a, 104b and the channel protective layer by sputtering. Next, using the resist mask formed using the fifth photomask in this embodiment mode, the conductive film formed on the channel protective layer 106 is etched and separated, and then the source electrode is formed as shown in FIG. 2D layer and drain electrode layer 105a, 105b. Note that a hydrogen peroxide solution or heated hydrochloric acid may be used as an etchant to etch a conductive film of a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order.

Note that in this embodiment mode, since the formation of the buffer layers 104a, 104b and the formation of the source and drain electrode layers 105a, 105b are performed separately, it is easy to control the buffer layers 104a, 104b and the source and drain electrode layers 105a, 105a, and 105b respectively. The length of the overlapping portion in the end of 105b.

The characteristics of the thin film transistor using the oxide containing In, Ga, and Zn (IGZO) described in this embodiment mode as the semiconductor layer 103 are improved by heat-treating the formed semiconductor layer 103 . Specifically, on-current increases and unevenness in transistor characteristics decreases.

The heat treatment temperature of the semiconductor layer 103 is preferably in the range of 300°C to 400°C. Here, the treatment was performed at 350° C. for one hour. The heat treatment may be performed at any time as long as the semiconductor layer 103 is formed. For example, the heat treatment may be performed after the semiconductor layer 103 and the insulating film to become the channel protective layer 106 are successively formed, the heat treatment may be performed after the channel protective layer 106 is formed by patterning, or the buffer layers 104a, 104b may be formed after the heat treatment is performed. The oxide semiconductor film containing In, Ga, and Zn having n-type conductivity is then subjected to heat treatment. In addition, the heat treatment may be performed after forming the conductive film to be the source electrode layer and the drain electrode layer 105a, 105b, and the heat treatment may be performed after forming the sealing film of the thin film transistor. Furthermore, the thermal curing treatment of the planarization film formed on the thin film transistor may also be used as the heating treatment of the semiconductor layer 103 .

According to the above description, the amorphous oxide semiconductor layer 103, the channel protection layer 106, the buffer layers 104a, 104b, and the source and drain electrode layers 105a, 105b shown in FIGS. 1A and 1B are formed.

A thin film transistor according to one aspect of the present invention has a gate electrode, a gate insulating film, a semiconductor layer (an oxide semiconductor layer containing In, Ga, and Zn), a buffer layer, a channel protective layer, a source electrode layer, and a drain electrode layer. layer structure. By using a buffer layer having a carrier concentration higher than that of the semiconductor layer, parasitic capacitance can be suppressed while reducing the film thickness of the semiconductor layer.

Since the structure of the thin film transistor according to one embodiment of the present invention is a structure in which the channel protective layer 106 is provided, the region of the oxide semiconductor film on the opposite side from the surface contacting the gate insulating film 102b, that is, the so-called back surface can be protected. The channel is protected from damage during the process (reduction in film thickness, oxidation, etc. due to plasma and etchant during etching). Therefore, the reliability of the thin film transistor can be improved.

Note that the channel protective layer 106 can be said to be a channel stopper because it is used as an etching stopper in the etching process for forming the semiconductor layer 103 .

In addition, in this embodiment mode, since the ends of the source electrode layer and the drain electrode layer 105a, 105b are set back from the ends of the buffer layers 104a, 104b on the channel protective layer 106, and are located at positions separated from each other, it is possible to A leakage current and a short circuit generated between the source electrode layer and the drain electrode layer 105a, 105b are prevented.

Thus, by applying one aspect of the present invention, it is possible to obtain a thin film transistor in which photocurrent is small, parasitic capacitance is small, and an on/off ratio is high, and a thin film transistor having excellent dynamic characteristics can also be manufactured. Therefore, it is possible to provide a semiconductor device including a thin film transistor with high electrical characteristics and high reliability.

Embodiment 2

In this embodiment mode, a thin film transistor in which the buffer layer includes an oxide semiconductor including In, Ga, and Zn having an n-type conductivity in a structure different from that of Embodiment Mode 1 will be described with reference to FIGS. 3A1 to 3D . In addition, in this embodiment, the same reference numerals are used for the same parts as in Embodiment 1, and detailed description thereof will be omitted.

Through the same steps as in Embodiment Mode 1, as shown in FIG. 3A-1 , a channel protective layer 106 is formed using an insulating film in a region overlapping with the channel formation region of the semiconductor layer 103 . Note that in the etching process of the channel protective layer 106, the surface of the semiconductor layer 103 bonded to the buffer layer 104 may also be etched as shown in FIG. 3A-2. By etching the surface of the oxide semiconductor layer that is bonded to the buffer layer 104 , better bonding to the buffer layer 104 can be obtained.

In other words, the channel protective layer 106 is formed in a region overlapping the gate electrode 101 on the semiconductor film 133 through the same process as in Embodiment Mode 1. FIG. Note that, in the step of forming the channel protective layer 106, the surface of the semiconductor film 133 may be etched as shown in FIG. 3A-2. The surface of the semiconductor film 133 located in the opening of the channel protective layer 106 is etched, and as a result, the surface can be superior to the next-formed oxide semiconductor film 134 containing In, Ga, and Zn having an n-type conductivity and serving as a buffer layer. ground joint. Note that in this embodiment, the description is continued according to the manner of FIG. 3A-2.

In the present embodiment, as shown in FIG. 3B , an oxide semiconductor film 134 including In, Ga, and Zn having n-type conductivity is formed as a buffer layer. After forming the oxide semiconductor film 134 of n-type conductivity including In, Ga, and Zn as a buffer layer in the same manner as described in Embodiment Mode 1, the source electrode layer and The conductive film 105 of the drain electrode layers 105a, 105b.

The conductive film 105 is formed in the same manner as in the first embodiment. Here, as the conductive film 105, a three-layer laminated film is formed by a sputtering method. For example, a titanium film may be used as the source or drain electrode layer 105a1, 105b1, an aluminum film may be used as the source or drain electrode layer 105a2, 105b2, and a titanium film may be used as the source or drain electrode layer 105a3, 105b3.

In other words, the first conductive layer ( 105 a 1 , 105 b 1 ) made of titanium is formed using the conductive film 105 in which titanium used as the first conductive film, aluminum used as the second conductive film, and titanium used as the third conductive film are stacked. , the source electrode layer and the drain electrode layer (105a, 105b) of the second conductive layer (105a2, 105b2) made of aluminum, and the third conductive layer (105a3, 105b3) made of titanium.

Next, the conductive film 105 is etched using the resist mask formed using the fourth photomask in this embodiment mode.

First, source and drain electrode layers 105a1 and 105b1 are used as etching stopper layers, and are etched by wet etching to form source and drain electrode layers 105a2, 105a3, 105b2, and 105b3. The source electrode layer or drain electrode layer 105a1, 105b1, the buffer layers 104a, 104b, and the semiconductor layer 103 are formed by dry etching using the same mask as the wet etching described above. Therefore, as shown in FIG. 3D, the end of the source electrode layer 105a1 coincides with the end of the buffer layer 104a, and the end of the source electrode layer 105b1 coincides with the end of the buffer layer 104b. The ends of the source or drain electrode layers 105a2, 105a3 and the ends of the source or drain electrode layers 105b2, 105b3 are set back from the ends of the source or drain electrode layers 105a1, 105b1.

In other words, first, the titanium film as the third conductive film is etched to form the third conductive layer (105a3, 105b3), then, the titanium film as the first conductive film is used as an etching stopper film and the aluminum as the second conductive film is etched film to form the second conductive layer (105a2, 105b2). Furthermore, dry etching is performed on the titanium film as the first conductive film and the oxide semiconductor film 134 containing In, Ga, and Zn having n-type conductivity using the same resist mask as the wet etching described above to form the third conductive film. Conductive layers (105a3, 105b3) and buffer layers (104a, 104b). When the source electrode layer and the drain electrode layer (105a, 105b) are formed through this process, the ends of the first conductive layer (105a1, 105b1) coincide with the ends of the buffer layer (104a, 104b), while the second conductive layer The ends of (105a2, 105b2) and the third conductive layer (105a3, 105b3) recede from the ends of the first conductive layer (105a1, 105b1). Note that Figure 3D shows a cross-sectional view at this stage.

Like this, when the selection ratio of the conductive film used for the source electrode layer and the drain electrode layer, the buffer layer, and the semiconductor layer is low in the etching process, it is often necessary to stack the conductive film used as the etching stopper film and perform the etching process under other etching conditions. Second-rate.

In addition, heat treatment is performed on the formed semiconductor layer 103 in the same manner as in the first embodiment.

According to the present embodiment, since the buffer layers 104a, 104b and the source and drain electrode layers 105a, 105b are patterned using a resist mask formed using the same photomask, compared with Embodiment 1, it is possible to save The number of photomasks used. As a result, by unifying a plurality of processes into one process, the number of processes can be reduced, yield can be improved, and manufacturing time can be shortened.

Embodiment 3

In this embodiment mode, the structure of a thin film transistor including a buffer layer having a structure different from that of Embodiment Mode 1 and Embodiment Mode 2 will be described with reference to FIGS. 4A to 4D . In addition, in this embodiment, the same reference numerals are used for the same parts as in Embodiment 1, and detailed description thereof will be omitted.

Through the same process as in Embodiment Mode 2, as shown in FIG. 4A , a channel protective layer 106 is formed on an oxide (IGZO) semiconductor film 133 containing In, Ga, and Zn to be the semiconductor layer 103 .

In this embodiment mode, the semiconductor layer 103 is not formed by selectively etching the semiconductor film 133 here, but the buffer layers 104a and 104b are formed on the semiconductor film 133 by the same method as in the second embodiment mode. An oxide semiconductor film containing In, Ga, and Zn. Next, buffer layers 104a, 104b and semiconductor layer 103 are formed as shown in FIG. 4B using the resist mask formed using the third photomask in this embodiment mode.

The source and drain electrode layers 105a and 105b are made of conductive films and formed in the same manner as in the first embodiment. Here, on the buffer layers 104a, 104b and the channel protective layer 106, a three-layer laminated film consisting of a titanium film, an aluminum film, and a titanium film serving as a conductive film is formed by sputtering. Next, the conductive film is removed by etching using the resist mask formed using the fourth photomask in this embodiment, and the source and drain electrode layers 105 a and 105 b are formed as shown in FIG. 4D . FIG. 4D is a plan view, and FIG. 4C is a cross-sectional view taken along A1-A2 in FIG. 4D.

In addition, heat treatment is performed on the formed semiconductor layer 103 in the same manner as in the first embodiment.

According to this embodiment mode, since the buffer layers 104a, 104b and the semiconductor layer 103 are patterned at the same time, compared with the first embodiment mode, the number of photomasks used can be saved. As a result, by unifying a plurality of processes into one process, the number of processes can be reduced, yield can be improved, and manufacturing time can be shortened.

Embodiment 4

In this embodiment mode, a thin film transistor including a plurality of electrically connected gate electrodes and buffer layers will be described with reference to FIGS. 5A to 7B . FIG. 5A is a plan view, and FIG. 5B is a cross-sectional view taken along A1-A2 in FIG. 5A. FIG. 6A is a plan view, and FIG. 6B is a cross-sectional view taken along A1-A2 in FIG. 6A. FIG. 7A is a plan view, and FIG. 7B is a cross-sectional view taken along A1-A2 in FIG. 7A. In addition, in this embodiment, the same reference numerals are used for the same parts as in Embodiment 1, and detailed description thereof will be omitted.

Note that although a structure connecting two channel formation regions is used in this embodiment mode, it is not limited to this and may use a so-called multi-gate structure (including a series connection) such as a triple gate structure connecting three channel formation regions. structure with more than two channel formation regions).

As the method of connecting two channel formation regions of the thin film transistor of this embodiment, there are the following three methods: the method of connecting the two channel formation regions using only the buffer layer 104c (FIGS. 5A and 5B); using the buffer layer 104c and The manner in which the conductive layer 105c connects the two channel formation regions ( FIGS. 6A and 6B ); and the manner in which the two channel formation regions are connected using the semiconductor layer 103 , the buffer layer 104c and the conductive layer 105c ( FIGS. 7A and 7B ). These thin film transistors can be formed by the same method as in the first embodiment by changing the part of the photomask of the equivalent layer sandwiched between the two first gate electrodes 101a and the second gate electrode 101b.

This multi-gate structure is extremely effective in reducing the off-current value.

Embodiment 5

In this embodiment mode, the structure of a thin film transistor including a buffer layer having a structure different from that of Embodiment Modes 1 to 4 described above will be described with reference to FIG. 8 . Note that, since parts other than the buffer layer of the thin film transistor of this embodiment can be formed in the same manner as described in Embodiment Mode 1, detailed descriptions other than the buffer layer will be omitted.

The buffer layer of this embodiment is comprised of two layers of a 1st buffer layer and a 2nd buffer layer. The buffer layers 104a, 104b in contact with the source electrode or the drain electrode are the first buffer layers, and the second buffer layers sandwiched by the first buffer layers 104a, 104b and the semiconductor layer 103 are respectively the second buffer layers 114a, 114b.

In other words, the buffer layer of this embodiment is composed of the first buffer layer 104a in contact with one of the source electrode and the drain electrode, the first buffer layer 104b in contact with the other of the source electrode and the drain electrode, and the first buffer layer 104a contacted by the first buffer layer 104a. The second buffer layer 114 a sandwiched between the semiconductor layer 103 and the second buffer layer 114 b sandwiched between the first buffer layer 104 b and the semiconductor layer 103 are formed.

Both the first buffer layers 104a, 104b and the second buffer layers 114a, 114b are formed of an oxide semiconductor containing In, Ga, and Zn having n-type conductivity.

In addition, an oxide semiconductor containing In, Ga, and Zn having n-type conductivity may be doped with a different type of metal and used. Examples of the dopant include magnesium, aluminum, titanium, scandium, yttrium, zirconium, hafnium, boron, thallium, germanium, tin, lead, and the like. The carrier concentration in the buffer layer can be increased by doping.

As an example of the film-forming method of the buffer layer, a co-sputtering method in which a target material containing an oxide (IGZO) containing In, Ga, and Zn and a target material containing an oxide (IGZO) containing In, Ga, and Zn and a dopant containing a conductive type imparting n-type are simultaneously sputtered and sintered can also be used. The target of the compound of dopant. By the co-sputtering method, a mixed layer of an oxide (IGZO) containing In, Ga, and Zn and a compound containing a dopant can be formed, and the first buffer layers 104a, 104b and the second buffer layers 114a, 114a, 114b.

The carrier concentration of the first buffer layer 104a, 104b and the second buffer layer 114a, 114b is higher than that of the semiconductor layer 103 composed of oxide (IGZO) containing In, Ga, and Zn, and its conductivity is superior, and the first buffer layer The layer 104a, 104b is selected to have a higher carrier concentration than the second buffer layer 114a, 114b. That is, the buffer layers 104a, 104b function as n ⁺ layers, while the second buffer layer (buffer layers 114a, 114b ⁾ functions as an n- layer.

Preferably, the carrier concentration range (channel concentration range 1) of the semiconductor layer 103 is lower than 1×10 ¹⁷ atoms/cm ³ (more preferably above 1×10 ¹¹ atoms/cm ³ ), which is suitable for n The carrier concentration range (buffer layer concentration range 2) of the IGZO film in the buffer layers 104a and 104b of the ⁺ layer is 1×10 ¹⁸ atoms/cm ³ or more (more preferably 1×10 ²² atoms/cm ³ or less).

The contact resistance between the semiconductor layer 103 and the source and drain electrode layers 105a and 105b can be reduced by making the carrier concentration have a gradient increasing from the semiconductor layer 103 to the source and drain electrode layers 105a and 105b.

Furthermore, by sandwiching the buffer layer having a gradient in which the carrier concentration increases from the semiconductor layer 103 to the source and drain electrode layers 105a, 105b at the junction interface, the electric field concentrated at the junction interface can be relaxed.

The thin-film transistor having the stacked buffer layer according to one embodiment of the present invention has a low off-state current, and a semiconductor device including such a thin-film transistor can be provided with high electrical characteristics and high reliability.

This embodiment mode can be implemented in combination with other embodiment modes as appropriate.

Embodiment 6

Here, an example of manufacturing an inverted staggered thin film transistor formed continuously so that at least the stack of the gate insulating film and the oxide semiconductor film is not exposed to the atmosphere will be described below. Here, the steps up to the continuous film formation are shown, and the thin film transistor may be manufactured according to any one of Embodiments 1 to 5 in the subsequent steps.

When continuous film formation is performed without exposure to the atmosphere, it is preferable to use a multi-chamber manufacturing apparatus as shown in FIG. 9 .

In the central part of the manufacturing apparatus, a transfer chamber 80 equipped with a transfer mechanism (typically a transfer machine 81) for transferring substrates is provided, and a cassette chamber (cassette chamber) 82 is connected to the transfer chamber 80, in which a plurality of A cassette case for substrates in or out of a transfer chamber.

In addition, a plurality of process chambers are coupled to the transfer chamber through gate valves 84 to 88, respectively. Here, an example in which five processing chambers are connected to the transfer chamber 80 whose top view shape is hexagonal is shown. Note that the number of process chambers that can be connected can be changed by changing the top view shape of the transfer chamber. For example, three process chambers can be coupled when changed to a quadrangle, and seven process chambers can be coupled when changed to an octagon.

At least one of the five processing chambers is a sputtering processing chamber where sputtering is performed. The sputtering processing chamber is provided with at least a sputtering target, a power applying mechanism and a gas introducing unit for sputtering the target, a substrate holder holding a substrate at a predetermined position, and the like in its interior. In addition, a pressure control unit for controlling the pressure in the sputtering processing chamber is provided in the sputtering processing chamber so as to put the sputtering processing chamber in a depressurized state.

The sputtering method includes an RF sputtering method using a high-frequency power source as a power source for sputtering, a DC sputtering method, and a pulsed DC sputtering method in which a bias voltage is pulsed. The RF sputtering method is mainly used in the case of forming an insulating film, and the DC sputtering method is mainly used in the case of forming a metal film.

In addition, there is a multi-source sputtering apparatus (multi-source sputtering apparatus) capable of setting a plurality of targets of different materials. The multi-element sputtering device can form layers of different material films in the same processing chamber or simultaneously discharge a plurality of materials in the same processing chamber to form a film.

In addition, there are sputtering devices using the magnetron sputtering method equipped with a magnet mechanism in the processing chamber, and sputtering devices using the ECR sputtering method that uses microwaves instead of glow discharge to generate of plasma.

In the sputtering treatment chamber, the above-mentioned various sputtering methods are suitably used. In addition, as a film forming method, there are reactive sputtering methods in which a target material and sputtering gas components are chemically reacted to form a thin film of their compounds during film formation, and a bias sputtering method in which a voltage is also applied to a substrate during film formation. pressure sputtering method.

In addition, among the five processing chambers, one of the other processing chambers is a heat processing chamber for preheating the substrate before sputtering, etc., a cooling processing chamber for cooling the substrate after sputtering, or a processing chamber for plasma processing room.

Next, an example of the operation of the manufacturing apparatus will be described.

A substrate cassette accommodating a substrate 94 with its film-formed surface facing downward is installed in the cassette chamber 82, and the cassette chamber is depressurized by a vacuum exhaust unit provided in the cassette chamber 82. Note that the insides of the respective processing chambers and the transfer chamber 80 are decompressed in advance using vacuum evacuation units respectively provided therein. Through the above steps, it is possible to maintain a clean state without being exposed to the atmosphere when the substrate is transferred between the processing chambers.

Note that at least a gate electrode is provided in advance on the substrate 94 whose film-forming surface faces downward. For example, a base insulating film such as a silicon nitride film or a silicon oxynitride film obtained by plasma CVD may be provided between the substrate and the gate electrode. In the case where a glass substrate containing an alkali metal is used as the substrate 94, the base insulating film has a function of suppressing changes in the electrical characteristics of the TFT due to the intrusion of mobile ions such as sodium from the substrate into the semiconductor region thereon. Phenomenon.

Here, a substrate in which a first-layer gate insulating film is formed by forming a silicon nitride film covering the gate electrode by a plasma CVD method is used. The silicon nitride film formed by the plasma CVD method is dense, and by using it as the first gate insulating film, the generation of pinholes and the like can be suppressed. Note that although an example in which the gate insulating film is stacked is shown here, it is not limited thereto and a single layer or a stack of three or more layers may be employed.

Next, the gate valve 83 is opened and the first substrate 94 is withdrawn from the cassette using the transfer mechanism 81, the gate valve 84 is opened and the first substrate 94 is transferred into the first processing chamber 89, and the gate valve 84 is closed. In the first processing chamber 89 , the substrate is heated with a heater or lamp heating to remove moisture or the like attached to the substrate 94 . In particular, when the gate insulating film contains moisture, the electrical characteristics of the TFT may change, so heating before sputtering is effective. Note that this heat treatment is unnecessary when moisture has been sufficiently removed in the stage of mounting the substrate in the cassette chamber 82 .

In addition, a plasma processing unit may also be provided in the first processing chamber 89 to perform plasma processing on the surface of the first gate insulating film. In addition, a heating unit may also be provided in the cassette chamber 82 and be heated in the cassette chamber 82 to remove moisture.

Next, the gate valve 84 is opened to transfer the substrate to the transfer chamber 80 by the transfer machine 81 , the gate valve 85 is opened to transfer the substrate to the second processing chamber 90 , and the gate valve 85 is closed.

Here, the second processing chamber 90 is a sputtering processing chamber using RF magnetron sputtering. In the second processing chamber 90 , a silicon oxide film (SiO _x film (x>0)) serving as a second-layer gate insulating film is formed. As the second gate insulating film, besides the silicon oxide film, an aluminum oxide film (Al ₂ O ₃ film), a magnesium oxide film (MgO _x film (x>0)), an aluminum nitride film (AlN _x film (x>0)), yttrium oxide film (YO _x film (x>0)), etc.

In addition, a small amount of halogen elements such as fluorine and chlorine may be added to the second gate insulating film to immobilize mobile ions such as sodium. As its method, a gas containing a halogen element is introduced into a processing chamber to perform sputtering. However, in the case of introducing a gas containing halogen elements, the exhaust unit of the treatment chamber needs to be provided with a detoxification device. It is preferable to set the concentration of the halogen element contained in the gate insulating film so that the concentration peak obtained by analysis using SIMS (Secondary Ion Mass Spectrometer) is 1×10 ¹⁵ cm ⁻³ or more and 1×10 ²⁰ cm In the range below ^-3 .

In the case of obtaining a SiO _x film (x>0), the following methods can be used: using artificial quartz as the target material and using a rare gas, typically argon sputtering method; or using single crystal silicon as the target material and making it Reactive sputtering method to obtain SiO _x film (x>0) by chemical reaction with oxygen gas. Here, in order to make the SiO _x film (x>0) contain a lot of oxygen, artificial quartz is used as the target material, and it is carried out in an atmosphere of only oxygen, or in an atmosphere with 90% or more of oxygen and 10% or less of Ar. sputtering to form a _SiOx film with excess oxygen (x>0).

After the _SiOx film (x>0) is formed, the gate valve 85 is opened without contacting the atmosphere and the substrate is transferred to the transfer chamber 80 by the transfer machine 81, the gate valve 86 is opened and the substrate is transferred to the third processing chamber 91, And the gate valve 86 is closed.

Here, the third processing chamber 91 is a sputtering processing chamber using a DC magnetron sputtering method. In the third processing chamber 91 , a metal oxide layer (IGZO film) serving as a semiconductor layer is formed. The metal oxide layer can be formed using an oxide semiconductor target including indium (In), gallium (Ga), and zinc (Zn) under a rare gas atmosphere or an oxygen atmosphere. Here, in order to make the IGZO film contain a very large amount of oxygen, an oxide semiconductor containing In, Ga, and Zn is used as a target, and it is used in an atmosphere of only oxygen, or in an atmosphere where oxygen is 90% or more and Ar is 10% or less. Sputtering by a pulsed DC sputtering method was performed under an atmosphere to form an IGZO film with excess oxygen.

Like this, by successively forming a SiO _x film (x>0) with excess oxygen and an IGZO film with excess oxygen without contacting the atmosphere, since they are both films with excess oxygen, it is possible to make them The state of the interface between them is stable, and the reliability of the TFT is improved. When the substrate is exposed to the atmosphere before the IGZO film is formed, moisture, etc. adheres and adversely affects the interface state, so there is concern about non-uniform threshold value, degradation of electrical characteristics, and phenomenon of TFT in a normally-on state. Moisture is a hydrogen compound, and the hydrogen compound present at the interface can be eliminated by continuous film formation without contact with the atmosphere. Therefore, through continuous formation, it is possible to reduce unevenness in threshold value, prevent degradation of electrical characteristics, and reduce shift of TFT to the normally-on state side, and it is preferable to eliminate such shift.

In addition, by setting both the artificial quartz target material and the oxide semiconductor target material containing In, Ga, and Zn in the sputtering processing chamber of the second processing chamber 90, and using a shutter (shutter) to stack sequentially, continuous processing is performed. Film formation can also be stacked in the same processing chamber. A baffle is provided between the target and the substrate, and the baffle of the target to be film-formed is opened, while the baffle of the target not to be film-formed is closed. The advantage of stacking in the same processing chamber is that the number of processing chambers used can be reduced and particles, etc. can be prevented from adhering to the substrate when the substrate is transferred between different processing chambers.

Next, the gate valve 86 is opened to transfer the substrate to the transfer chamber 80 by the transfer mechanism 81 without being exposed to the atmosphere, the gate valve 87 is opened to transfer the substrate into the fourth processing chamber 92 , and the gate valve 87 is closed.

Here, the fourth processing chamber 92 is a sputtering processing chamber using the RF magnetron sputtering method. In the fourth processing chamber 92 , a silicon oxide film (SiO _x film (x>0)) serving as an insulating film to become a channel protective layer is formed. In addition, as the channel protective layer, besides the silicon oxide film, an aluminum oxide film (Al ₂ O ₃ film), a magnesium oxide film (MgO _x film (x>0)), an aluminum nitride film (AlN _x film (x>0)), yttrium oxide film (YO _x film (x>0)), etc.

In addition, a small amount of halogen elements such as fluorine and chlorine may be added to the channel protective layer to immobilize mobile ions such as sodium. As its method, a gas containing a halogen element is introduced into a processing chamber to perform sputtering. However, in the case of introducing a gas containing halogen elements, the exhaust unit of the treatment chamber needs to be provided with a detoxification device. It is preferable to set the concentration of the halogen element contained in the channel protective layer so that the concentration peak obtained by analysis using SIMS (Secondary Ion Mass Spectrometer) is 1×10 ¹⁵ cm ⁻³ or more and 1×10 ²⁰ cm In the range below ^-3 .

In the case of obtaining a SiO _x film (x>0) used as a channel protective layer, the following methods can be used: a sputtering method using artificial quartz as a target and using a rare gas, typically argon; or as a target A reactive sputtering method that uses single crystal silicon and chemically reacts it with oxygen gas to obtain a SiO _x film (x>0). Here, in order to make the SiO _x film (x>0) contain a lot of oxygen, artificial quartz is used as the target material, and it is carried out in an atmosphere of only oxygen, or in an atmosphere with 90% or more of oxygen and 10% or less of Ar. sputtering to form a _SiOx film with excess oxygen (x>0).

Like this, by successively forming the SiO _x film (x>0) with excess oxygen, the IGZO film with excess oxygen, and the channel protective layer with excess oxygen without contacting the atmosphere, all three layers have excess Oxygen film, so its interface state is more stable, and can improve the reliability of TFT. When the substrate is exposed to the atmosphere before and after the formation of the IGZO film, moisture, etc. will adhere and have a bad influence on the interface state, so there are concerns about non-uniform threshold value, degradation of electrical characteristics, and phenomenon of TFT in a normally-on state. Moisture is a hydrogen compound, and the hydrogen compound existing at the interface of the IGZO film can be eliminated by performing continuous film formation without exposure to the atmosphere. Thus, by continuously forming three layers, it is possible to reduce unevenness in threshold value, prevent deterioration of electrical characteristics, reduce shift of TFT to the normally-on side, and preferably remove such shift.

In addition, in the sputtering processing chamber of the second processing chamber 90, both the artificial quartz target and the oxide semiconductor target containing In, Ga, and Zn may be provided, and three sputtering targets may be successively formed by sequentially laminating them using a shutter. Layers are stacked in the same processing chamber. The advantages of stacking in the same process chamber are that the number of process chambers used can be reduced and particles, etc., can be prevented from adhering to the substrate when the substrate is transferred between different process chambers.

After the film-forming process is performed on the substrates in the cassette by repeating the above steps, and the processing of multiple substrates is completed, the vacuum of the cassette chamber is released to the atmosphere and the substrates and cassettes are taken out.

Next, in order to pattern the IGZO film, the channel protective layer is selectively etched and the IGZO film is selectively etched. The formation may be performed by dry etching or wet etching, or the IGZO film may be selectively etched by performing two etchings. In this stage, in the region where the IGZO film is removed, the surface of the gate insulating film is exposed.

Next, the channel protective layer is etched so that only the portion overlapping the gate electrode, that is, the portion overlapping the IGZO film forming the channel formation region remains. As the etching of the channel protective layer here, conditions are employed in which the etching rate is sufficiently different from the etching rate of the IGZO film. When the etching rate of the channel protective layer is not sufficiently different, the surface of the IGZO film is partially etched to form a region whose film thickness is thinner than that of the region overlapping the channel protective layer. Note that when the material of the channel protective layer and the material of the gate insulating film are the same, the gate insulating film is also etched by this etching. Therefore, it is preferable to use a material different from that of the gate insulating film for the channel protective layer in order to prevent the gate insulating film from being etched. In this embodiment mode, the gate insulating film is two layers, and the upper layer is a _SiOx film (x>0), so there is a possibility of being removed, but the lower layer is a silicon nitride film, so it is used as an etching stopper film.

Next, the substrate was mounted again in the cassette chamber of the multi-chamber manufacturing apparatus shown in FIG. 9 .

Next, after putting the cassette chamber in a depressurized state, the substrate is transferred to the transfer chamber 80 and transferred to the third processing chamber 91 . Here, sputtering by a pulsed DC sputtering method is performed in an atmosphere of only a rare gas to form an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity as a buffer layer. The oxygen concentration in the n-type conductivity-type oxide semiconductor film containing In, Ga, and Zn is lower than that in the IGZO film with excess oxygen. In addition, as an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity, it is preferable to set its carrier concentration higher than that of an IGZO film having an excess of oxygen, and as a target , a target in which the oxide semiconductor containing In, Ga, and Zn also contains Mg, Al, and Ti can also be used. Mg, Al, and Ti are materials that are prone to oxidation reactions. By including this material in an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type, the barrier effect of oxygen and the like can be exhibited, and even if heat treatment or the like is performed after film formation, the oxygen concentration of the semiconductor layer can be reduced. Stay within the most suitable range. The oxide semiconductor film containing In, Ga, and Zn having n-type conductivity is used as a source region or a drain region.

Next, the gate valve 87 is opened and the substrate is transferred to the transfer chamber 80 by the transfer mechanism 81 without exposure to the atmosphere, the gate valve 88 is opened and the substrate is transferred to the fifth processing chamber 93, and the gate valve 88 is closed.

Here, the fifth processing chamber 93 is a sputtering processing chamber using a DC magnetron sputtering method. In the fifth processing chamber 93, a metal multilayer film to be a source electrode and a drain electrode is formed. In the sputtering treatment chamber of the fifth treatment chamber 93 , both the titanium target and the aluminum target were set, and they were stacked sequentially using shutters to perform continuous film formation and were stacked in the same treatment chamber. Here, an aluminum film is laminated on a titanium film, and a titanium film is laminated on an aluminum film.

In this way, by continuously forming an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity and a metal multilayer film without exposure to the atmosphere, it is possible to form an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity. A high-quality interface state is realized between the oxide semiconductor film and the metal multilayer film, and the contact resistance is reduced.

After the above steps are repeated to form a film on the substrates in the cassette and the processing of multiple substrates is completed, the vacuum of the cassette chamber is released to the atmosphere and the substrates and cassettes are taken out.

Next, the metal multilayer film is selectively etched to form a source electrode and a drain electrode. Furthermore, etching is performed using the source electrode and the drain electrode as a mask, and the oxide semiconductor film having n-type conductivity including In, Ga, and Zn is selectively etched to form a source region or a drain region. The channel protective layer functions as an etching stopper when etching an oxide semiconductor film containing In, Ga, and Zn having n-type conductivity.

Through the above steps, an inverted staggered thin film transistor having a channel protection layer can be manufactured.

In addition, an example in which an IGZO film having excess oxygen and an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type were formed in the same process chamber was shown in the above-mentioned process, but there is no particular limitation. Film formation may be performed separately in different processing chambers.

Although a multi-chamber manufacturing apparatus is described here as an example, an in-line manufacturing apparatus in which sputtering chambers are connected in series may be used to perform continuous film formation without exposure to the atmosphere.

In addition, in the apparatus shown in FIG. 9, a so-called downward-type processing chamber in which the film-forming surface of the substrate is installed facing downward is used, but a vertically-installed processing chamber in which the substrate is erected vertically may also be used. . The processing chamber of the vertical installation method has an advantage that its footprint is smaller than that of the processing chamber of the downward method, and it is effective when using a large-area substrate that bends due to its own weight.

Embodiment 7

In this embodiment mode, an example in which at least a part of the driver circuit and a thin film transistor disposed in the pixel portion are manufactured on the same substrate will be described below.

A thin film transistor arranged in a pixel portion is formed according to Embodiment Mode 1 to Embodiment Mode 5. FIG. In addition, since the thin film transistors shown in Embodiment Modes 1 to 5 are n-channel TFTs, a part of the driving circuit that can be configured using n-channel TFTs in the driving circuit is formed on the same surface as the thin film transistor in the pixel portion. on a substrate.

FIG. 10A shows an example of a block diagram of an active matrix liquid crystal display device. The display device shown in FIG. 10A includes, on a substrate 5300: a pixel portion 5301 having a plurality of pixels including display elements; a scanning line driver circuit 5302 for selecting each pixel; and a device for controlling the input of a video signal to the selected pixel. Signal line driving circuit 5303.

The pixel portion 5301 is connected to the signal line driving circuit 5303 by a plurality of signal lines S1 to Sm (not shown) extending from the signal line driving circuit 5303 in the column direction, and is connected to the signal line driving circuit 5303 by extending in the row direction from the scanning line driving circuit 5302 . A plurality of scanning lines G1 to Gn (not shown) connected to the scanning line driving circuit 5302 has a plurality of pixels (not shown) arranged in a matrix corresponding to the signal lines S1 to Sm and the scanning lines G1 to Gn. Furthermore, each pixel is connected to a signal line Sj (any one of the signal lines S1 to Sm) and a scanning line Gi (any one of the scanning lines G1 to Gn).

In addition, the thin film transistors described in Embodiment Modes 1 to 5 are n-channel TFTs, and a signal line driver circuit composed of n-channel TFTs is shown with reference to FIG. 11 .

The signal line driving circuit shown in FIG. 11 includes: a driver IC 5601 ; switch groups 5602_1 to 5602_M; first wiring 5611 ; second wiring 5612 ; third wiring 5613 ; The switch groups 5602_1 to 5602_M respectively include a first thin film transistor 5603a, a second thin film transistor 5603b and a third thin film transistor 5603c.

The driver IC 5601 is connected to a first wiring 5611 , a second wiring 5612 , a third wiring 5613 , and wirings 5621_1 to 5621_M. Also, the switch groups 5602_1 to 5602_M are respectively connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621_1 to 5621_M respectively corresponding to the switch groups 5602_1 to 5602_M. Also, the wirings 5621_1 to 5621_M are connected to three signal lines through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c, respectively. For example, the wiring 5621_J (any one of the wirings 5621_1 to 5621_M) in the J-th column is connected to the signal lines Sj-1, Signal line Sj, signal line Sj+1.

Note that signals are respectively input to the first wiring 5611 , the second wiring 5612 , and the third wiring 5613 .

Note that the driver IC 5601 is preferably formed on a single crystal substrate. Furthermore, the switch groups 5602_1 to 5602_M are preferably formed on the same substrate as the pixel portions described in Embodiment Modes 1 to 5. Therefore, it is preferable to connect the driver IC 5601 and the switch groups 5602_1 to 5602_M through FPC or the like.

Next, the operation of the signal line driving circuit shown in FIG. 11 will be described with reference to the timing chart of FIG. 12 . Note that FIG. 12 shows a timing chart when the scanning line Gi of the i-th row is selected. Moreover, the selection period of the i-th scan line Gi is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, the signal line driver circuit in FIG. 11 performs the same operation as that in FIG. 12 even when a scanning line in another row is selected.

Note that the timing diagram of FIG. 12 shows that the J-th column wiring 5621_J is connected to the signal line Sj-1, the signal line Sj, and the signal line Sj+1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. Condition.

Note that the timing diagram in FIG. 12 shows the timing when the i-th scan line Gi is selected, the timing 5703a of turning on/off the first thin film transistor 5603a, the timing 5703b of turning on/off the second thin film transistor 5603b, and the timing 5703b of turning on/off the third thin film transistor 5603a. On/off timing 5703c of the thin film transistor 5603c and a signal 5721_J input to the J-th column wiring 5621_J.

Note that in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, different video signals are input to the wiring 5621_1 to the wiring 5621_M, respectively. For example, the video signal input to the wiring 5621_J in the first sub-selection period T1 is input to the signal line Sj-1, the video signal input to the wiring 5621_J in the second sub-selection period T2 is input to the signal line Sj, and in the third sub-selection period T2, the video signal input to the wiring 5621_J is input to the signal line Sj-1. The video signal input to the wiring 5621_J in the selection period T3 is input to the signal line Sj+1. Furthermore, the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 are Data_j−1, Data_j, and Data_j+1, respectively.

As shown in FIG. 12, in the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data_j-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, Data_j input to the wiring 5621_J is input to the signal line Sj through the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 through the third thin film transistor 5603c.

Accordingly, the signal line driver circuit in FIG. 11 can input video signals from one wiring 5621 to three signal lines in one gate selection period by dividing one gate selection period into three. Therefore, in the signal line driver circuit of FIG. 11 , the number of connections between the substrate on which the driver IC 5601 is formed and the substrate on which the pixel portion is formed can be set to about 1/3 of the number of signal lines. By reducing the number of connections to approximately 1/3, the reliability, yield, and the like of the signal line drive circuit shown in FIG. 11 can be improved.

In addition, as shown in FIG. 11, as long as one gate selection period can be divided into a plurality of sub-selection periods, and a video signal can be input to a plurality of signal lines from a certain wiring in each of the sub-selection periods, the thin film transistor is not limited. configuration, quantity and driving method etc.

For example, when a video signal is input to three or more signal lines from one line in each of three or more sub-selection periods, it is sufficient to add a thin film transistor and a line for controlling the thin film transistor. However, when one gate selection period is divided into four or more sub-selection periods, the sub-selection period is shortened. Therefore, it is preferable to divide one gate selection period into two or three sub-selection periods.

As another example, as shown in the timing chart of FIG. 13 , one selection period may be divided into a precharge period Tp, a first sub-selection period T1 , a second sub-selection period T2 , and a third sub-selection period T3 . Furthermore, the timing diagram in FIG. 13 shows the timing of selecting the scan line Gi in the i-th row, the timing 5803a of turning on/off the first thin film transistor 5603a, the timing 5803b of turning on/off the second thin film transistor 5603b, the timing of the third thin film transistor 5603b turning on/off, On/off timing 5803c of the thin film transistor 5603c and a signal 5821_J input to the J-th column wiring 5621_J. As shown in FIG. 13 , during the pre-charging period Tp, the first thin film transistor 5603a, the second thin film transistor 5603b and the third thin film transistor 5603c are turned on. At this time, the precharge voltage Vp input to the wiring 5621_J is input to the signal line Sj−1, signal line Sj, and signal line Sj+1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c, respectively. In the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data_j-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, Data_j input to the wiring 5621_J is input to the signal line Sj through the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 through the third thin film transistor 5603c.

Accordingly, since the signal line driving circuit of FIG. 11 to which the timing chart of FIG. 13 is applied can precharge the signal line by providing the precharge selection period before the subselection period, it is possible to write video signals to pixels at high speed. . Note that in FIG. 13 , the same reference numerals are used to denote the same parts as in FIG. 12 , and detailed explanations for the same parts or parts having the same functions are omitted.

In addition, the configuration of the scanning line driving circuit will be described. The scanning line driving circuit includes a shift register and a buffer. In addition, depending on circumstances, a level shifter may also be included. In the scanning line driving circuit, a selection signal is generated by inputting a clock signal (CLK) and a start pulse signal (SP) to the shift register. The generated selection signal is buffered and amplified in the buffer, and supplied to the corresponding scan line. The scan lines are connected to the gate electrodes of the transistors of the pixels on one line. Furthermore, since it is necessary to simultaneously turn on the transistors of pixels on one line, a buffer capable of generating a large current is used.

One embodiment of a shift register used as part of the scanning line driver circuit will be described with reference to FIGS. 14 and 15 .

Fig. 14 shows the circuit structure of the shift register. The shift register shown in FIG. 14 is constituted by a plurality of flip-flops 5701_i (any one of flip-flops 5701_1 to 5701_n). In addition, the first clock signal, the second clock signal, the start pulse signal, and the reset signal are input to operate.

The connection relation of the shift register in Fig. 14 will be described. In the i-th stage flip-flop 5701_i (any one of the flip-flops 5701_1 to 5701_n) of the shift register in FIG. 14 , the first wiring 5501 shown in FIG. The second wiring 5502 is connected to the seventh wiring 5717_i+1, the third wiring 5503 shown in FIG. 15 is connected to the seventh wiring 5717_i, and the sixth wiring 5506 shown in FIG. 15 is connected to the fifth wiring 5715.

Furthermore, the fourth wiring 5504 shown in FIG. 15 is connected to the second wiring 5712 in odd-numbered stages of flip-flops, and to the third wiring 5713 in even-numbered stages of flip-flops, and the fifth wiring 5505 shown in FIG. 15 is connected to to the fourth wiring 5714 .

However, the first wiring 5501 shown in FIG. 15 of the first-stage flip-flop 5701_1 is connected to the first wiring 5711 , and the second wiring 5502 shown in FIG. 15 of the n-th stage flip-flop 5701_n is connected to the sixth wiring 5716 .

In addition, the first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 5716 may also be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. Furthermore, the fourth wiring 5714 and the fifth wiring 5715 may also be referred to as a first power supply line and a second power supply line, respectively.

Next, FIG. 15 shows a detailed structure of the flip-flop shown in FIG. 14 . The trigger shown in FIG. 15 includes a first thin film transistor 5571, a second thin film transistor 5572, a third thin film transistor 5573, a fourth thin film transistor 5574, a fifth thin film transistor 5575, a sixth thin film transistor 5576, a seventh thin film transistor 5577 and The eighth thin film transistor 5578. In addition, the first thin film transistor 5571, the second thin film transistor 5572, the third thin film transistor 5573, the fourth thin film transistor 5574, the fifth thin film transistor 5575, the sixth thin film transistor 5576, the seventh thin film transistor 5577 and the eighth thin film transistor 5578 are n-channel type transistors, and they become conductive when the voltage between the gate/source (Vgs) exceeds the threshold voltage (Vth).

Next, the connection structure of the flip-flop shown in FIG. 14 is shown below.

The first electrode (one of the source electrode and the drain electrode) of the first thin film transistor 5571 is connected to the fourth wiring 5504, and the second electrode (the other one of the source electrode and the drain electrode) of the first thin film transistor 5571 is connected to the fourth wiring 5504. Three wires 5503.

The first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506 , and the second electrode of the second thin film transistor 5572 is connected to the third wiring 5503 .

The first electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505, the second electrode of the third thin film transistor 5573 is connected to the gate electrode of the second thin film transistor 5572, and the gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505.

The first electrode of the fourth thin film transistor 5574 is connected to the sixth wiring 5506, the second electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the second thin film transistor 5572, and the gate electrode of the fourth thin film transistor 5574 is connected to the first thin film transistor 5574. Gate electrode of transistor 5571.

The first electrode of the fifth thin film transistor 5575 is connected to the fifth wiring 5505, the second electrode of the fifth thin film transistor 5575 is connected to the gate electrode of the first thin film transistor 5571, and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501.

The first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506, the second electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the first thin film transistor 5571, and the gate electrode of the sixth thin film transistor 5576 is connected to the second thin film transistor 5576. Gate electrode of transistor 5572.

The first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506, the second electrode of the seventh thin film transistor 5577 is connected to the gate electrode of the first thin film transistor 5571, and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502. The first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506, the second electrode of the eighth thin film transistor 5578 is connected to the gate electrode of the second thin film transistor 5572, and the gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 5501.

Note that the gate electrode of the first thin film transistor 5571, the gate electrode of the fourth thin film transistor 5574, the second electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor 5576, and the second electrode of the seventh thin film transistor 5577 The connecting part of is as node 5543. Furthermore, the gate electrode of the second thin film transistor 5572, the second electrode of the third thin film transistor 5573, the second electrode of the fourth thin film transistor 5574, the gate electrode of the sixth thin film transistor 5576, and the second electrode of the eighth thin film transistor 5578 The connected portion of the electrodes serves as a node 5544 .

In addition, the first wiring 5501 , the second wiring 5502 , the third wiring 5503 , and the fourth wiring 5504 may also be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. Furthermore, the fifth wiring 5505 and the sixth wiring 5506 may also be referred to as a first power supply line and a second power supply line, respectively.

In addition, the signal line driver circuit and the scan line driver circuit may be manufactured using only the n-channel TFTs described in the first to fifth embodiments. Since the transistor mobility of the n-channel TFT shown in Embodiment Modes 1 to 5 is large, the driving frequency of the driving circuit can be increased. In addition, since the n-channel TFTs shown in Embodiment Modes 1 to 5 use a buffer layer to reduce parasitic capacitance, frequency characteristics (referred to as f characteristics) are high. For example, since the scanning line driving circuit using the n-channel TFT shown in Embodiment Modes 1 to 5 can be operated at high speed, frame frequency can be increased, black screen insertion can be realized, and the like.

Furthermore, a higher frame frequency can be realized by increasing the channel width of the transistor of the scanning line driving circuit, or disposing a plurality of scanning line driving circuits. In the case of disposing a plurality of scanning line driving circuits, by disposing the scanning line driving circuits for driving the scanning lines of the even-numbered rows on one side of the display panel, and disposing the scanning line driving circuits for driving the scanning lines of the odd-numbered rows On its opposite side, an increase in frame frequency can be achieved.

In addition, in the case of manufacturing an active matrix type light-emitting display device, a plurality of thin film transistors are arranged in at least one pixel, so it is preferable to arrange a plurality of scanning line driver circuits. FIG. 10B shows an example of a block diagram of an active matrix light-emitting display device.

The display device shown in FIG. 10B includes on a substrate 5400: a pixel portion 5401 having a plurality of pixels having display elements; a first scanning line driving circuit 5402 and a second scanning line driving circuit 5404 for selecting each pixel; and a control pair The video signal of the selected pixel is input to the signal line driver circuit 5403 .

When a video signal input to a pixel of the display device shown in FIG. 10B is digital, the pixel is turned into a light-emitting or non-light-emitting state by switching the thin film transistor to an on state or an off state. Therefore, the area gray scale method or the time gray scale method can be used for gray scale display. The area gradation method is a driving method in which gradation display is performed by dividing one pixel into a plurality of sub-pixels and driving each sub-pixel according to a video signal. In addition, the time gray scale method is a driving method in which gray scale display is performed by controlling the period during which pixels of transistors emit light.

The response speed of the light-emitting element is faster than that of the liquid crystal element, so it is more suitable for the time gray scale method than the liquid crystal element. Specifically, in the case of displaying using the time gray scale method, one frame period is divided into multiple sub-frame periods. Then, according to the video signal, the light-emitting elements of the pixels are brought into a light-emitting or non-light-emitting state in each sub-frame period. By dividing into a plurality of sub-frame periods, the video signal can be used to control the total length of the period during which the pixels actually emit light in one frame period, and to display gradation.

In addition, an example is shown in the light-emitting device shown in FIG. 10B in which when two TFTs, that is, a switching TFT and a current control TFT are arranged in one pixel, the first scanning line driving circuit 5402 is used to generate the current input to the switching TFT. The signal of the first scanning line of the gate wiring is used to generate the signal of the second scanning line of the gate wiring of the current control TFT using the second scanning line driver circuit 5404 . However, it is also possible to use one scanning line driver circuit to generate the signal input to the first scanning line and the signal input to the second scanning line. In addition, for example, depending on the number of transistors included in the switching element, a plurality of first scanning lines for controlling the operation of the switching element may be provided in each pixel. In this case, one scanning line driving circuit may be used to generate all the signals input to the plurality of first scanning lines, or a plurality of scanning line driving circuits may be used to generate all the signals input to the plurality of first scanning lines respectively.

In addition, in the light-emitting device, a part of the driver circuit, which can be composed of n-channel TFTs, may be formed on the same substrate as the thin film transistor in the pixel portion. In addition, the signal line driver circuit and the scan line driver circuit may be manufactured using only the n-channel TFTs described in Embodiment Modes 1 to 5.

In addition, the drive circuit described above can be used in electronic paper that drives electronic ink using an element electrically connected to a switching element, in addition to a liquid crystal display device or a light emitting device. Electronic paper is also called an electrophoretic display device (electrophoretic display), and has the advantages of being as easy to read as paper, consuming less power than other display devices, and being able to be formed into a thin and light shape.

Various methods are conceivable as the electrophoretic display. An electrophoretic display is a device in which a plurality of microcapsules including first particles having a positive charge and second particles having a negative charge are dispersed in a solvent or a solute, and the particles in the microcapsules are caused to interact with each other by applying an electric field to the microcapsules. Move in the opposite direction to only show the color of particles that are grouped together. In addition, the first particle or the second particle contains a dye, and does not move in the absence of an electric field. Also, the first particle and the second particle have different colors (including colorless).

As such, an electrophoretic display is a display utilizing a so-called dielectrophoretic effect. In this dielectrophoretic effect, a substance with a high dielectric constant moves to a high electric field region. The electrophoretic display does not require a polarizing plate and an opposing substrate required for a liquid crystal display device, thereby reducing its thickness and weight by half.

The solvent in which the above microcapsules are dispersed is called electronic ink, which can be printed on the surface of glass, plastic, cloth, paper, or the like. In addition, color display can also be performed by using color filters or particles having pigments.

Furthermore, a plurality of the above microcapsules are appropriately arranged on an active matrix substrate so that the microcapsules are sandwiched between two electrodes to complete an active matrix type display device, and display can be performed by applying an electric field to the microcapsules. For example, an active matrix substrate obtained according to Embodiment Mode 2 can be used.

In addition, as the first particle and the second particle in the microcapsule, a material selected from conductor materials, insulator materials, semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescence materials, electrochromic materials, magnetic One of the swimming materials or a combination of these materials can be used.

Embodiment 8

A semiconductor device having a display function (also referred to as a display device) can be manufactured by manufacturing a thin film transistor according to one embodiment of the present invention and using the thin film transistor in a pixel portion and a driver circuit. Also, a system-on-panel can be formed by integrally forming a part or the whole of the driver circuit on the same substrate as the pixel portion using the thin film transistor according to one embodiment of the present invention.

The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) and a light emitting element (also referred to as a light emitting display element) can be used. The category of light-emitting elements includes elements whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence; electroluminescence), organic EL, and the like. In addition, a display medium whose contrast is changed by electricity, such as electronic ink, can also be applied.

In addition, the display device includes a panel in which a display element is sealed and a module in which an IC including a controller and the like are mounted. Furthermore, an aspect of the present invention relates to an element substrate corresponding to an aspect before the display element is completed in the process of manufacturing the display device, and each of a plurality of pixels is provided with a to supply current to the unit of the display element. Specifically, the element substrate may be in a state where only the pixel electrodes of the display element are formed, or may be in a state after forming a conductive film to be a pixel electrode and before forming a pixel electrode by etching, and any of them may be used.

Note that a display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). In addition, the display device also includes modules equipped with connectors such as FPC (Flexible Printed Circuit; flexible printed circuit), TAB (Tape Automated Bonding; tape carrier automatic bonding) tape or TCP (Tape Carrier Package; tape carrier package); A module in which the printed circuit board is fixed to the end of the TAB tape or TCP; a module in which the IC (integrated circuit) is directly mounted on the display element by COG (Chip On Glass; chip on glass).

In this embodiment mode, an example of a liquid crystal display device is shown as a semiconductor device according to one embodiment of the present invention.

16A and 16B show an active matrix liquid crystal display device to which one embodiment of the present invention is applied. FIG. 16A is a plan view of a liquid crystal display device, and FIG. 16B is a cross-sectional view along line V-X in FIG. 16A. The thin film transistor 201 used in a semiconductor device can be manufactured in the same manner as the thin film transistor described in Embodiment Mode 4, and it includes an IGZO semiconductor layer and a buffer composed of an n-type conductive oxide semiconductor layer containing In, Ga, and Zn. A thin film transistor with high layer reliability. In addition, the thin film transistors described in Embodiment Mode 1 to Embodiment Mode 3 and Embodiment Mode 5 can also be used as the thin film transistor 201 of this embodiment mode.

The liquid crystal display device of this embodiment shown in FIG. 16A includes a source wiring layer 202 , an inverted staggered thin film transistor 201 with a multi-gate structure, a gate wiring layer 203 , and a capacitance wiring layer 204 .

In addition, in FIG. 16B, the liquid crystal display device of the present embodiment includes a substrate 200 and a substrate 266 sandwiching a liquid crystal layer 262 and a liquid crystal display element 260. The substrate 200 is provided with a multi-gate transistor 201, an insulating layer 211, an insulating layer 212, an insulating layer 213, an electrode layer 255 for a display element, an insulating layer 261 serving as an alignment film, a polarizer 268, and the substrate 266 is provided with an insulating layer 263 serving as an alignment film, for The electrode layer 265 of the display element, the colored layer 264 used as a color filter, and the polarizer 267 .

Note that FIGS. 16A and 16B are examples of a transmissive liquid crystal display device, but one embodiment of the present invention can be applied to a reflective liquid crystal display device or a transflective liquid crystal display device.

In addition, the liquid crystal display device of FIGS. 16A and 16B shows that a polarizing plate 267 is provided on the outside (visible side) of a substrate 266, and a colored layer 264, an electrode layer 265 for a display element are provided in this order on the inside of the substrate 266. example, but a polarizing plate 267 may also be provided inside the substrate 266. In addition, the lamination structure of the polarizing plate and the colored layer is not limited to those shown in FIGS. 16A and 16B, and may be appropriately set according to the materials of the polarizing plate and the colored layer and the conditions of the manufacturing process. In addition, a light-shielding film serving as a black matrix may also be provided.

As the electrode layers 255 and 265 used as the pixel electrode layers, light-transmitting conductive materials such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and oxide containing titanium oxide can be used. Indium tin, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, etc.

In addition, the electrode layers 255 and 265 may be formed using a conductive composition including a conductive polymer (also referred to as a conductive polymer). The sheet resistance of the pixel electrode formed using the conductive composition is preferably 10000 Ω/□ or less, and the light transmittance at a wavelength of 550 nm is preferably 70% or more. In addition, the resistivity of the conductive polymer included in the conductive composition is preferably 0.1 Ω·cm or less.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or the copolymer of two or more of these materials etc. are mentioned.

Through the above steps, a highly reliable liquid crystal display device as a semiconductor device can be manufactured.

This embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

Embodiment 9

In this embodiment, an example of electronic paper is shown as a semiconductor device according to one aspect of the present invention.

FIG. 17 shows an active matrix electronic paper as an example of a semiconductor device to which one embodiment of the present invention is applied. The thin film transistor 581 used in a semiconductor device can be manufactured in the same way as the thin film transistor described in Embodiment Mode 4, and the thin film transistor 581 is made of an oxide semiconductor including In, Ga, and Zn having an n-type conductivity type including an IGZO semiconductor layer. A thin film transistor with high reliability of the buffer layer composed of layers. In addition, the thin film transistor described in Embodiment Mode 1, Embodiment Mode 3, or Embodiment Mode 4 may also be applied as the thin film transistor 581 of this embodiment mode.

The electronic paper shown in FIG. 17 is an example of a display device using a rotating ball display method. The rotating ball display method refers to a method in which spherical particles having a black surface on one hemisphere and a white surface on the other hemisphere are arranged between a first electrode layer and a second electrode layer of an electrode layer for a display element, and A potential difference is generated between the first electrode layer and the second electrode layer to control the direction of the spherical particles for display.

The thin film transistor 581 is an inverted staggered thin film transistor with a multi-gate structure, and contacts and is electrically connected to the first electrode layer 587 through a source electrode layer and a drain electrode layer in an opening formed in the insulating layer 585 . A spherical particle 589 is arranged between the first electrode layer 587 and the second electrode layer 588, and the spherical particle has a black region 590a and a white region 590b, and a cavity 594 filled with liquid is included around it, and the periphery of the spherical particle 589 is filled with Filler 595 such as resin (see FIG. 17 ).

In FIG. 17 , an electrode layer including a light-transmitting conductive polymer is used as the first electrode layer. An inorganic insulating film is provided on the first electrode layer 587 , and serves as a barrier film to prevent diffusion of ionic impurities from the first electrode layer 587 .

In addition, an electrophoretic element may also be used instead of the rotating ball. A microcapsule having a diameter of about 10 μm to 200 μm in which a transparent liquid, positively charged white particles and negatively charged black particles are sealed is used. For the microcapsules disposed between the first electrode layer and the second electrode layer, when an electric field is applied by the first electrode layer and the second electrode layer, white particles and black particles move to opposite directions, so that white or black can be displayed. A display element applying this principle is an electrophoretic display element, which is generally called electronic paper. Electrophoretic display elements have higher reflectance than liquid crystal display elements, and thus do not require auxiliary lamps. In addition, the power consumption is small, and the display portion can be seen even in a dark place. In addition, even if power is not supplied to the display unit, the image displayed once can be retained. Therefore, even if the semiconductor device with a display function (simply referred to as a display device, or a semiconductor device with a display device) is kept away from the radio wave emission source, it is also possible to store the displayed image.

Through the above steps, electronic paper with high reliability as a semiconductor device can be manufactured.

This embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

Embodiment 10

In this embodiment mode, an example of a light-emitting display device is shown as a semiconductor device according to one aspect of the present invention. Here, a light-emitting element using electroluminescence is shown as a display element included in the display device. Light-emitting elements using electroluminescence are distinguished according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

In an organic EL element, by applying a voltage to a light-emitting element, electrons and holes are respectively injected from a pair of electrodes into a layer containing a light-emitting organic compound to generate a current. Then, by recombining these carriers (electrons and holes), the light-emitting organic compound reaches an excited state, and when this excited state returns to the ground state, light emission is obtained. Based on this mechanism, the light emitting element is called a current excitation type light emitting element.

Inorganic EL elements are classified into dispersion type inorganic EL elements and thin film type inorganic EL elements according to their element structures. The dispersion-type inorganic EL element includes a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and its light-emitting mechanism is a donor-acceptor recombination type light emission utilizing a donor level and an acceptor level. A thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and electrodes, and its light-emitting mechanism is localized light emission utilizing inner-shell electron transitions of metal ions. Note that an organic EL element is used as a light-emitting element in the description herein.

18A and 18B show an active matrix light-emitting display device as an example of a semiconductor device to which one embodiment of the present invention is applied. 18A is a plan view of a light emitting display device, and FIG. 18B is a cross-sectional view taken along line Y-Z in FIG. 18A. Note that FIG. 19 shows an equivalent circuit of the light-emitting display device shown in FIGS. 18A and 18B.

The thin film transistors 301 and 302 used in semiconductor devices can be manufactured in the same way as the thin film transistors shown in Embodiment Mode 1 and Embodiment Mode 2, and the thin film transistors 301 and 302 include an IGZO semiconductor layer and are made of In , Ga, and Zn oxide semiconductor layers as buffer layers with high reliability thin film transistors. In addition, the thin film transistors described in Embodiment Mode 3 to Embodiment Mode 5 can also be applied as the thin film transistors 301 and 302 of this embodiment mode.

The light-emitting display device of this embodiment shown in FIG. 18A and FIG. 19 includes a thin film transistor 301 with a multi-gate structure, a light-emitting element 303 , a capacitor element 304 , a source wiring layer 305 , a gate wiring layer 306 , and a power supply line 307 . The thin film transistors 301 and 302 are n-channel thin film transistors.

In addition, in FIG. 18B, the light-emitting display device of this embodiment includes a thin film transistor 302, an insulating layer 311, an insulating layer 312, an insulating layer 313, a partition wall 321, a first electrode layer 320 for a light-emitting element 303, an electroluminescent layer 322 . The second electrode layer 323 .

The insulating layer 313 is preferably formed using an organic resin such as acrylic, polyimide, polyamide, or siloxane.

In this embodiment, since the thin film transistor 302 of the pixel is n-type, it is preferable to use a cathode as the first electrode layer 320 of the pixel electrode layer. Specifically, as the cathode, a material having a small work function such as Ca, Al, CaF, MgAg, AlLi, or the like can be used.

The partition wall 321 is formed using an organic resin film, an inorganic insulating film, or an organopolysiloxane. Particularly preferably, an opening is formed on the first electrode layer 320 using a photosensitive material, and the sidewall of the opening is formed as an inclined surface with a continuous curvature.

The electroluminescence layer 322 may be composed of a single layer or a stack of multiple layers.

The second electrode layer 323 using an anode is formed to cover the electroluminescent layer 322 . The second electrode layer 323 can be formed by using a light-transmitting conductive film using a light-transmitting conductive material listed as the pixel electrode layer in Embodiment Mode 7. In addition to the above-mentioned light-transmitting conductive film, a titanium nitride film or a titanium film may also be used. The light emitting element 303 is formed by overlapping the first electrode layer 320 , the electroluminescent layer 322 , and the second electrode layer 323 . Then, a protective film may be formed on the second electrode layer 323 and the partition wall 321 to prevent intrusion of air (oxygen, hydrogen, moisture, carbon dioxide, etc.) into the light emitting element 303 . As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, or the like can be formed.

Furthermore, in practice, it is preferable to use a highly airtight and less air-leakage protective film (lamination film, ultraviolet curable resin film, etc.) exposed to air.

Next, the structure of the light emitting element will be described with reference to FIGS. 20A to 20C. Here, the cross-sectional structure of the pixel will be described by taking the case where the driving TFT is n-type as an example. The driving TFTs 7001, 7011, and 7021 used in the semiconductor devices shown in FIGS. 20A, 20B, and 20C can be produced in the same way as the thin film transistors shown in Embodiment Mode 1, and these TFTs include an IGZO semiconductor layer and are made of n-type conductivity containing In, A highly reliable thin film transistor with a buffer layer made of Ga and Zn oxide semiconductor layers. In addition, the thin film transistors described in Embodiment Mode 2, Embodiment Mode 3, or Embodiment Mode 4 may be applied as TFTs 7001 , 7011 , and 7021 .

In order to take out light emission, at least one of the anode and the cathode of the light emitting element may be transparent. Furthermore, a thin film transistor and a light-emitting element are formed on a substrate, and there is a light-emitting element having a structure of top emission for taking out light emission from a surface opposite to the substrate, bottom emission for taking light emission from a surface on one side of the substrate, and a light emission element from a surface opposite to the substrate. One side of the substrate and the side opposite to the substrate take out the luminous double-sided emission. The pixel structure of one embodiment of the present invention can be applied to light-emitting elements of any emission structure.

A light-emitting element with a top emission structure will be described with reference to FIG. 20A .

A cross-sectional view of a pixel when the driving TFT 7001 is n-type and light emitted from the light emitting element 7002 passes through the anode 7005 side is shown in FIG. 20A . In FIG. 20A , a cathode 7003 of a light emitting element 7002 is electrically connected to a driving TFT 7001 , and a light emitting layer 7004 and an anode 7005 are sequentially stacked on the cathode 7003 . As for the cathode 7003, various materials can be used as long as it is a conductive film having a small work function and reflecting light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are preferably used. Also, the light emitting layer 7004 may be composed of a single layer or a stack of multiple layers. When composed of multiple layers, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are sequentially stacked on the cathode 7003 . Note that not all of these layers need to be set. The anode 7005 is formed by using a light-transmitting transparent conductive material, and a light-transmitting conductive film such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide including titanium oxide, indium tin oxide (hereinafter, referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, and the like.

The region where the light emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light emitting element 7002 . In the pixel shown in FIG. 20A , light emitted from the light emitting element 7002 is emitted to the anode 7005 side as indicated by an arrow.

Next, a light emitting element having a bottom emission structure will be described with reference to FIG. 20B . A cross-sectional view of a pixel in a case where the driving TFT 7011 is n-type and light emitted from the light-emitting element 7012 is emitted to the cathode 7013 side is shown. In FIG. 20B , a cathode 7013 of a light-emitting element 7012 is formed on a light-transmitting conductive film 7017 electrically connected to a driving TFT 7011 , and a light-emitting layer 7014 and an anode 7015 are sequentially stacked on the cathode 7013 . Note that when the anode 7015 is light-transmitting, a shielding film 7016 may be formed to cover the anode to reflect light or shield light. As in the case of FIG. 20A , as for the cathode 7013, various materials can be used as long as it is a conductive material with a small work function. However, the thickness is set to transmit light (preferably about 5 nm to 30 nm). For example, an aluminum film having a film thickness of 20 nm can be used as the cathode 7013 . Furthermore, as in FIG. 20A , the light emitting layer 7014 may be composed of a single layer or a stack of multiple layers. The anode 7015 does not need to transmit light, but can be formed using a light-transmitting conductive material as in FIG. 20A . In addition, although a light-reflecting metal or the like can be used as the shielding film 7016, it is not limited to a metal film. For example, a resin to which a black pigment is added may be used.

The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 corresponds to the light-emitting element 7012 . In the pixel shown in FIG. 20B , light emitted from the light emitting element 7012 is emitted to the cathode 7013 side as indicated by an arrow.

Next, a light-emitting element with a double-sided emission structure will be described with reference to FIG. 20C . In FIG. 20C , a cathode 7023 of a light-emitting element 7022 is formed on a light-transmitting conductive film 7027 electrically connected to a driving TFT 7021 , and a light-emitting layer 7024 and an anode 7025 are sequentially stacked on the cathode 7023 . As in the case of FIG. 20A , as for the cathode 7023, various materials can be used as long as it is a conductive material with a small work function. However, its thickness is set to transmit light. For example, Al having a thickness of 20 nm can be used as the cathode 7023 . Furthermore, as in Fig. 20A, the light emitting layer 7024 may be composed of a single layer or a stack of multiple layers. The anode 7025 can be formed using a translucent conductive material that transmits light as in FIG. 20A .

The portion where the cathode 7023 , the light-emitting layer 7024 , and the anode 7025 overlap corresponds to the light-emitting element 7022 . In the pixel shown in FIG. 20C , light emitted from the light emitting element 7022 is emitted to the anode 7025 side and the cathode 7023 side as indicated by arrows.

In addition, although an organic EL element is described here as a light emitting element, an inorganic EL element may also be provided as a light emitting element.

In this embodiment, an example is shown in which a thin film transistor (driving TFT) that controls the driving of the light emitting element is electrically connected to the light emitting element, but a configuration in which a current control TFT is connected between the driving TFT and the light emitting element may also be employed.

In addition, the semiconductor device shown in this embodiment mode is not limited to the structure shown in FIGS. 20A to 20C and various modifications can be made according to the technical idea of the present invention.

Through the above steps, a highly reliable light-emitting display device as a semiconductor device can be manufactured.

This embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

Embodiment 11

Next, the structure of a display panel which is one embodiment of the semiconductor device of the present invention is shown below. In this embodiment mode, a liquid crystal display panel (also referred to as a liquid crystal panel) which is one mode of a liquid crystal display device including a liquid crystal element serving as a display element, and light emission of one mode of a semiconductor device including a light emitting element serving as a display element will be described. Display panels (also known as light-emitting panels).

Next, the appearance and cross-section of a light-emitting display panel corresponding to one embodiment of the semiconductor device of the present invention will be described with reference to FIGS. 21A and 21B . 21A and 21B are top views of a panel in which a buffer including an IGZO semiconductor layer formed on a first substrate and an oxide semiconductor layer containing In, Ga, and Zn having n-type conductivity is sealed by using a sealing material. Thin film transistors and light emitting elements with high layer reliability are sealed between the second substrate. FIG. 21B corresponds to a cross-sectional view along H-I in FIG. 21A.

A sealing material 4505 is provided to surround the pixel portion 4502 provided on the first substrate 4501, the signal line driver circuits 4503a, 4503b, and the scanning line driver circuits 4504a, 4504b. In addition, a second substrate 4506 is provided over the pixel portion 4502, the signal line driver circuits 4503a, 4503b, and the scanning line driver circuits 4504a, 4504b. Therefore, the pixel portion 4502 , signal line driver circuits 4503 a , 4503 b , and scanning line driver circuits 4504 a , 4504 b are sealed by the first substrate 4501 , sealing material 4505 , and second substrate 4506 together with the filler 4507 .

In addition, the pixel portion 4502, the signal line driver circuits 4503a, 4503b, and the scan line driver circuits 4504a, 4504b provided on the first substrate 4501 include a plurality of thin film transistors. In FIG. 21B , a thin film transistor 4510 included in a pixel portion 4502 and a thin film transistor 4509 included in a signal line driver circuit 4503 a are illustrated.

The thin-film transistors 4509 and 4510 correspond to thin-film transistors including an IGZO semiconductor layer and a buffer layer composed of an n-type conductivity-type oxide semiconductor layer containing In, Ga, and Zn, and can be applied as described in Embodiment Mode 1 to Embodiment Mode 5. thin film transistors. In this embodiment, the thin film transistors 4509 and 4510 are n-channel thin film transistors.

In addition, reference numeral 4511 corresponds to a light emitting element, and a first electrode layer 4517 as a pixel electrode included in the light emitting element 4511 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510 . In addition, the structure of the light emitting element 4511 is not limited to the structure shown in this embodiment. The structure of the light emitting element 4511 can be appropriately changed according to the direction of light taken out from the light emitting element 4511 or the like.

In addition, various signals and potentials supplied to the signal line driving circuits 4503a and 4503b, the scanning line driving circuits 4504a and 4504b, or the pixel unit 4502 are supplied from the FPCs 4518a and 4518b.

In this embodiment, the wiring 4516 is formed using the same material as the source electrode layer or the drain electrode layer, and the wiring 4516 is connected to the pixel portion 4502, Signal line driving circuits 4503a, 4503b, or scanning line driving circuits 4504a, 4504b. Furthermore, a connection terminal 4515 is formed using the same material as that of the first electrode layer 4517 on the wiring 4516 at the end of the substrate 4501 .

The connection terminal 4515 is electrically connected to a terminal of the FPC 4518 a via an anisotropic conductive film 4519 .

The second substrate 4506 located in the extraction direction of light from the light emitting element 4511 needs to be light-transmissive. In this case, a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

In addition, as the filler 4507, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin may be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) may be used. In this embodiment, nitrogen is used as a filler.

In addition, if necessary, such as polarizers, circular polarizers (including elliptical polarizers), phase difference plates (λ/4, λ/2), color filters, etc. Optical films such as sheets. In addition, an antireflection film may be provided on a polarizing plate or a circular polarizing plate. For example, anti-glare treatment can be performed, which is a treatment that uses the unevenness of the surface to diffuse reflected light and reduce glare.

The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b may be mounted on a separately prepared substrate as a driver circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film. In addition, only a signal line driver circuit or a part thereof, or a scanning line driver circuit or a part thereof may be separately formed and mounted. The present embodiment is not limited to the structures of FIGS. 21A and 21B.

Next, the appearance and cross section of a liquid crystal display panel corresponding to one embodiment of the semiconductor device of the present invention will be described with reference to FIGS. 22A1 , 22A2 , and 22B. 22A1 and 22A2 are top views of a panel in which a semiconductor layer including IGZO and an oxide semiconductor layer including In, Ga, and Zn having n-type conductivity are formed on a first substrate 4001 by using a sealing material 4005. The thin film transistors 4010 and 4011 and the liquid crystal element 4013 with high reliability of the buffer layer are sealed between the buffer layer and the second substrate 4006 . Fig. 22B corresponds to a cross-sectional view along M-N of Figs. 22A1 and 22A2.

A sealing material 4005 is provided to surround the pixel portion 4002 and the scanning line driver circuit 4004 provided on the first substrate 4001 . In addition, a second substrate 4006 is provided over the pixel portion 4002 and the scanning line driver circuit 4004 . Therefore, the pixel portion 4002 and the scanning line driver circuit 4004 are sealed together with the liquid crystal 4008 by the first substrate 4001 , the sealing material 4005 and the second substrate 4006 . Further, in a region on the first substrate 4001 different from the region surrounded by the sealing material 4005 is mounted a signal line driver circuit 4003 which is formed using a single crystal semiconductor film or a polycrystalline semiconductor film and is separately prepared. on the substrate.

In addition, there is no particular limitation on the connection method of the separately formed driving circuit, and a COG method, a wire bonding method, a TAB method, or the like may be employed. FIG. 22A1 is an example of mounting the signal line driver circuit 4003 by the COG method, and FIG. 22A2 is an example of mounting the signal line driver circuit 4003 by the TAB method.

Furthermore, the pixel portion 4002 and the scanning line driver circuit 4004 provided on the first substrate 4001 include a plurality of thin film transistors. FIG. 22B illustrates a thin film transistor 4010 included in the pixel portion 4002 and a thin film transistor 4011 included in the scanning line driver circuit 4004 .

The thin-film transistors 4010 and 4011 correspond to thin-film transistors including an IGZO semiconductor layer and a buffer layer composed of an n-type conductivity-type oxide semiconductor layer containing In, Ga, and Zn, and can be applied as described in Embodiment Mode 1 to Embodiment Mode 5. thin film transistors. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors.

In addition, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010 . Further, the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006 . The portion where the pixel electrode layer 4030 , the counter electrode layer 4031 , and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013 . Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are respectively provided with insulating layers 4032 and 4033 serving as alignment films, and a liquid crystal layer 4008 is sandwiched between the insulating layers 4032 and 4033 .

Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, and plastics can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics; fiber-reinforced plastics) plate, PVF (polyvinyl fluoride) film, polyester film, or acrylic resin film can be used. In addition, a sheet having a structure in which aluminum foil is sandwiched between PVF films or polyester films can also be used.

Also, reference numeral 4035 denotes a columnar spacer obtained by selectively etching an insulating film, and it is provided for controlling the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 . Note that spherical spacers can also be used.

In addition, various signals and potentials supplied to the separately formed signal line driver circuit 4003 , scanning line driver circuit 4004 , or pixel portion 4002 are supplied from the FPC 4018 .

In this embodiment, connection terminal 4015 is made of the same conductive film as pixel electrode layer 4030 of liquid crystal element 4013 , and wiring 4016 is made of the same conductive film as gate electrode layers of thin film transistors 4010 and 4011 .

The connection terminal 4015 is electrically connected to a terminal that the FPC 4018 has through the anisotropic conductive film 4019 .

Furthermore, although an example in which the signal line driver circuit 4003 is additionally formed and mounted on the first substrate 4001 is shown in FIGS. 22A and 22B , this embodiment mode is not limited to this structure. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

FIG. 23 shows an example in which a liquid crystal display module used as a semiconductor device is formed using a TFT substrate 2600 manufactured by applying one embodiment of the present invention.

23 is an example of a liquid crystal display module, which is formed by fixing a TFT substrate 2600 and a counter substrate 2601 with a sealing material 2602, and interposing a pixel portion 2603 including a TFT or the like, a display element 2604 including a liquid crystal layer, and a colored layer 2605. display area. The coloring layer 2605 is required for color display, and when the RGB method is used, coloring layers corresponding to red, green, and blue are provided for each pixel. A polarizing plate 2606 , a polarizing plate 2607 , and a diffusing plate 2613 are disposed outside the TFT substrate 2600 and the counter substrate 2601 . The light source is composed of a cold cathode tube 2610 and a reflector 2611. The circuit substrate 2612 is connected to the wiring circuit part 2608 of the TFT substrate 2600 by a flexible circuit board 2609, and external circuits such as a control circuit and a power circuit are assembled therein. In addition, they may be laminated with a retardation plate between the polarizing plate and the liquid crystal layer.

As a liquid crystal display module, TN (Twisted Nematic; Twisted Nematic) mode, IPS (In-Plane Switching; In-Plane-Switching) mode, FFS (Fringe Field Switching; Fringe Field Switching) mode, MVA (Multi-Domain Vertical Alignment) mode can be used. ;Multi-domain Vertical Alignment) mode, PVA (vertical alignment configuration; PatternedVertical Alignment) mode, ASM (axis symmetric array microcell; Axially Symmetric aligned Micro-cell) mode, OCB (optical compensation bending; Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal; Ferroelectric Liquid Crystal) mode, AFLC (Antiferroelectric Liquid Crystal; Anti Ferroelectric Liquid Crystal) mode, etc.

Through the above steps, a highly reliable display panel as a semiconductor device can be manufactured.

This embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

Embodiment 12

The semiconductor device according to the present invention can be applied to various electronic devices (including game machines). Examples of electronic equipment include television sets (also called televisions or television receivers), monitors for computers, electronic paper, digital cameras, digital video cameras, digital photo frames, mobile phones (also called mobile phones, etc.) , mobile phone devices), portable game machines, portable information terminals, sound reproduction devices, large game machines such as pachinko machines, etc. In particular, as shown in Embodiment Mode 8 to Embodiment Mode 11, by applying the thin film transistor according to the present invention to a liquid crystal display device, a light emitting device, an electrophoretic display device, etc., it can be used in a display portion of an electronic device. Hereinafter, specific examples will be given.

The semiconductor device according to one embodiment of the present invention can be applied to electronic paper as described in the ninth embodiment. Electronic paper can be used for electronic devices in all fields for displaying information. For example, electronic paper can be applied to electronic books (e-books), posters, compartment advertisements of vehicles such as trains, displays on various cards such as credit cards, and the like. 24A and 24B and FIG. 25 show an example of electronic equipment.

FIG. 24A shows a poster 1601 made using electronic paper. When the advertisement medium is a printed matter of paper, advertisements are exchanged by hand, but by using electronic paper to which a semiconductor device according to one aspect of the present invention is applied, the display content of advertisements can be changed in a short time. In addition, since thin film transistors with good electrical characteristics are used, stable images can be obtained without display disturbance. Note that the poster may also have a structure capable of transmitting and receiving information wirelessly.

In addition, FIG. 24B shows a compartment advertisement 1602 of a vehicle such as a train. When the advertisement medium is printed paper, advertisements are exchanged by hand. However, by using electronic paper to which a semiconductor device according to one embodiment of the present invention is applied, advertisement display contents can be changed in a short time without many hands. In addition, since thin film transistors with good electrical characteristics are used, stable images can be obtained without display disturbance. Note that the car advertisement may also have a structure capable of transmitting and receiving information wirelessly.

In addition, FIG. 25 shows an example of an electronic book 2700 . For example, electronic book 2700 is composed of two frames, namely frame 2701 and frame 2703 . The frame body 2701 and the frame body 2703 are integrally formed by the shaft portion 2711, and can be opened and closed around the shaft portion 2711. By adopting such a structure, it is possible to perform work like a paper book.

The housing 2701 is assembled with a display unit 2705 , and the housing 2703 is assembled with a display unit 2707 . The configurations of the display unit 2705 and the display unit 2707 may be configured to display continuous screens, or may be configured to display different screens. By adopting a structure for displaying different screens, for example, an article can be displayed on the right display (display 2705 in FIG. 25 ), and an image can be displayed on the left display (display 2707 in FIG. 25 ).

In addition, FIG. 25 shows an example in which the housing 2701 includes an operation unit and the like. For example, the housing 2701 includes a power supply 2721 , operation keys 2723 , a speaker 2725 , and the like. Pages can be turned using the operation keys 2723 . In addition, a configuration may be adopted in which a keyboard, a pointing device, and the like are provided on the same surface as the display portion of the casing. In addition, it is also possible to adopt a configuration in which external connection terminals (earphone terminals, USB terminals, or terminals connectable to various cables such as AC adapters and USB cables), recording medium insertion parts, etc. are provided on the back or side of the housing. Furthermore, the electronic book 2700 may also have the function of an electronic dictionary.

In addition, the electronic book 2700 may have a structure capable of transmitting and receiving information wirelessly. It is also possible to adopt a structure in which desired book data etc. are purchased wirelessly from an electronic book server and then downloaded.

An example of a television set 9600 is shown in FIG. 26A . In television device 9600 , display unit 9603 is incorporated into housing 9601 . Videos can be displayed on the display unit 9603 . In addition, a structure in which the frame body 9601 is supported by a bracket 9605 is shown here. The display devices described in the eighth to eleventh embodiments can be applied as the display unit 9603 .

The television apparatus 9600 can be operated by using the operation switches included in the housing 9601 and the remote control unit 9610 provided separately. By using the operation keys 9609 included in the remote control device 9610 , channel and volume operations can be performed, and images displayed on the display unit 9603 can be operated. In addition, a configuration may be employed in which the remote operation device 9610 is provided with a display unit 9607 that displays information output from the remote operation device 9610 .

In addition, the television device 9600 has a configuration including a receiver, a modem, and the like. General TV broadcasts can be received by using a receiver. Furthermore, it is connected to a wired or wireless communication network through a modem, so that one-way (from sender to receiver) or two-way (between sender and receiver or between receivers, etc.) information communication can also be carried out .

An example of a digital photo frame 9700 is shown in FIG. 26B. For example, in a digital photo frame 9700 , a display unit 9703 is incorporated into a frame body 9701 . The display unit 9703 can display various images, and can function similarly to a general photo frame by displaying, for example, image data captured by a digital camera or the like.

In addition, the digital photo frame 9700 has a configuration including an operation unit, terminals for external connection (USB terminal, a terminal connectable to various cables such as a USB cable, etc.), a recording medium insertion unit, and the like. These structures can also be assembled on the same surface as the display unit, but it is preferable to provide them on the side or the back to improve the designability. For example, a memory storing image data captured by a digital camera may be inserted into the recording medium insertion portion of a digital photo frame to extract the image data, and then the extracted image data may be displayed on the display portion 9703 .

In addition, the digital photo frame 9700 may also adopt a structure capable of transmitting and receiving information wirelessly. It is also possible to employ a configuration in which desired image data is extracted wirelessly and displayed.

FIG. 27 shows an example of a digital player 2100 as a portable audio device. The digital player 2100 includes a main body 2130, a display unit 2131, a memory unit 2132, an operation unit 2133, earphones 2134, a control unit 2137, and the like. Note that instead of earphones 2134, headphones or wireless earphones may be used. The display devices described in Embodiment Mode 8 to Embodiment Mode 11 can be applied as the display unit 2131 .

In addition, by operating the operation unit 2133 using the memory unit 2132 , video and audio (music) can be recorded and reproduced. Note that the display unit 2131 can suppress power consumption by displaying white characters on a black background. Note that the memory provided in the memory unit 2132 may also have a removable structure.

FIG. 28 shows an example of mobile phone 1000 . Mobile phone 1000 includes operation buttons 1003 , an external connection port 1004 , a speaker 1005 , a microphone 1006 , and the like in addition to display unit 1002 mounted in housing 1001 . The display devices described in Embodiment Mode 8 to Embodiment Mode 11 can be applied as the display unit 1002 .

Mobile phone 1000 shown in FIG. 28 can touch display unit 1002 with a finger or the like to input information. In addition, operations such as making a phone call or writing an e-mail can be performed by touching the display unit 1002 with a finger or the like.

The screen of the display unit 1002 mainly has three modes. The first is a display mode that mainly displays images, the second is an input mode that mainly inputs information such as characters, and the third is a display+input mode in which two modes of a display mode and an input mode are mixed.

For example, when making a phone call or writing an e-mail, it is sufficient to set the display unit 1002 to a character input mode mainly for character input, and perform a character input operation displayed on the screen. In this case, it is preferable to display a keyboard or number buttons on most parts of the screen of the display section 1002 .

The orientation of the mobile phone 1000 (vertical or horizontal) can be determined by providing a detection device with a sensor for detecting inclination such as a gyroscope and an acceleration sensor inside the mobile phone 1000, and the screen display of the display unit 1002 can be adjusted. Switch automatically.

The screen mode is switched by touching the display unit 1002 or operating the operation button 1003 of the housing 1001 . It is also possible to switch the screen mode according to the kind of image displayed on the display section 1002 . For example, when the image signal displayed on the display is video data, the screen mode is switched to the display mode, and when the image signal displayed on the display is character data, the screen mode is switched to the input mode.

In the input mode, when the signal detected by the light sensor of the display unit 1002 is detected and it is known that there is no input by the touch operation of the display unit 1002 for a certain period of time, the screen mode may be switched from the input mode to the display mode. way to control.

The display unit 1002 can also be used as an image sensor. For example, personal identification can be performed by touching the display unit 1002 with a palm or a finger to capture palm prints, fingerprints, and the like. Furthermore, by using a backlight emitting near-infrared light or a sensing light source emitting near-infrared light in the display section, it is also possible to photograph finger veins, palm veins, and the like.

This embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

This specification is prepared based on Japanese Patent Application No. 2008-197137 accepted at the Japan Patent Office on July 31, 2008, and the contents of the application are included in this specification.

Claims (11)

1. A method for manufacturing a semiconductor device, comprising the steps of: forming a gate electrode layer on the substrate; forming a gate insulating film covering the gate electrode layer; forming a semiconductor layer on the gate electrode layer via the gate insulating film; forming a channel protection layer on the channel formation region of the semiconductor layer; forming a pair of buffer layers on the semiconductor layer; and forming a source electrode layer and a drain electrode layer on the pair of buffer layers, Wherein, the pair of buffer layers has n-type conductivity, and Wherein, each of the gate insulating film, the semiconductor layer, and the channel protective layer is formed by performing sputtering in an atmosphere containing 90% or more of oxygen. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer and the pair of buffer layers each include an oxide semiconductor containing indium, gallium, and zinc. 3. The method for manufacturing a semiconductor device according to claim 1, wherein a carrier concentration of the pair of buffer layers is higher than a carrier concentration of the semiconductor layer. 4. A method for manufacturing a semiconductor device, comprising the steps of: forming a gate electrode layer on the substrate; forming a gate insulating film covering the gate electrode layer; forming a semiconductor layer on the gate electrode layer via the gate insulating film; forming a channel protection layer on the channel formation region of the semiconductor layer; forming a pair of first buffer layers on the semiconductor layer via a pair of second buffer layers; and forming a source electrode layer and a drain electrode layer on the pair of first buffer layers, Wherein, each of the pair of first buffer layers and the pair of second buffer layers has n-type conductivity, and Wherein, each of the gate insulating film, the semiconductor layer, and the channel protective layer is formed by performing sputtering in an atmosphere containing 90% or more of oxygen. 5. The method for manufacturing a semiconductor device according to claim 4, wherein each of the semiconductor layer, the pair of first buffer layers, and the pair of second buffer layers comprises a compound containing indium, gallium, and Zinc oxide semiconductor. 6. The method for manufacturing a semiconductor device according to claim 4, wherein, The carrier concentration of the pair of first buffer layers is higher than the carrier concentration of the pair of second buffer layers, and A carrier concentration of the pair of second buffer layers is higher than a carrier concentration of the semiconductor layer. 7. The method for manufacturing a semiconductor device according to claim 4, wherein the pair of first buffer layers serves as an n ⁺ layer, and the pair of second buffer layers serves as an n ⁻ layer. 8. The method for manufacturing a semiconductor device according to claim 1 or 4, wherein the channel protection layer is used as an etching stopper layer. 9. The method for manufacturing a semiconductor device according to claim 1 or 4, wherein the gate insulating film, the semiconductor layer, and the channel protective layer are continuously formed without being exposed to the atmosphere . 10. A semiconductor device comprising: gate electrode; a gate insulating film covering the gate electrode; a semiconductor layer on the gate electrode layer via the gate insulating film; a channel protection layer on the channel formation region of the semiconductor layer; a pair of first buffer layers on the semiconductor layer; and a source electrode layer and a drain electrode layer on the pair of first buffer layers, wherein each of the semiconductor layer and the pair of buffer layers includes an oxide semiconductor including indium, gallium, and zinc, Wherein, the carrier concentration of the pair of first buffer layers is higher than the carrier concentration of the semiconductor layer, Wherein, the pair of first buffer layers has n-type conductivity, and Wherein, each of the gate insulating film and the semiconductor layer contains excess oxygen. 11. The semiconductor device according to claim 10, further comprising: a pair of second buffer layers between the pair of first buffer layers and the semiconductor layer, Wherein, the pair of second buffer layers has n-type conductivity, Wherein, the pair of second buffer layers includes an oxide semiconductor including indium, gallium, and zinc, and Wherein, the carrier concentration of the pair of second buffer layers is higher than the carrier concentration of the semiconductor layer, and lower than the carrier concentration of the pair of first buffer layers.