CN103745934B - Wafer-level packaging method - Google Patents

Abstract

The present invention relates to a kind of wafer-level packaging method, described method for packing includes: providing the multiple wafers being categorized as at least two classification, multiple wafers of each classification are respectively provided with the multiple samples comprising at least one wafer；Sample for each classification carries out chip probing test respectively, obtains the wafer figure of sample respectively；In conjunction with wafer figure, and the inefficacy that comparison is preset divides threshold value, distinctly displays effective chip unit and invalid chip unit；Combinations matches before being packaged different classes of sample, obtains the optimum matching method that effective chip unit combines；According to described optimum matching method, different classes of wafer is carried out wafer-level packaging.

Description

Wafer Level Packaging Method

technical field

The invention relates to the field of wafer packaging, in particular to a wafer-level packaging method.

Background technique

Wafer level package (wafer level package, WLP) refers to the completion of the packaging process on the wafer, which has the advantages of greatly reducing the area of the packaging structure, reducing manufacturing costs, electrical performance, and superior batch manufacturing, which can significantly reduce the workload and equipment needs. In the packaging method of the prior art, after performing wire redistribution on the wafer, multiple wafers are vertically stacked and bonded (wafer to wafer, W2W), and then sliced to form a 3D integrated IC.

This method has low manufacturing cost and has great advantages, but at the same time, it will introduce a problem of decreased yield index. For example: if the yield rate of one wafer is 90%, and the yield rate of the other wafer is also 90%, then the yield rate of the two chips after bonding will be slightly greater than 90%*90%=81% (because some of them will overlap. The failure chip fail die), which will increase the cost originally reduced by the W2W technology due to the loss of yield.

To sum up, it is an urgent problem for those skilled in the art to provide a wafer-level packaging method that solves the above-mentioned problem of reduced yield due to packaging.

The information disclosed in the Background of the Invention section is only intended to deepen the understanding of the general background of the present invention, and should not be considered as an acknowledgment or any form of suggestion that the information constitutes prior art known to those skilled in the art.

Contents of the invention

In order to solve the above-mentioned problems in the prior art, the object of the present invention is to provide an optimized method for wafer-level packaging.

In order to achieve the above object, the present invention provides a wafer-level packaging method, the packaging method comprising: A) providing a plurality of wafers classified into at least two categories, each category of a plurality of wafers has at least one Multiple samples of the wafer; B) Carry out chip detection tests for each category of samples separately, and obtain the wafer images of the samples; C) Combine the wafer images and compare the preset failure thresholds to distinguish effective chips Units and invalid chip units; D) Combination and matching of different types of samples before packaging to obtain the optimal pairing method for combining effective chip units; E) Wafer processing of different types of wafers according to the optimal pairing method described level packaging.

Preferably, the at least two categories are A, B...Φ, wherein the number of the categories is N, where N≧2; the invalid chips corresponding to samples A1, A2, ..., An in the category A The number of units is a1, a2, ..., an, where a1 to an are integers greater than or equal to 0; the number of invalid chip units corresponding to samples B1, B2, ..., Bn in category B is b1, b2, ... , bn, where b1 to bn are all integers greater than or equal to 0.

Preferably, in the step D), multiple pairing groups are formed after combination matching, and the numbers of invalid chip units in each pairing group are respectively c1, c2, ..., cn, wherein, c1 to cn are all greater than or equal to 0 Integer, the paired packaging yields of each paired group are respectively Y1, Y2, ..., Yn, the packaging yield Yn of each paired group and the overall packaging yield Ya are calculated by the following formula: Yn=(Na-cn )/Na*100%; Ya=(Y1+Y2+...+Yn)/n*100%; wherein, Na is the number of packaged chips in each paired group, and n is the number of paired groups; the step D) The optimal pairing mode is: the matching mode that maximizes the overall packaging yield Ya.

Preferably, in the step E), it also includes: after the samples in the category are correspondingly rotated 180 degrees with respect to the samples in the other category, the front of the samples in the one category and the front of the samples in the other category are carried out. Bonded package.

Preferably, the step E) further includes: directly bonding and encapsulating the front surfaces of the samples in one category and the reverse surfaces of the samples in another category.

Preferably, the samples in one category and the samples in the other category consist of at least one wafer.

Preferably, the failure classification threshold includes: dividing the chips into two grades: failed chips and non-failed chips.

Preferably, the failure classification threshold can further include: dividing the failed chip into two grades: a first-level DC failure level and a second-level functional failure level.

Preferably, the step D) further includes: first performing the pairing process in step D) on the first-level DC failure level to obtain the first-level optimal pairing method, and then performing step D on the second-level functional failure level ) pairing process to obtain the second-level optimal pairing method.

Preferably, the adhesive packaging is performed according to step E) according to the first-level optimal pairing mode; and the adhesive packaging is performed according to step E) according to the second-level optimal pairing mode.

The beneficial effects of the present invention are: the present invention adds a screening process after the chip detection test, arranges and combines the chips through computer optimization to achieve the optimal pairing of the chips, and rearranges the positions of some wafers for packaging accordingly, thereby achieving The purpose of improving yield, reducing cost and improving market competitiveness.

Description of drawings

Other features and advantages of the present invention will become clear or be more specifically explained through the accompanying drawings and the following specific embodiments used to illustrate some principles of the present invention together with the accompanying drawings.

FIG. 1 is a wafer diagram of sample A1 of type A wafer according to the wafer level packaging method of the present invention after chip detection test.

FIG. 1A is a wafer diagram of sample A2 of type A wafer according to the wafer level packaging method of the present invention after chip detection test.

FIG. 2 is a wafer diagram of sample B1 of type B wafer according to the wafer level packaging method of the present invention after chip detection test.

FIG. 2A is a wafer diagram of sample B2 of type B wafer according to the wafer level packaging method of the present invention after chip detection test.

FIG. 3 is a schematic diagram of wafer front-to-front packaging according to the wafer level packaging method of the present invention.

FIG. 4 is a schematic diagram of wafer back-front packaging according to the wafer-level packaging method of the present invention.

FIG. 5 is a flowchart of a wafer level packaging method according to the present invention.

It should be understood that the drawings in the specification do not necessarily show the specific structure of the invention to scale, and that the illustrative features used to illustrate some principles of the invention in the drawings in the specification are also drawn in a somewhat simplified manner. The specific design features of the invention disclosed herein, including, for example, specific dimensions, orientations, locations and shapes will be determined in part by the particular intended application and use environment.

Throughout the several figures of the drawing of the specification, the same reference numbers refer to the same or equivalent parts of the present invention.

Description of main component symbols:

1 Sample A1 of type A wafer

2 Sample A2 of type A wafer

3 Sample B1 of type B wafer

4 Sample B2 of type B wafer

5 Type A Wafer Front Side

6 Type A wafer reverse side

7 Type B Wafer Front Side

8 Type B wafer reverse side.

detailed description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar extensions without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

In the following, specific embodiments of the present invention will be described in conjunction with the accompanying drawings. Please refer to FIG. 5 , the present invention provides a wafer level packaging method.

Packaging method of the present invention comprises the following steps:

A) providing a plurality of wafers classified into at least two classes, each class of the plurality of wafers having a plurality of samples comprising at least one wafer;

B) Carry out chip detection test for samples of each category respectively, and obtain wafer images of samples respectively;

C) Combining with the wafer map and comparing with the preset failure division threshold, the effective chip unit and the invalid chip unit are displayed differently;

D) Combination and matching of different types of samples before packaging to obtain the optimal pairing method for effective chip unit combination;

E) Wafer-level packaging is performed on different types of wafers according to the optimal pairing method.

In the wafer-level packaging method of the present invention, the types of wafers provided are at least two types, such as two types A and B; they can also be multiple types, such as any of 4 to 10 types. The values are further, for example, four types of wafers of A, B, C, and D. In addition, each type of wafer contains multiple samples, and each sample contains at least one wafer, and may also contain multiple wafers, for example, any value from 4 to 25. Further, For example, class A wafer contains 4 samples A1, A2, A3, A4, each sample of class A wafer contains 25 wafers; class B wafer also contains 4 samples B1, B2, B3, B4, each sample of class B wafers contained 25 wafers. Regardless of providing multiple categories of wafers or comprising multiple samples in each category or comprising multiple wafers in each sample, the principle of its combination matching is the same as that described in detail below in the embodiment (two categories, Each category contains two samples, and each sample contains one wafer) The principle of arrangement and combination is the same, and the required combination is generally obtained by calculating the total packaging yield after combination matching.

In an embodiment of the present invention, according to step A), firstly, two types of wafers are provided, that is, one type A (hereinafter referred to as type A) and another type B (hereinafter referred to as type B). As shown in Fig. 1, Fig. 1A, Fig. 2 and Fig. 2A, type A contains two samples, respectively sample A1 and sample A2, each of type A sample A1 and sample A2 contains one wafer, and each wafer The total number N of chips on the circle is 21; similarly, type B also includes sample B1 and sample B2, and each of type B’s sample B1 and sample B2 also includes 1 wafer, and the total number of chips on each wafer is The number N is 21 for both.

Then according to step B) and step C), combined with the sample wafer map obtained after the above-mentioned chip detection test, and comparing with the preset failure division threshold, valid chip units and invalid chip units are displayed differently. For the preset failure division threshold in this embodiment, the setting of the threshold is to divide the chip into non-failed chips and failed chips, that is, corresponding to the above-mentioned valid chip unit and invalid chip unit.

Specifically, as shown in Fig. 1, Fig. 1A, Fig. 2 and Fig. 2A, wherein Fig. 1 and Fig. 1A are two samples A1 and A2 of the type A wafer according to the wafer-level packaging method of the present invention after the chip detection test 2 and 2A are wafer diagrams of two samples B1 and B2 of type B wafer according to the wafer-level packaging method of the present invention after the chip detection test. In Figure 1, Figure 1A, Figure 2, and Figure 2A, the chips marked with black shadows are invalid chip units that are determined to be invalid after the chip detection test, that is, invalid chips, while the remaining chips without color block marks are valid chip units That is, the chip has not failed.

It can be seen that the number of invalid chip units a1 of sample A1 and the number of invalid chip units a2 of sample A2 are both 2, that is, a1=a2=2, while the number of invalid chip units b1 of sample B1 and the number of invalid chip units of sample B2 b2 is also 2, that is, b1=b2=2. From this, the yield rate Ya1 of sample A1, the yield rate Ya2 of sample A2, the yield rate Yb1 of sample B1, and the yield rate Yb2 of sample B2 can be calculated, which are calculated by the following formula:

Ya1=(N-a1)/N*100%;

Ya2=(N-a2)/N*100%;

Yb1=(N-b1)/N*100%;

Yb2=(N-b2)/N*100%;

where N is the total number of chips on each wafer.

Then Ya1=Ya2=Yb1=Yb2=(21-2)/21*100%=90.5%,

Then according to step D), the four wafers of the four samples are combined and matched. Specifically, two combined matching methods can be obtained, and each combined matching method can form two paired groups. The combined methods are respectively: Sample A1 - Sample B1 (pair 1) and Sample A2 - Sample B2 (pair 2), or Sample A1 - Sample B2 (pair 11) and Sample A2 - Sample B1 (pair 22).

In this embodiment, the package bonding between the two groups of wafers adopts a front-to-front bonding method, as shown in Figure 3, that is, the wafers in type A and the wafers in type B are front-to-side. The front side is bonded to each other, so in the actual bonding process, the two wafers of type A are turned over, and then bonded with the wafer of type B after rotating 180 degrees.

Based on the above-mentioned front-front bonding method, for the first combination and matching method: sample A1-sample B1 (pairing group 1) and sample A2-sample B2 (pairing group 2), after sample A1 is turned 180 degrees, it will be combined with sample B1 When bonding, the failed chip units on the wafers of the two samples do not overlap, that is, they are not in the same position. The same is true for sample A2 and sample B2 after being flipped over, so the invalid chips of paired group 1 after matching The number of units c1 and the number of invalid chip units c2 in paired group 2 are both 4, that is, c1=c2=4, and the paired packaging yields of paired group 1 and paired group 2 are Y1 and Y2 respectively, which are calculated by the following formula:

Y1=(Na-c1)/Na*100%;

Y2=(Na-c2)/Na*100%;

The overall packaging yield Ya is calculated by the following formula:

Ya=(Y1+Y2)/n*100%;

Among them, Na is the number of packaged chips in each paired group, which is actually the same as the total number N of chips on each wafer before packaging, and n is the number of paired groups, which is 2 here.

Then Y1=Y2=(21−4)/21*100%=81%, and the overall packaging yield Ya=(81%+81%)/2*100%=81%.

For the second combination and matching method: sample A1-sample B2 (pairing group 11) and sample A2-sample B1 (pairing group 22), when sample A1 is turned over 180 degrees and then bonded to sample B2, the crystals of the two samples The invalid chip units on the circle are coincident, that is, at the same position, the same is true when sample A2 is flipped over and bonded to sample B1, so the number of invalid chip units c11 of paired group 11 after matching and the number of invalid chip units of paired group 22 are the same. The number of chip units c22 is 2, that is, c11=c22=2, and the paired packaging yields of paired group 11 and paired group 22 are Y11 and Y22 respectively, which are calculated by the following formula:

Y11=(Na-c11)/Na*100%;

Y22=(Na-c22)/Na*100%;

The overall packaging yield Ya is calculated by the following formula:

Ya=(Y11+Y22)/n*100%;

Wherein, N is the number of packaged chips in each paired group, which is actually the same as the total number N of chips on each wafer before packaging, and n is the number of paired groups, which is 2 here.

Then Y11=Y22=(21-2)/21*100%=90.5%, and the overall packaging yield Ya=(90.5%+90.5%)/2*100%=90.5%.

Based on the calculation of the above-mentioned yield rate, it can be seen that the second pairing combination method generally has fewer invalid chip units after packaging than the first pairing combination method, that is, there are more effective chip units, and thus the overall packaging yield Ya Larger, so the second pairing combination method is better, that is, the optimal pairing method combined with the effective chip unit described in this embodiment, and then according to step E), according to this optimal pairing method for the type Wafers in type A and type B can be packaged at wafer level.

The above mentioned two types of wafers, each type contains two samples, and each sample contains only one wafer, which can be easily deduced according to the relevant knowledge of the arrangement and combination in the prior art. In various cases where wafers of multiple categories or each category contains multiple samples or each sample contains multiple wafers, the calculation method and principle are the same as those in the above-mentioned embodiments.

In addition, the package bonding between two groups of wafers can also adopt the reverse-front bonding method, as shown in Figure 4, that is, the wafers in type A and the wafers in type B are reverse-to-front. Mutual bonding, in the actual bonding process, the two wafers of type A do not need to be turned over, and the wafers of type B are directly bonded. It can be easily concluded from the above-mentioned combination method and its yield calculation method that for this reverse-front bonding method, the first pairing combination method is the optimal pairing method. All in all, the purpose is to minimize the overall number of invalid chip units after bonding and packaging, that is, to improve the overall yield.

Moreover, in order to describe the behavior of the chip in more detail, the failed chips can be further classified into levels, such as DC failure and functional failure, that is, the above-mentioned invalid chip units can be further divided into different levels of invalid chip units , such as the first-level DC failure level and the second-level functional failure level, in this case, the matching process in step D) is first performed on the first-level DC failure level to obtain the first-level optimal Matching mode, then carry out the matching process of step D) to the second-level functional failure level to obtain the second-level optimal pairing mode, and according to the first-level optimal pairing mode, carry out adhesive packaging according to step E) or according to the second level The optimal pairing method of the level is carried out according to the step E) for bonding and encapsulation.

The above embodiments are used to illustrate the principles and effects of the present invention, but the present invention is not limited to the above embodiments. Those skilled in the art can modify the above-mentioned embodiments within the protection scope of the claims without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be covered by the claims of the present invention.

Claims (9)

1. a wafer-level packaging method, described method for packing includes:

A) offer is categorized as multiple wafers of at least two classification, and multiple wafers of each classification are equal There are the multiple samples comprising at least one wafer；

B) sample for each classification carries out chip probing test respectively, obtains sample respectively Wafer figure；

C) combine wafer figure, and the inefficacy that comparison is preset divides threshold value, distinctly displays effective chip Unit and invalid chip unit；

D) combinations matches before being packaged different classes of sample, obtains effective chip unit In conjunction with optimum matching method；

E) according to described optimum matching method, different classes of wafer is carried out wafer-level packaging；

Described step D) in, form multiple matched group, the nothing of each matched group after combinations matches Effect chip unit quantity be respectively c1, c2 ..., cn, wherein, c1 to cn be more than or Integer equal to 0, the pairing encapsulation yield of described each matched group is respectively Y1, Y2 ..., Yn, the encapsulation yield Yn and overall package yield Ya of each matched group are calculated by below equation Draw:

Yn=(Na-cn)/Na*100%；

Ya=(Y1+Y2+ ...+Yn)/n*100%；

Wherein, Na is the encapsulation number of chips in each matched group, and n is the quantity of matched group；

Described step D) optimum matching method be: described overall package yield Ya is reached Maximum matching method.

Wafer-level packaging method the most according to claim 1, it is characterised in that: described At least two classification is A, B ... Φ, and the quantity of classification is N, wherein N 2；

Sample A1, A2 in described A classification ..., the invalid chip unit quantity that An is corresponding For a1, a2 ..., an, wherein a1 to an is the integer more than or equal to 0；Described B classification in sample B1, B2 ..., invalid chip unit quantity corresponding for Bn is b1, b2 ..., Bn, wherein b1 to bn is the integer more than or equal to 0.

Wafer-level packaging method the most according to claim 1, it is characterised in that: described step Rapid E) in, also include: by sample in a classification for the sample corresponding rotation in another category After 180 degree, sample front in the front of the sample in a classification and another category is carried out bonding envelope Dress.

Wafer-level packaging method the most according to claim 1, it is characterised in that: described step Rapid E) in, also include: the sample in the direct front by the sample in a classification and another category Reverse side carries out bonding encapsulation.

Wafer-level packaging method the most according to claim 1, it is characterised in that: a classification In sample and sample in another category be made up of at least one wafer respectively.

Wafer-level packaging method the most according to claim 1, it is characterised in that: described mistake Effect divides threshold value and includes: described chip is divided into two grades: chip failing and not losing efficacy Chip.

Wafer-level packaging method the most according to claim 6, it is characterised in that: described mistake Effect divides threshold value and can farther include: described chip failing is divided into two grades: first The direct current failure level of level and the disabler grade of the second level.

Wafer-level packaging method the most according to claim 7, it is characterised in that: described step Rapid D) farther include: first the direct current failure level of the first order is carried out step D) in Pairing process thus obtain first order optimum matching method, then the disabler grade to the second level Carry out step D) pairing process thus obtain second level optimum matching method.

Wafer-level packaging method the most according to claim 8, it is characterised in that: according to institute State first order optimum matching method according to step E) carry out bonding encapsulation；According to the described second level Excellent matching method is according to step E) carry out bonding encapsulation.