CN103718244A - Acquisition method and device for media processing accelerator - Google Patents

Abstract

Apparatus, systems, and methods are described including dividing cache lines into at least a most significant portion and a next most significant portion, storing cache line contents in a register array such that the most significant portion of each cache line is stored in a first row of the register array and the next most significant portion of each cache line is stored in a second row of the register array. The contents of the first register portion of the first row may be provided to a barrel shifter, where the contents may be aligned and then stored in a buffer.

Description

Acquisition method and device for media processing accelerator

Background technique

Video planes are usually stored in memory in a block format to improve memory controller efficiency. Video processing algorithms often require access to a 2D region of interest (ROI) of arbitrary rectangular size at an arbitrary location within these video planes. These arbitrary locations may be cache-unaligned, and may span several non-adjacent cache lines and/or tiles. To acquire a pixel from such a location, traditional approaches can overfetch several cache lines of pixel data from memory, followed by swizzling, masking and downscaling operations, making the acquisition process challenging.

Power-efficient media processing is typically performed by programmable vector or scalar architectures, or by fixed-function logic. In a traditional vector implementation, the pixel values of an ROI can be captured using vector capture instructions, which typically include: collecting certain values from a line of pixel values from a cache line, masking out any invalid values, Values are stored in memory, additional pixel values for that row are collected from the next cache line, and the process is repeated until a complete horizontal row of pixel values has been collected. As a result, in order to satisfy the block format, a typical vector acquisition process often requires multiple retransmissions of the same cache line using different masks.

Description of drawings

The materials described herein are illustrated in the drawings by way of example and not limitation. For simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements. In the attached picture:

Figure 1 is a schematic diagram of an exemplary system;

Figure 2 illustrates an exemplary process;

Figure 3 illustrates an exemplary chunk store format;

Figure 4 illustrates an exemplary chunk store format;

Figures 5, 6 and 7 illustrate the exemplary system of Figure 1 in different environments;

Figure 8 illustrates an additional portion of the exemplary process of Figure 2;

Figure 9 illustrates the exemplary system of Figure 1 under overflow conditions; and

10 is a schematic diagram of an exemplary system, all arranged in accordance with at least some embodiments of the present disclosure.

Detailed ways

One or more embodiments are now described with reference to the figures. While specific structures and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the art will recognize that other structures and arrangements may be used without departing from the spirit and scope of the description. It will be apparent to those skilled in the art that the techniques and/or arrangements described herein may also be used in various other systems and applications than those described herein.

Although the following description sets forth various implementations that may occur within an architecture such as this System-on-Chip (SoC) architecture, implementations of the techniques and/or arrangements described herein are not limited to a particular architecture and/or computing system, can be implemented by any architecture and/or computing system serving a similar purpose. For example, using various architectures such as multiple integrated circuit (IC) chips and/or packages, and/or various computing devices, and/or various consumer electronics (CE) devices such as set-top boxes, smartphones, etc., may Implement the techniques and/or arrangements described herein. Furthermore, while the following description may set forth numerous specific details, such as logical implementations, types and interrelationships of system components, logical partitioning/integration options, etc., claimed subject matter may be practiced without such specific details. In other instances, for example, some material, such as control structures and full software instruction sequences, may not be shown in detail so as not to obscure material disclosed herein.

The material disclosed herein can be implemented in hardware, firmware, software, or any combination thereof. The material disclosed herein can also be implemented as instructions stored on a machine-readable medium, which can be read and executed by one or more processors. A machine-readable medium may include any medium and/or mechanism for storing or transmitting information in a form readable by a machine (eg, a computing device). For example, a machine-readable medium may include: read-only memory (ROM); random-access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; , infrared signal, digital signal, etc.), and other media.

References in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," etc. mean that the described implementations may include a particular feature, structure, or characteristic, but that every implementation need not include the particular feature, structure, or characteristic. character, structure or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with one embodiment, it should be within the knowledge of those skilled in the art that such feature, structure, or characteristic would function in other related embodiments, regardless of the context herein. Is it clearly stated in .

FIG. 1 illustrates an exemplary implementation of an acquisition engine 100 according to the present disclosure. In various implementations, capture engine 100 may form at least a portion of a media processing accelerator. Acquisition engine 100 includes register array 102 , barrel shifter 104 , two acquisition register buffers (GRB) 106 and 108 , and multiplexer (MUX) 110 . Register array 102 includes a plurality of tetris registers 112 , 114 , 116 , 118 , and 120 having a plurality of register storage locations or sections 122 . In various implementations, a Tetris register according to the present disclosure may be any temporary storage logic, such as processor register logic configured as byte tagged or enabled.

According to the present disclosure, the capture engine 100 may be used to capture video data from a region of interest (ROI) of a video surface stored in a memory such as a cache (eg L1 cache). In various embodiments, the ROI may include any type of video data, such as pixel intensity values and the like. In various implementations, the engine 100 may be configured to store the contents of a plurality of cache lines (CLs) received from a cache (not shown) across Tetris registers 112-120 of the array 102 Each cache line (eg, CL1, CL2, etc.) is stored in a portion 122 of the corresponding one. In various implementations, the first portion of the Tetris registers may constitute the first row 124 of the array 102, the second portion of the Tetris registers may constitute the second row 126 of the array, and so on.

According to the present disclosure, cache line contents may be stored in array 102 such that a different portion of the content of each CL is stored in a different portion of a corresponding one of the Tetris registers. For example, in various embodiments, the most significant portion of CL1 may be stored in the first portion 128 of the Tetris register 112, the most significant portion of CL2 may be stored in the first portion 130 of the Tetris register 114, and so on. The next most significant portion of CL1 may be stored in the second portion 132 of the Tetris register 112, the next most significant portion of CL2 may be stored in the second portion 134 of the Tetris register 114, and so on.

According to the present disclosure, the number of rows of array 102 may match the number of octal words (OW) in a cache line to be processed, while the number of columns of array 102 (and thus the number of Tetris registers employed ) can match the number of cache lines OW plus one. In the example of FIG. 1, the engine 100 may be configured to capture 64-byte cache lines such that each Tetris register includes four sections 122 to store four 16-byte cache lines for the corresponding cache line. OW portion, and thus array 102 includes four rows. For example, the most significant OW for CL1 may be stored in section 128 of Tetris register 112, the next most significant OW for CL1 may be stored in section 132 of register 112, and so on. As will be explained in more detail below, in order to accommodate and handle misaligned and/or overflowing cache line contents, an acquisition engine according to the present disclosure may include more Tetris registers than are required to store cache line OW Number of Tetris registers at least one more. For example, to handle a 64-byte cache line with four OWs, array 102 includes five Tetris registers 112-120 such that each row of array 102 spans a total of 80 bytes in width.

The barrel shifter 104 can receive the contents of any row of the register 102 . For example, barrel shifter 104 may be a 64 byte barrel shifter configured to receive the contents of row 124 corresponding to the most significant portion of the five cache lines stored in array 102 . In various implementations, as will be explained in more detail below, barrel shifter 104 may align the contents of register section 122 by, for example, left shifting them, and may then provide the aligned contents to GRB 106 or GRB 108 . For example, barrel shifter 104 may receive the contents of portion 122 of row 124 in successive iterations, align those contents, and provide the aligned contents to GRB 106 . For example, barrel shifter 104 may receive the contents of register section 128 , may align those contents, and then provide the aligned data to GRB 106 . Barrel shifter 104 may then receive the contents of register section 130, may align those contents and then provide the aligned data to GRB 106 for temporary storage adjacent to the aligned data corresponding to register section 128, so By analogy, until the content of line 124 is aligned with and stored in GRB 106 , an aligned line of pixel data is generated.

When the engine 100 processes the contents of row 124 as just described, the engine 100 can also process the contents of row 126 in a similar manner until the contents of row 126 are aligned with and stored in RGB108 to generate a pixel value The second justifies the row. In various implementations, as explained in more detail below, GRB 106 and GRB 108 may provide aligned lines of pixel data to a 2D register file (not shown) in a reciprocating manner using MUX 110 to alternately provide the contents of GRB 106 and GRB 108 to the register file (RF).

In various implementations, capture engine 100 may be implemented in one or more integrated circuits (ICs), such as add-on ICs for system-on-chip (SoC) and consumer electronics (CE) media processing systems. For example, engine 100 may be implemented by any device configured to process video data, such as, but not limited to, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), digital signal processors (DSPs), etc. . As noted above, although engine 100 includes five Tetris registers 112-120 suitable for processing a 64-byte cache line, acquisition engines according to the present disclosure may include An arbitrary number of Tetris registers of ROI size.

FIG. 2 illustrates a flowchart of an exemplary process 200 for implementing acquisition operations in accordance with various implementations of the present disclosure. Process 200 may include one or more operations, functions or actions as illustrated by one or more of blocks 201 , 202 , 204 , 206 , 208 , 210 , and 212 of FIG. 2 . By way of non-limiting example, process 200 will be described herein with reference to the exemplary acquisition engine 100 of FIG. 1 . Process 200 may begin at block 201, where the acquisition process for an ROI of a video plane begins. For example, process 200 may begin at block 201 , where acquisition processing begins for a 64x64 ROI (eg, the ROI spans 64 rows, each row having 64 bytes of pixel values).

At block 202, a first cache line (CL) may be received, wherein the CL corresponds to a first CL of data contained in a ROI. At block 204, the CL may be partitioned into the most significant portion, the next most significant portion, and so on. For example, if a 64-byte CL is received at block 202, the CL can be divided into four 16-byte OW sections. The CL portion may then be loaded into the register array so that the most significant portion is stored in the first location of the first row of the array, the next most significant portion is stored in the first location of the second row of the array, and so on. For example, the 64 bytes CL (CL1) received by array 102 may be divided into four OWs and loaded into register section 122 of first Tetris register 112 so that the most significant OW is stored in section 128, the next most significant OW is stored in section 132, and so on.

At block 208, a determination is made as to whether additional cache lines of data are to be obtained for the ROI. If additional CLs are to be obtained, the process 200 can loop back and proceed to blocks 202-206 for the next CL in the ROI. For example, the next 64 bytes CL (CL2) may be received by array 102, divided into four OWs and loaded into register section 122 of second Tetris register 114, so that the most significant OW is stored in section 130, the next highest Effective OWs are stored in section 134, and so on. In this manner, process 200 may continue to loop through successive iterations of blocks 202 - 206 until one or more additional CLs of the ROI are loaded into array 102 . For example, continuing the example above until three more CLs (e.g., CL3, CL4, and CL5) of the ROI can be received by the array 102, similarly divided into four OWs and loaded into the remaining Tetris registers 116, 118, and 120 in the register section 122 of the

3 and 4 illustrate exemplary tile-y formats for storing video planes in a tile store according to various embodiments of the present disclosure. In FIG. 3, a 4KB block 300 of memory may include eight (8) columns by thirty-two (32) rows of 16 byte wide storage locations. In block-y format, block 300 may store four OWs of 64 bytes CL 302 as the first part of the column of block 300 . In this manner, bank 300 can store sixty-four (64) cache lines of data. In FIG. 4, a block 300 is shown spanning a portion of a region 400 of memory, such as a cache memory. With reference to process 200 and engine 100 , successive reciprocations of blocks 202 - 206 to load the CL of the ROI may include sequentially loading cache lines 402 - 410 of block 300 into array 102 .

Returning to the discussion of FIG. 2, when one or more CLs of the ROI have been loaded into the register array, process 200 may continue at block 210, where, for each successive portion of the first row of the array, the The section is loaded into the barrel shifter, aligning the contents of the section if necessary. For example, block 210 may include loading the contents of first portion 128 of row 124 into shifter 104 and then left shifting the data to align it to GRB 106 . In some implementations, block 210 may not include alignment content if the cache line was already aligned when it was loaded into the array at blocks 202-206. At block 212, the aligned first row of pixel values may be provided to a first acquisition buffer. For example, the aligned pixel value content of row 124 may be provided to GRB 106 from barrel shifter 104 .

For example, FIG. 5 illustrates engine 100 in an environment 500 performing blocks 210 and 212 of process 200 for a first register portion, according to various embodiments of the present disclosure. In environment 500 , as shown, five CLs of an ROI have been loaded into array 102 , where the contents of the ROI (shown by dashed markers) are not aligned relative to array 102 . In this example, the first CL of the ROI (eg, CL1 ) is loaded into the first Tetris register 112 such that each portion 122 of the Tetris register 112 includes an invalid portion 502 . According to the present disclosure, when block 210 is performed for the first register portion 128 of row 124, the contents of portion 128 are loaded into shifter 104 and shifted left such that when the content is provided to GRB 106 at block 210 , the data is aligned to GRB106 as shown.

Continuing with the example, FIG. 6 illustrates engine 100 in an environment 600 performing blocks 210 and 212 of process 200 for the next register section, according to various implementations of the present disclosure. In environment 600, block 210 and 212 so that the data is stored adjacent to the aligned data from portion 128 as shown. In this way, at the end of blocks 210 and 212, the fully aligned contents of row 124 may be stored in GRB 106, as shown in FIG. Engine 100 is instantiated in environment 700 where blocks 210 and 212 of process 200 are completed 124 .

Returning to the discussion of FIG. 2 , when the aligned contents of the first row have been loaded into the first capture buffer at block 212 , the process 200 may proceed with processing any additional rows of the register array. FIG. 8 shows a flow diagram of additional portions of an exemplary process 200 for implementing acquisition operations in accordance with various implementations of the present disclosure. Additional portions of process 200 may include one or more operations, functions or actions as illustrated by one or more of blocks 215 , 214 , 216 , 218 , 220 , and 222 of FIG. 8 . By way of non-limiting example, additional blocks of the process 200 will also be described herein with reference to the exemplary acquisition engine 100 of FIG. 1 . Process 200 may continue at block 214 of FIG. 8 .

At block 214, the contents of the portion of the second row of the array may be sequentially loaded into the barrel shifter, and the contents may be aligned if necessary. At block 215, the contents of the aligned register portion may be incorporated into a second capture buffer. For example, blocks 214 and 215 may include loading the contents of the first portion 132 of the second row 126 into the shifter 104, shifting the data left, loading the aligned data into the GRB 108, and shifting the contents of the second row 126 The contents of the second portion 134 of 1 are loaded into shifter 104, the data is shifted left, the aligned data is loaded into GRB 108 adjacent to the aligned data from portion 132, and so on until the second row of all parts. Thus, in this example, at the end of block 214 and block 215 , the aligned contents of second row 126 of register array 102 may be loaded into GRB 108 .

While block 214 and/or block 215 are in progress, at block 216 the aligned contents of the first row may be provided from the first register buffer to the 2D register file. For example, block 216 may include using MUX 110 to provide aligned first row data stored in GRB 106 to RF, where the data may be stored as first row data in RF. At block 218, the aligned contents of the second row may be provided to the RF from the second register buffer. For example, block 218 may include using MUX 110 to provide aligned second row data stored in GRB 108 to RF, where the data may be stored as second row data in RF.

Process 200 may continue at block 220, where additional rows of the register array are processed in a manner similar to that described above for the first two rows of the register array. Thus, for example, block 220 may cause the aligned contents of the three remaining rows of array 102 to be stored in RF as the next three rows of data, and processing of these rows of the array may be completed. At block 222, a determination may be made as to whether acquisition of more cache lines for the ROI should be made. For example, if the first iteration of process 200 has resulted in the acquisition of four rows of a 64x64 ROI, the acquisition operation may continue for the next four rows of the ROI. If acquisition operations are to continue for the ROI, process 200 may return to FIG. 2 and a second pass of process 200 may begin at block 201 for one or more additional cache lines of the ROI. Otherwise, if acquisition operations are not to continue, process 200 may end.

Although an implementation of the exemplary process 200, as shown in FIGS. Only a subset of all blocks shown are performed and/or in an order different from that shown. For example, in various implementations, block 216 of FIG. 8 may be performed before, during, and/or after either or both of blocks 214 and 215 . In addition, acquisition processing according to the present disclosure can be done for different filling stages of the register array, so that if at any one time, one or more rows of the register array are empty, then the ROI remaining can be processed as described herein. At the same time as the rows of the array of pixel values are loaded, those rows are loaded with the ROI pixel values from the cache.

Additionally, any one or more of the processes and/or blocks of Figures 2 and 8 may be performed in response to instructions provided by one or more computer program products. Such a program product may include a signal bearing medium providing instructions that, when executed by, for example, one or more processor cores, may provide the functionality described herein. A computer program product may be provided on any form of computer readable medium. Thus, for example, a processor including one or more processor cores may perform one or more of the blocks shown in FIGS. 2 and 8 in response to instructions conveyed to the processor by a computer-readable medium.

Furthermore, while process 200 has been described herein in the context of an exemplary capture engine 100 that captures a 64-byte cache line for a 64x64 ROI of a video plane stored in tile-y format in the cache , but the present disclosure is not limited to a particular size of cache line, size or shape of ROI, and/or a particular block memory format. For example, to enable acquisition processing for ROIs having a width greater than 64 bytes, one or more additional Tetris registers may be added to the register array. Also, for smaller width ROIs, such as a 32x64 ROI, the first two rows of the array can be collected into the acquisition buffer before being written out to RF. Additionally, other chunk memory formats, such as chunk-x, can be captured in accordance with this disclosure.

In various embodiments, one or more processor cores may use the engine 100 to process the process 200 data for any size and/or shape of the ROI and for any alignment of the ROI data relative to the engine 100 . In doing so, processor throughput may depend on the size, shape and/or alignment of the ROI. For example, in a non-limiting example, if the ROI to be acquired is stretched in the X direction (e.g., as a row of pixel values in block-y format) and perfectly aligned, a cache can be processed in two loops Wire. In this environment, throughput is limited by the cache memory width. On the other hand, if the ROI is stretched in the Y direction (e.g., as a column of pixel values in block-y format) and perfectly aligned, then one cache line can be processed in 64 cycles. In another non-limiting example, for a fully misaligned 17x17 ROI, one cache line can be processed in 12 cycles. In a final non-limiting example, pixel values for an aligned 24x24 ROI may be acquired in 50 cycles, whereas if the 24x24 ROI is not aligned at all, it may take 81 cycles to acquire all pixel values.

In various embodiments, acquisition processes according to the present disclosure may be performed under overflow conditions. For example, referring to exemplary acquisition engine 100 , in some implementations, the ROI may exceed the width of barrel shifter 104 and GRBs 106 and 108 . FIG. 9 illustrates engine 100 in an environment 900 in which process 200 is performed under overflow conditions, according to various implementations of the present disclosure. As shown in FIG. 9 , after filling GRB 106 with most of the first row, overflow data 902 remaining from the first row can be placed into GRB 108 . Processing of the remaining rows may continue in a similar manner.

architecture(IA)的计算平台或SoC。本领域技术人员易于理解，在不脱离本公开内容的范围的情况下，本文所描述的实施方式可以应用于替换的处理系统。FIG. 10 illustrates an example system 1000 according to the present disclosure. The system 1000 may be configured to perform some or all of the various functions discussed herein, and may include any device or collection of devices capable of acquisition and processing according to various embodiments of the present disclosure. For example, system 1000 may include components of selected computing platforms or devices such as desktop computers, mobile or tablet computers, smartphones, set-top boxes, etc., but the disclosure is not limited thereto. In some implementations, the system 1000 may be based on a CE device

architecture (IA) computing platform or SoC. Those skilled in the art will readily appreciate that the embodiments described herein may be applied to alternative processing systems without departing from the scope of the present disclosure.

System 1000 includes a processor 1002 having one or more processor cores 1004 . Processor core 1004 may be any type of processor logic capable of executing software and/or processing data signals, at least in part. In various examples, processor core 1004 may include a CISC processor core, a RISC microprocessor core, a VLIW microprocessor core, and/or any number of processor cores implementing any combination of instruction sets, or such as digital signal Any other processor device like a processor or microcontroller. In various implementations, one or more processor cores 1004 may implement an acquisition engine and/or perform acquisition processing in accordance with the present disclosure.

Processor 1002 also includes a decoder 1006, which may be used to decode instructions received by, for example, display processor 1008 and/or graphics processor 1010 into control signals and/or microcode entry points. Although illustrated in system 1000 as a separate component from cores 1004 , one skilled in the art will appreciate that one or more cores 1004 may implement decoder 1006 , display processor 1008 and/or graphics processor 1010 . In response to the control signals and/or microcode entry points, the display processor 1008 and/or the graphics processor 1010 may perform corresponding operations.

Processing core 1004, decoder 1006, display processor 1008, and/or graphics processor 1010 may be communicatively and/or operably coupled via system interconnect 1016 to each other and/or to various other system devices that Devices may include, but are not limited to, memory controller 1014 , audio controller 1018 and/or peripherals 1020 , for example. Peripherals 1020 may include, for example, a Universal Serial Bus (USB) host port, a Peripheral Component Interconnect (PCI) Express port, a Serial Peripheral Interface (SPI), an expansion bus, and/or other peripherals. Although FIG. 10 illustrates memory controller 1014 as being coupled to decoder 1006 and processors 1008 and 1010 by interconnect 1016, in various implementations, memory controller 1014 may be directly coupled to decoder 1006, display processor 1008, and/or graphics processor 1010 .

In some implementations, system 1000 can communicate with multiple I/O devices not shown in FIG. 10 via an I/O bus (not shown). Such I/O devices may include, but are not limited to, for example, Universal Asynchronous Receiver/Transmitter (UART) devices, USB devices, I/O expansion interfaces, or other I/O devices. In various implementations, system 1000 can represent at least a portion of a system for mobile, network, and/or wireless communications.

System 1000 may further include memory 1012 . Memory 1012 may be one or more discrete memory components, such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, or other memory devices. Memory 1012 may store instructions and/or data represented by data signals, which may be executed by processor 1002 . In some implementations, memory 1012 may include a system memory portion and a display memory portion. In various implementations, the memory 1012 may store video data, such as frames of video data including pixel values that may be stored at various junctures as captured by the engine 100 and/or processed by the process 200 cache line.

Although FIG. 10 illustrates memory 1012 external to processor 1002, in various implementations, processor 1002 includes one or more instances of internal cache memory 1024, such as an L1 cache. According to the present disclosure, cache 1024 may store video data, such as pixel values, in the form of cache lines arranged in a block-y format. Processor core 1004 may access data stored in cache memory 1024 to implement the acquisition functions described herein. Additionally, the cache memory 1024 may provide a 2D register file, which stores the aligned data output of the engine 100 and process 200 . In various implementations, cache memory 1024 may receive video data, such as pixel values, from memory 1012 .

The systems described above, and the processes performed by the systems as described herein, may be implemented in hardware, firmware, or software, or any combination thereof. Additionally, any one or more features disclosed herein can be implemented in hardware, software, firmware, and combinations thereof, including discrete and integrated circuit logic, application-specific integrated circuit (ASIC) logic, and microcontrollers, and can be implemented in Part of a domain-specific integrated circuit package, or combination of integrated circuit packages. The term software as used herein refers to a computer program product comprising a computer readable medium having computer program logic stored therein to cause a computer system to perform one or more features and/or combinations of features disclosed herein .

While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Accordingly, various modifications of the embodiments described herein, as well as other embodiments, which are apparent to those skilled in the art to which the invention pertains are considered to be within the spirit and scope of the present disclosure.

Claims (19)

1. A device for collecting pixel values, comprising: a plurality of Tetris registers arranged as a register array, each Tetris register comprising at least a first register portion and a second register portion, wherein the first row of the register array comprises each said first register portion of a Tetris register, said register array to store a plurality of cache lines of pixel values such that said first row of said register array stores the most significant part; a barrel shifter to receive the most significant portion of the plurality of cache memory lines from the first row of the register array as first row pixel values, the barrel shifter to aligning said first row of pixel values; and A first buffer for receiving aligned first row pixel values from the barrel shifter. 2. The apparatus of claim 1 , wherein a second row of the register array includes the second register portion of each Tetris register, the register array storing the plurality of high-speed registers of pixel values. buffering memory lines such that a second row of said register array stores the next most significant portion of each of said cache memory lines, said barrel shifter to receive all cache memory lines from said second row of said register array The next most significant part of the plurality of cache memory lines is used as the pixel value of the second row, and the barrel shifter is used to align the pixel value of the second row, and the device further includes: A second buffer for receiving the aligned second row of pixel values from the barrel shifter. 3. The apparatus of claim 1, further comprising: a multiplexer coupled to the first buffer and the second buffer; and a register file coupled to the multiplexer, wherein the multiplexer is configured to provide either the aligned first row pixel values or the aligned second row pixel values to The register file, wherein the register file is configured to store the aligned second row of pixel values adjacent to the aligned first row of pixel values. 4. The apparatus of claim 1, wherein the most significant portion of each cache line comprises a row of pixel data in block-y format. 5. The apparatus of claim 1 , wherein each cache memory line comprises 64 bytes of pixel values, wherein the plurality of Tetris registers comprises at least five Tetris registers, wherein each Tetris The square registers are each configured to store 64-byte pixel values, and wherein both the first register portion and the second register portion are configured to store 16-byte pixel values. 6. The apparatus of claim 1, wherein, to align the first row of pixel values, the barrel shifter is configured to left shift the first row of pixel values. 7. A computer implemented method comprising: receiving multiple cache lines; dividing each cache line into at least a most significant portion and a next most significant portion; storing the contents of the plurality of cache lines in a register array such that the most significant portion of each cache line is stored in a first row of the register array, the first row comprising a first plurality of register sections; providing the contents of a first register portion of the first plurality of register portions to a barrel shifter; aligning the contents of the first register portion of the first plurality of register portions; and The aligned contents of the first register portion of the first plurality of register portions are stored in a first buffer. 8. The method of claim 7 , wherein storing the contents of the plurality of cache memory lines in the register array comprises storing the contents of the plurality of cache memory lines in the register array , such that the next most significant portion of each cache line is stored in a second row of the register array, the second row comprising a second plurality of register portions, the method further comprising: providing the contents of a first register portion of the second plurality of register portions to a barrel shifter; aligning the contents of the first register portion of the second plurality of register portions; and The aligned contents of the first register portion of the second plurality of register portions are stored in a second buffer. 9. The method of claim 8, further comprising: Providing the aligned contents of the first register portion of the first plurality of register portions prior to providing the aligned contents of the first register portion of the second plurality of register portions to a register file to the register file. 10. The method of claim 7, wherein the register array includes a plurality of Tetris registers. 11. The method of claim 10, wherein the plurality of Tetris registers are arranged such that a first portion of each Tetris register stores the most significant part. 12. The method of claim 7 , wherein aligning the contents of the first register portion of the first plurality of register portions comprises left shifting the first register portion of the first plurality of register portions Content. 13. A system for collecting pixel values comprising: a cache memory to store a plurality of cache memory lines of pixel values; an acquisition engine coupled to the cache memory; and an additional memory coupled to the acquisition engine, wherein instructions in the additional memory configure the acquisition engine to receive the plurality of cache lines from the cache memory, the acquisition engine comprising : a plurality of Tetris registers arranged as a register array, each Tetris register comprising at least a first register portion and a second register portion, wherein the first row of the register array comprises each said first register portion of a Tetris register, said register array to store said plurality of cache lines such that said first row of said register array stores the most significant portion of each cache line ; a barrel shifter to receive the most significant portion of the plurality of cache memory lines from the first row of the register array as first row pixel values, the barrel shifter to aligning said first row of pixel values; and A first buffer for receiving aligned first row pixel values from the barrel shifter. 14. The system of claim 13 , wherein a second row of the register array includes the second register portion of each Tetris register, the register array to store the plurality of cache lines , such that the second row of the register array stores the next most significant portion of each of the cache lines, the barrel shifter is configured to receive the The next most significant portion of the plurality of cache memory lines is used as a second row of pixel values, the barrel shifter aligns the second row of pixel values, and the acquisition engine further includes: A second buffer for receiving the aligned second row of pixel values from the barrel shifter. 15. The system according to claim 14, further, the acquisition engine further comprising: a multiplexer coupled to the first buffer and the second buffer; and a register file coupled to the multiplexer, wherein the multiplexer is configured to provide either the aligned first row pixel values or the aligned second row pixel values to The register file, wherein the register file is configured to store the aligned second row of pixel values adjacent to the aligned first row of pixel values. 16. The system of claim 13, wherein the cache is configured to store cache lines in block-y format. 17. The system of claim 13 , wherein each cache memory line includes 64 bytes of pixel values, wherein the plurality of Tetris registers includes at least five Tetris registers, wherein each Tetris The square registers are both configured to store 64-byte pixel values, and wherein both the first register part and the second register part are configured to store 16-byte pixel values. 18. The system of claim 13, wherein, to align the first row of pixel values, the barrel shifter is configured to left shift the first row of pixel values. 19. The system of claim 13 , said additional memory to store video data and to provide a portion of said video data to said cache memory for storage as said plurality of cache memory lines .

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