CN103681498B - A kind of manufacture method of semiconductor device - Google Patents

Abstract

The invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, the semiconductor substrate including an NMOS region and a PMOS region; sequentially forming an oxide layer and a polysilicon layer on the semiconductor substrate; removing all A polysilicon layer on the PMOS region; forming an amorphous germanium telluride layer on the semiconductor substrate; forming a dummy gate structure in the PMOS region; forming a dummy gate structure in the NMOS region; forming sidewall structures on both sides of the dummy gate structure; forming a stress material layer on the semiconductor substrate to cover the dummy gate structure, and performing an annealing process; removing the stress material layer; removing the For the dummy gate structure, a gate trench is formed between the sidewall structures. According to the present invention, the stress memory technology does not need to be implemented separately for the NMOS region and the PMOS region, thereby eliminating the process of forming and removing a mask, shortening the production time and reducing the manufacturing cost.

Description

A method of manufacturing a semiconductor device

technical field

The invention relates to a semiconductor manufacturing process, in particular to an implementation method of a stress memory technology (SMT) for a high-k-metal gate process.

Background technique

For the semiconductor manufacturing process with nodes below 65nm, stress memory technology is a method often used to improve the performance of NMOS. This technology improves the performance of NMOS by recrystallizing the polysilicon gate of the NMOS. The mechanism of the recrystallization of the polysilicon gate is as follows: Implement ion implantation in the semiconductor substrate on both sides of the polysilicon gate When an unactivated source/drain region is formed, the polysilicon gate is amorphized; when annealing is performed after forming a stress memory material layer covering the polysilicon gate on the semiconductor substrate, the unactivated The source/drain regions are activated, and at the same time, the polysilicon gate recrystallizes. During the recrystallization process of the polysilicon gate, due to the blocking of the stress memory material layer, the volume expansion of the polysilicon gate is suppressed, thereby transferring the stress of the stress memory material layer to the In a channel region in a semiconductor substrate, tensile stress is applied to the channel region to increase carrier mobility of the channel region.

For CMOS, before applying the above-mentioned stress memory technology to the NMOS part, a mask needs to be formed to shield the PMOS part, so as to avoid the decrease of carrier mobility in the channel region of the PMOS part. After implementing the above-mentioned stress memory technology, the mask needs to be removed. During the process of removing the mask, more damage will be caused to the sidewall structures on both sides of the gate structure of the NMOS part, and at the same time It is not conducive to simplification of the manufacturing process.

Therefore, a method needs to be proposed to solve the above problems.

Contents of the invention

Aiming at the deficiencies of the prior art, the present invention provides a method for manufacturing a semiconductor device, comprising: a) providing a semiconductor substrate, the semiconductor substrate including an NMOS region and a PMOS region; b) forming sequentially on the semiconductor substrate an oxide layer and a polysilicon layer; c) removing the polysilicon layer on the PMOS region; d) forming an amorphous germanium telluride layer on the semiconductor substrate; e) forming a dummy part of the PMOS region gate structure; f) forming a dummy gate structure in the NMOS region; g) forming sidewall structures on both sides of the dummy gate structure; h) forming a stress material layer on the semiconductor substrate to Covering the dummy gate structure and performing an annealing process; i) removing the stress material layer; j) removing the dummy gate structure to form gate trenches between the sidewall structures.

Further, the step b) is implemented by oxidation and chemical vapor deposition processes.

Further, the step c) includes: first forming a patterned photoresist layer to shield the polysilicon layer on the NMOS region; and then using a dry etching process to remove The polysilicon layer on the PMOS region; finally, the patterned photoresist layer is removed by an ashing process.

Further, the amorphous germanium telluride layer is formed by using a physical vapor deposition process or an atomic layer deposition process.

Further, the step e) includes: first forming a patterned photoresist layer to shield the middle part of the amorphous germanium telluride layer on the PMOS region; The rest of the amorphous germanium telluride layer and the rest of the oxide layer on the PMOS region covered by the photoresist layer; finally, the patterned photoresist layer is removed by an ashing process .

Further, the step f) includes: first forming a patterned photoresist layer to shield the middle of the polysilicon layer on the NMOS region and the PMOS region; The remaining part of the polysilicon layer on the NMOS region and the remaining part of the oxide layer on the NMOS region shielded by the photoresist layer; finally, the patterned photoresist layer is removed by an ashing process.

Further, the sidewall structure includes at least one oxide layer and/or at least one nitride layer.

Further, before implementing the step g), it also includes performing an ion implantation step to form inactive lightly doped source/drain regions in the semiconductor substrate on both sides of the dummy gate structure.

Further, after implementing step g), it also includes performing an ion implantation step again to form inactivated heavily doped source/drain regions in the semiconductor substrate on both sides of the dummy gate structure.

Further, the step i) is implemented by using a wet etching process.

Further, after implementing the step i), the method further includes the step of forming salicide on the source/drain regions on both sides of the sidewall structure.

Further, after forming the salicide, a step of forming a contact hole etching stop layer to at least cover the dummy gate structure is also included.

Further, after forming the contact hole etch stop layer, the following steps are also included: forming an interlayer dielectric layer to cover the contact hole etch stop layer; grinding the interlayer dielectric layer and the contact hole etch stop layer , to expose the top of the dummy gate structure.

Further, after implementing the step j), the following steps are further included: sequentially forming an interface layer, a high-k dielectric layer and a work function metal layer in the gate trench; performing backfilling of the metal gate; performing a A grinding process to remove the metal gate, work function metal layer, high-k dielectric layer and interfacial layer formed outside the gate trench.

According to the present invention, the stress memory technology does not need to be implemented separately for the NMOS region and the PMOS region, thereby eliminating the process of forming and removing the mask, shortening the production time and reducing the manufacturing cost.

Description of drawings

The following drawings of the invention are hereby included as part of the invention for understanding the invention. The accompanying drawings illustrate embodiments of the invention and description thereof to explain principles of the invention.

In the attached picture:

1A-1J are schematic cross-sectional views of each step of the implementation method of the stress memory technology for the high-k-metal gate process proposed by the present invention;

FIG. 2 is a flow chart of the implementation method of the stress memory technology for the high-k-metal gate process proposed by the present invention.

detailed description

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

In order to thoroughly understand the present invention, detailed steps will be provided in the following description to illustrate the implementation method of the stress memory technology for the high-k-metal gate process proposed by the present invention. Obviously, the practice of the invention is not limited to specific details familiar to those skilled in the semiconductor arts. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

It should be understood that when the terms "comprising" and/or "comprising" are used in this specification, they indicate the presence of the features, integers, steps, operations, elements and/or components, but do not exclude the presence or addition of one or Multiple other features, integers, steps, operations, elements, components and/or combinations thereof.

Next, with reference to FIG. 1A-FIG. 1J and FIG. 2, the detailed steps of the implementation method of the stress memory technology for the high-k-metal gate process proposed by the present invention will be described.

Referring to FIG. 1A-FIG. 1J , there are shown schematic cross-sectional views of various steps of the implementation method of the stress memory technology for the high-k-metal gate process proposed by the present invention.

First, as shown in FIG. 1A , a semiconductor substrate 100 is provided, and the constituent material of the semiconductor substrate 100 may be undoped single crystal silicon, single crystal silicon doped with impurities, silicon-on-insulator (SOI) or the like. As an example, in this embodiment, the semiconductor substrate 100 is made of single crystal silicon. An isolation structure 101 is formed in the semiconductor substrate 100, and the isolation structure 101 is a shallow trench isolation (STI) structure or a local oxide of silicon (LOCOS) isolation structure. In this embodiment, the isolation structure 101 is a shallow trench isolation structure, and the isolation structure 101 divides the semiconductor substrate 100 into an NMOS region and a PMOS region. Various well structures are also formed in the semiconductor substrate 100 , which are omitted in the illustration for simplicity.

Next, an oxide layer 102 and a polysilicon layer 103 are sequentially formed on the semiconductor substrate 100 . Various suitable processes familiar to those skilled in the art can be used to form the above two layers of materials, such as oxidation and chemical vapor deposition processes.

Next, as shown in FIG. 1B , the polysilicon layer 103 on the PMOS region is removed. The removal process includes: first forming a patterned photoresist layer to shield the polysilicon layer 103 on the NMOS region; The polysilicon layer 103 on the PMOS region; finally, the patterned photoresist layer is removed by an ashing process.

Next, an amorphous germanium telluride (GeTe) layer 104 is formed on the semiconductor substrate 100 . Forming the amorphous germanium telluride layer 104 can adopt various suitable processes familiar to those skilled in the art, such as physical vapor deposition process or atomic layer deposition process.

Next, as shown in FIG. 1C , a patterned photoresist layer 105 is formed to cover the middle of the amorphous GeTe layer 104 on the PMOS region.

Next, as shown in FIG. 1D , the rest of the amorphous germanium telluride layer 104 not covered by the patterned photoresist layer and the oxide layer on the PMOS region are removed by a dry etching process. 102 to form the dummy gate structure of the PMOS region.

Next, as shown in FIG. 1E, the dummy gate structure of the NMOS region is formed, and the formation process includes the following steps: first forming a patterned photoresist layer to shield the middle part of the polysilicon layer 103 on the NMOS region and The PMOS region; and then use a dry etching process to remove the rest of the polysilicon layer 103 on the NMOS region that is not shielded by the patterned photoresist layer and the oxide layer 102 on the NMOS region The rest; finally, the patterned photoresist layer is removed by an ashing process.

Next, as shown in FIG. 1F , sidewall structures 106 are formed on both sides of the dummy gate structure, wherein the sidewall structures 106 may include at least one oxide layer and/or at least one nitride layer. Before forming the sidewall structure 106, perform an ion implantation to form inactivated lightly doped source/drain regions 107a in the semiconductor substrate 100 on both sides of the dummy gate structure; After step 106, another ion implantation is performed to form inactivated heavily doped source/drain regions 107b in the semiconductor substrate 100 on both sides of the dummy gate structure.

Next, as shown in FIG. 1G , a stress material layer 108 is formed on the semiconductor substrate 100 to cover the dummy gate structure. Forming the stress material layer 108 may adopt various suitable processes familiar to those skilled in the art, such as chemical vapor deposition process or atomic layer deposition process. The stress material layer 108 can be made of various suitable materials familiar to those skilled in the art, such as silicon nitride.

Next, an annealing process is performed. During the annealing process, the dopant substances in the deactivated lightly doped source/drain region 107a and the deactivated heavily doped source/drain region 107b are activated, respectively transformed into activated lightly doped The impurity source/drain region 109a and the activated heavily doped source/drain region 109b, at the same time, the recrystallization of the polysilicon layer 103 in the dummy gate structure of the NMOS region produces a pull on the channel region of the NMOS region Stress, the recrystallization of the amorphous germanium telluride layer 104 in the dummy gate structure of the PMOS region will produce about 9.6% volume shrinkage, and then a compressive stress will be generated on the channel region of the PMOS region. In the present invention, other materials with high shrinkage ratio can also be used to replace the polysilicon as the dummy gate material of the PMOS region.

Next, as shown in FIG. 1H , the stress material layer 108 is removed. The removal process can adopt various suitable processes familiar to those skilled in the art, such as wet etching process.

Next, as shown in FIG. 1I , a salicide 110 is first formed on the source/drain regions on both sides of the sidewall structure 106 . In this embodiment, the step of forming the salicide 110 includes: forming a hard mask layer to cover the semiconductor substrate 100 and the dummy gate structure; using a dry etching process to remove the A hard mask layer above the source/drain region; a metal nickel (Ni) or nickel-platinum alloy (NiPt) layer is formed to cover the semiconductor substrate 100, and at the same time, the metal nickel layer or the nickel-platinum alloy layer can be forming a Ti/TiN protective layer; annealing the metal nickel layer or the nickel-platinum alloy layer, and then removing the unreacted metal nickel layer or nickel-platinum alloy layer and the hard mask layer.

Next, a contact etch stop layer (CESL) 111 is formed on the semiconductor substrate 100 to at least cover the dummy gate structure. The material of the contact hole etching stop layer 111 is usually silicon nitride (SiN). The process of forming the etch stop layer 111 for the contact hole may adopt a process known to those skilled in the art, and details will not be repeated here.

Then, a chemical vapor deposition process is used to form an interlayer dielectric layer 112 to cover the etch stop layer 111 of the contact hole. The material of the interlayer dielectric layer 112 is preferably oxide. Thereafter, the interlayer dielectric layer 112 and the contact hole etch stop layer 111 are ground to expose the top of the dummy gate structure.

Next, as shown in FIG. 1J , the dummy gate structure is removed, and a gate trench 113 is formed between the sidewall structures 106 . The removal process of the dummy gate structure is completed by using a conventional process, such as dry etching.

So far, all the process steps implemented by the method according to the exemplary embodiment of the present invention have been completed. Next, the manufacture of the entire semiconductor device can be completed through a subsequent process, which is exactly the same as the traditional semiconductor device processing process, including the following processes Step: sequentially form an interface layer, a high-k dielectric layer and a work function metal layer in the gate trench 113, wherein the material of the interface layer is silicon oxide, and the high-k dielectric layer Materials may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, etc., particularly preferred Hafnium oxide, zirconium oxide and aluminum oxide are preferred, and the work function metal layer may include one or more layers of metals, and its constituent materials include titanium nitride, titanium aluminum alloy and tungsten nitride; the metal gate is backfilled, and the The material of the metal gate is tungsten or aluminum, wherein the metal gate is backfilled by chemical vapor deposition or physical vapor deposition, and atomic layer deposition or physical vapor deposition can also be used before backfilling the metal gate The process sequentially forms a barrier layer and a wetting layer, the material of the barrier layer includes tantalum nitride and titanium nitride, the material of the wetting layer includes titanium or titanium aluminum alloy; a grinding process is performed to remove the layer formed on the Metal gate, work function metal layer, high-k dielectric layer and interfacial layer outside the gate trench.

According to the present invention, the gate material layer in the dummy gate structure of the NMOS region is a polysilicon layer, and the gate material layer in the dummy gate structure of the PMOS region is an amorphous germanium telluride layer. During the annealing process performed after covering the stress material layer of the dummy gate structure, the volume expansion effect generated when the polysilicon layer is recrystallized produces a tensile stress on the channel region of the NMOS region, and the amorphous The volume shrinkage effect produced during the recrystallization of the germanium telluride layer produces a compressive stress on the channel region of the PMOS region, and the two proceed simultaneously. Therefore, compared with the prior art, adopting the method proposed by the present invention does not need to implement stress memory technology for the NMOS region and the PMOS region respectively, thereby eliminating the process of forming and removing the mask and shortening the production time , to reduce manufacturing costs.

Referring to FIG. 2 , it shows a flow chart of the implementation method of the stress memory technology for the high-k-metal gate process proposed by the present invention, which is used to briefly illustrate the flow of the entire manufacturing process.

In step 201, a semiconductor substrate is provided, and the semiconductor substrate includes an NMOS region and a PMOS region;

In step 202, an oxide layer and a polysilicon layer are sequentially formed on the semiconductor substrate;

In step 203, removing the polysilicon layer on the PMOS region;

In step 204, an amorphous germanium telluride layer is formed on the semiconductor substrate;

In step 205, a dummy gate structure of the PMOS region is formed;

In step 206, forming a dummy gate structure in the NMOS region;

In step 207, sidewall structures are formed on both sides of the dummy gate structure;

In step 208, forming a stress material layer on the semiconductor substrate to cover the dummy gate structure, and performing an annealing process;

In step 209, removing the stress material layer;

In step 210, the dummy gate structure is removed, and a gate trench is formed between the sidewall structures.

The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the claimed scope of the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (14)

1. a manufacture method for semiconductor device, comprising:

A) provide Semiconductor substrate, described Semiconductor substrate comprises nmos area and PMOS district;

B) monoxide layer and a polysilicon layer is formed successively on the semiconductor substrate;

C) polysilicon layer in described PMOS district is removed;

D) an amorphous telluride germanium layer is formed on the semiconductor substrate;

E) form the dummy gate structure in described PMOS district, the dummy gate structure in described PMOS district is made up of described oxide skin(coating) stacked from bottom to top and described amorphous telluride germanium layer;

F) form the dummy gate structure of described nmos area, the dummy gate structure of described nmos area is made up of described oxide skin(coating) stacked from bottom to top and described polysilicon layer;

G) side wall construction is formed in the both sides of described dummy gate structure;

H) form a stress material layer on the semiconductor substrate, to cover described dummy gate structure, and perform an annealing process;

I) described stress material layer is removed;

J) remove described dummy gate structure, between described side wall construction, form gate groove.

2. method according to claim 1, is characterized in that, adopts oxidation and chemical vapor deposition method to implement described step b).

3. method according to claim 1, is characterized in that, described step c) comprising: first form the photoresist layer of a patterning to cover the polysilicon layer on described nmos area; Adopt again dry method etch technology remove not by the photoresist layer of described patterning polysilicon layer in the described PMOS district of covering; Finally, cineration technics is adopted to remove the photoresist layer of described patterning.

4. method according to claim 1, is characterized in that, adopts physical gas-phase deposition or atom layer deposition process to form described amorphous telluride germanium layer.

5. method according to claim 1, is characterized in that, described step e) comprising: first form the photoresist layer of a patterning to cover the middle part of the amorphous telluride germanium layer in described PMOS district; Adopt again dry method etch technology remove not by the photoresist layer of described patterning the remainder of oxide skin(coating) in the remainder of amorphous telluride germanium layer that covers and described PMOS district; Finally, cineration technics is adopted to remove the photoresist layer of described patterning.

6. method according to claim 1, is characterized in that, described step f) comprising: first form the photoresist layer of a patterning to cover the middle part of the polysilicon layer on described nmos area and described PMOS district; Adopt again dry method etch technology remove not by the photoresist layer of described patterning the remainder of oxide skin(coating) on the remainder of polysilicon layer on the described nmos area of covering and described nmos area; Finally, cineration technics is adopted to remove the photoresist layer of described patterning.

7. method according to claim 1, is characterized in that, described side wall construction comprises at least one oxide skin(coating) and/or at least one nitride layer.

8. method according to claim 1, is characterized in that, in the described step g of enforcement) before, also comprise the step of execution one ion implantation, to form unactivated light dope source/drain region in the Semiconductor substrate of described dummy gate structure both sides.

9. method according to claim 1, is characterized in that, in the described step g of enforcement) after, also comprise the step again performing an ion implantation, to form unactivated heavy doping source/drain region in the Semiconductor substrate of described dummy gate structure both sides.

10. method according to claim 1, is characterized in that, adopts wet etching process to implement described step I).

11. methods according to claim 1, is characterized in that, in the described step I of enforcement) after, the source/drain region being also included in described side wall construction both sides is formed the step of self-aligned silicide.

12. methods according to claim 11, is characterized in that, after the described self-aligned silicide of formation, also comprise formation one contact etch stop layer, at least to cover the step of described dummy gate structure.

13. methods according to claim 12, is characterized in that, after the described contact etch stop layer of formation, further comprising the steps of: to form an interlayer dielectric layer, to cover described contact etch stop layer; Grind described interlayer dielectric layer and described contact etch stop layer, to expose the top of described dummy gate structure.

14. methods according to claim 1, is characterized in that, at the described step j of enforcement) after, further comprising the steps of: in described gate groove, to form a boundary layer, a high k dielectric layer and a workfunction layers successively; Implement the backfill of metal gate; Perform a process of lapping, to remove the metal gate, workfunction layers, high k dielectric layer and the boundary layer that are formed in described gate groove outside.