CN103684380B - Switched capacitor circuit - Google Patents

Abstract

The invention discloses a switched capacitor circuit, comprising: a charging capacitor module, a discharging capacitor module, a boost multiple control module, a charging control module and a discharging control module; in the charging stage, the boost multiple control module can control the charging capacitor module to have Different capacitance values, therefore, under the control of the boost multiple control module, the charging control module charges the first input signal of the signal input terminal into the charging capacitor module, so that the charging capacitor module has different charge amounts, and then, when the discharge control module When the charging capacitor module is controlled to charge the discharging capacitor module, the discharging capacitor modules have different voltages, so that the switch capacitor circuit has different boosting ranges. However, in the existing switched capacitor circuit, only one boosting range can be realized by using one charging capacitor module and one discharging capacitor module. Therefore, compared with the existing circuit, the switched capacitor circuit can reduce the chip area and reduce the power consumption of the switched capacitor circuit.

Description

A switched capacitor circuit

technical field

The invention relates to the technical field of integrated circuits, in particular to a switched capacitor circuit.

Background technique

At present, with the continuous development of integrated circuit technology, the operating voltage of the chip is getting lower and lower. Usually, the driving voltage of the integrated circuit is higher than the working voltage of the chip. In order to make the working voltage of the chip meet the driving voltage of the integrated circuit, a boost circuit is needed to realize it. The charge pump circuit used as a boost circuit in the integrated circuit It is usually realized by using a switched capacitor circuit (Switched Capacitor Circuits referred to as SC circuit). The switched capacitor circuit is a circuit composed of a switching device and a capacitor controlled by a clock signal. It uses the storage and transfer principle of the capacitor charge to realize the boost function of the circuit. However, the power consumption of the switched capacitor circuit used in the integrated circuit occupies a large proportion in the total power consumption of the integrated circuit. Therefore, with people's requirements for low power consumption of electronic products, reducing the power consumption of switched capacitor circuits has become an urgent problem to be solved by those skilled in the art.

Contents of the invention

A switched capacitor circuit provided by an embodiment of the present invention is used to realize a low power consumption switched capacitor circuit.

A switched capacitor circuit provided by an embodiment of the present invention includes: a charging capacitor module, a discharging capacitor module, a boost multiple control module, a charging control module, and a discharging control module; wherein,

In the charging stage: the charging control module receives the first input signal sent by the signal input terminal and the second input signal sent by the reference signal terminal, which are respectively output to the first terminal and the second terminal of the charging capacitor module, for all charging the charging capacitor module; and,

When the boost multiple control module receives the first input signal and the second input signal when the first input signal is lower than the set threshold voltage, they respectively output to the third terminal of the charging capacitor module and the fourth terminal, to charge the charging capacitor module; when the first input signal is greater than or equal to the set threshold voltage, the boost multiple control module turns on the third terminal of the charging capacitor module and fourth end;

In the discharge phase: the discharge control module receives the first input signal, and outputs the first input signal to the second terminal and the fourth terminal of the charging capacitor module; and connects the first input signal to the charging capacitor module One end and the third end are connected to the first end and the signal output end of the discharge capacitor module, so that the charge capacitor module charges the discharge capacitor module and outputs a signal through the signal output end; wherein the The second terminal of the discharge capacitor module receives the second input signal.

The switched capacitor circuit provided by the embodiment of the present invention includes: a charging capacitor module, a discharging capacitor module, a boost multiple control module, a charging control module and a discharging control module. Since in the charging phase, the boost multiple control module can control the charging capacitor module to have different capacitance values, therefore, under the control of the boost multiple control module, the charging control module charges the first input signal sent by the signal input terminal into the charging capacitor Modules can make the charging capacitor modules have different charge amounts, and furthermore, because the charging capacitor modules have different charge amounts, so in the discharge stage, when the discharge control module controls the charging capacitor module to charge the discharge capacitor module, the discharge capacitor can be made The modules have different voltages, and the voltages output from the signal output terminals are also different, so that the switch capacitor circuit has different boosting ranges. However, in the existing switched capacitor circuit, one charging capacitor module and one discharging capacitor module can only realize one boosting range, that is, to realize different boosting ranges, multiple switched capacitor circuits are required. Therefore, compared with the existing switched capacitor circuit, the switched capacitor circuit provided by the embodiment of the present invention can reduce the area of the chip and reduce the power consumption of the switched capacitor circuit.

Preferably, for the convenience of implementation, in the above-mentioned switched capacitor circuit provided by the embodiment of the present invention, the charging capacitor module specifically includes: a first capacitor and a second capacitor; wherein,

The first end of the first capacitor is the first end of the charging capacitor module, and the second end of the first capacitor is the fourth end of the charging capacitor module;

The first terminal of the second capacitor is the second terminal of the charging capacitor module, and the second terminal of the second capacitor is the third terminal of the charging capacitor module.

Preferably, for the convenience of implementation, in the above switched capacitor circuit provided by the embodiment of the present invention, the boost multiple control module specifically includes: a first switching device, a second switching device and a third switching device; wherein,

The input end of the first switching device is respectively connected to the input end of the second switching device and the second end of the first capacitor; the output end of the first switching device is connected to the reference signal end;

The input end of the third switching device is connected to the signal input end; the output end of the third switching device is respectively connected to the output end of the second switching device and the second end of the second capacitor;

In the charging phase, when the first input signal is less than the set threshold voltage, the second switching device is in the off state, the first switching device and the third switching device are in the on state, and the first capacitor It is connected in parallel with the second capacitor; in the charging stage, when the first input signal is greater than or equal to the set threshold voltage, the second switching device is in the conduction state, and the first switching device and the first switching device The three switching devices are in an off state, and the first capacitor and the second capacitor are in a series connection state;

In the discharge phase, the first switching device, the second switching device and the third switching device are in an off state.

Preferably, for the convenience of implementation, in the above switched capacitor circuit provided by the embodiment of the present invention, the charging control module specifically includes: a fourth switching device and a fifth switching device; wherein,

The input terminal of the fourth switching device is respectively connected to the signal input terminal and the input terminal of the third switching device; the output terminal of the fourth switching device is connected to the first terminal of the first capacitor;

The input end of the fifth switching device is connected to the first end of the second capacitor; the output end of the fifth switching device is connected to the reference signal end;

In the charging phase, the fourth switching device and the fifth switching device are in a conducting state; in the discharging phase, the fourth switching device and the fifth switching device are in an off state.

Preferably, in order to reduce the substrate current in the MOS transistor, thereby reducing the static power consumption of the switched capacitor circuit, in the above switched capacitor circuit provided by the embodiment of the present invention, the first switching device and the fifth switch The device is an N-type MOS tube; among them,

The source and the substrate of the N-type MOS transistor are respectively connected to a reference signal terminal, and the reference signal terminal is grounded.

Preferably, in order to reduce the substrate current in the MOS transistor, thereby reducing the static power consumption of the switched capacitor circuit, in the above switched capacitor circuit provided in the embodiment of the present invention, the second switching device, the third switch The device and the fourth switching device are N-type MOS transistors with a composite structure; wherein,

The N-type MOS transistor of the composite structure specifically includes: a first body potential selection transistor, a second body potential selection transistor and an N-type MOS transistor; wherein, the source of the N-type MOS transistor is connected to the first body potential selection transistor The source of the N-type MOS transistor is connected to the source of the second body potential selection transistor, and the substrate of the N-type MOS transistor is connected to the first body potential selection transistor and the second body potential selection transistor respectively. The drain of the first body potential selection transistor is connected to the substrate of the second body potential selection transistor.

Preferably, for the convenience of implementation, in the above switched capacitor circuit provided by the embodiment of the present invention, the discharge control module specifically includes: a sixth switching device, a seventh switching device, an eighth switching device and a ninth switching device ;in,

The input terminal of the sixth switching device is respectively connected to the signal input terminal and the input terminal of the seventh switching device; the output terminal of the sixth switching device is connected to the second terminal of the first capacitor;

The output end of the seventh switching device is connected to the first end of the second capacitor;

The input end of the eighth switching device is connected to the first end of the first capacitor; the output end of the eighth switching device is respectively connected to the output end of the ninth switching device and the first end of the discharge capacitor module. connected to the signal output terminal;

The input end of the ninth switching device is connected to the second end of the second capacitor;

In the charging stage, the sixth switching device, the seventh switching device, the eighth switching device and the ninth switching device are in the off state; in the discharging stage, the sixth switching device, the seventh switching device, the eighth switching device and the ninth switching device The switching device is in a conducting state.

Preferably, for the convenience of implementation, in the above switched capacitor circuit provided by the embodiment of the present invention, the sixth switching device, the seventh switching device, the eighth switching device and the ninth switching device are Metal-oxide-semiconductor MOS transistors with the same doping polarity.

Preferably, in order to reduce the substrate current in the MOS transistor, thereby reducing the static power consumption of the switched capacitor circuit, in the above switched capacitor circuit provided in the embodiment of the present invention, the sixth switching device, the seventh switch The device is a P-type MOS tube; among them,

The source electrode and the substrate of the P-type MOS transistor are respectively connected to the signal input end.

Preferably, in order to reduce the substrate current in the MOS transistor, thereby reducing the static power consumption of the switched capacitor circuit, in the above switched capacitor circuit provided by the embodiment of the present invention, the eighth switch device and the ninth switch The device is a P-type MOS transistor with a composite structure; among them,

The P-type MOS tube of the composite structure specifically includes: a first body potential selection tube, a second body potential selection tube and a P-type MOS tube; wherein the source of the P-type MOS tube is connected to the first body potential selection tube connected to the source, the drain of the P-type MOS transistor is connected to the source of the second body potential selection transistor, and the substrate of the P-type MOS transistor is connected to the first body potential selection transistor and the second body potential selection transistor respectively. The drain of the first body potential selection transistor is connected to the substrate of the second body potential selection transistor.

Preferably, for the convenience of implementation, in the above-mentioned switched capacitor circuit provided by the embodiment of the present invention, the discharge capacitor module specifically includes: a third capacitor; wherein,

The first end of the third capacitor is the second end of the discharge capacitor module, and the second end of the third capacitor is the first end of the discharge capacitor module.

Description of drawings

FIG. 1 is a schematic structural diagram of a switched capacitor circuit provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a switched capacitor circuit provided by an embodiment of the present invention;

FIG. 3a and FIG. 3b are respectively the working timing diagrams of the switched capacitor circuit provided by the embodiment of the present invention;

FIG. 4a is a schematic structural diagram of an N-type MOS transistor with a composite structure provided by an embodiment of the present invention;

Fig. 4b is a schematic structural diagram of a P-type MOS transistor with a composite structure provided by an embodiment of the present invention.

detailed description

The specific implementation manner of the switched capacitor circuit provided by the embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

A switched capacitor circuit provided by an embodiment of the present invention, as shown in FIG. 1 , includes: a charging capacitor module 1, a discharging capacitor module 2, a boost multiple control module 3, a charging control module 4, and a discharging control module 5; wherein,

In the charging stage: the charging control module 4 receives the first input signal sent by the signal input terminal Vin and the second input signal sent by the reference signal terminal Vref, which are respectively output to the first terminal Y1 and the second terminal Y2 of the charging capacitor module 1, charging the charging capacitor module 1; and,

When the first input signal is lower than the set threshold voltage, the boost multiple control module 3 receives the first input signal and the second input signal, which are respectively output to the third terminal Y3 and the fourth terminal Y4 of the charging capacitor module 1, for The charging capacitor module 1 is charged; when the first input signal is greater than or equal to the set threshold voltage, the boost multiple control module 3 turns on the third terminal Y3 and the fourth terminal Y4 of the charging capacitor module 1;

In the discharge stage: the discharge control module 5 receives the first input signal, and outputs the first input signal to the second terminal Y2 and the fourth terminal Y4 of the charging capacitor module 1; and connects the first terminal Y1 and the fourth terminal Y4 of the charging capacitor module 1 The three terminals Y3 are connected to the first terminal X1 of the discharge capacitor module 2 and the signal output terminal Vout, so that the charge capacitor module 1 charges the discharge capacitor module 2 and outputs a signal through the signal output terminal Vout; wherein the second terminal of the discharge capacitor module 2 Terminal X2 receives the second input signal.

The switched capacitor circuit provided by the embodiment of the present invention includes: a charging capacitor module, a discharging capacitor module, a boost multiple control module, a charging control module and a discharging control module. Since in the charging phase, the boost multiple control module can control the charging capacitor module to have different capacitance values, therefore, under the control of the boost multiple control module, the charging control module charges the first input signal sent by the signal input terminal into the charging capacitor Modules can make the charging capacitor modules have different charge amounts, and furthermore, because the charging capacitor modules have different charge amounts, so in the discharge stage, when the discharge control module controls the charging capacitor module to charge the discharge capacitor module, the discharge capacitor can be made The modules have different voltages, and the voltages output from the signal output terminals are also different, so that the switch capacitor circuit has different boosting ranges. However, in the existing switched capacitor circuit, one charging capacitor module and one discharging capacitor module can only realize one boosting range, that is, to realize different boosting ranges, multiple switched capacitor circuits are required. Therefore, compared with the existing switched capacitor circuit, the switched capacitor circuit provided by the embodiment of the present invention can reduce the area of the chip and reduce the power consumption of the switched capacitor circuit.

Specifically, in the above-mentioned switched capacitor circuit provided by the embodiment of the present invention, when the first input signal is lower than the set threshold voltage, in the charging phase: the charging control module 4 outputs the received first input signal to the charging capacitor module The first terminal Y1 of 1 charges the charging capacitor module 1; the charging control module 4 outputs the received second input signal to the second terminal Y2 of the charging capacitor module 1 to charge the charging capacitor module 1; the boost factor control The module 3 outputs the received first input signal to the third terminal Y3 of the charging capacitor module 1 to charge the charging capacitor module 1; the step-up multiple control module 3 outputs the received second input signal to the third terminal Y3 of the charging capacitor module 1 The four terminals Y4 charge the charging capacitor module 1 .

Preferably, for the convenience of implementation, in the above switched capacitor circuit provided by the embodiment of the present invention, as shown in FIG. 2 , the charging capacitor module 1 may specifically include: a first capacitor Cst1 and a second capacitor Cst2; wherein,

The first terminal m1 of the first capacitor Cst1 is the first terminal Y1 of the charging capacitor module 1, and the second terminal m2 of the first capacitor Cst1 is the fourth terminal Y4 of the charging capacitor module 1;

The first terminal n1 of the second capacitor Cst2 is the second terminal Y2 of the charging capacitor module 1 , and the second terminal n2 of the second capacitor Cst2 is the third terminal Y3 of the charging capacitor module.

Further, in the above switched capacitor circuit provided by the embodiment of the present invention, the capacitance values of the first capacitor Cst1 and the second capacitor Cst2 may be equal or unequal, which is not limited herein.

Specifically, during implementation, in the above-mentioned switched capacitor circuit provided by the embodiment of the present invention, the charging capacitor module may specifically include: a first capacitor and a second capacitor, and the first capacitor and the second capacitor can be controlled by the step-up multiple control module. For the total capacitance value of the second capacitor, the charging control module can charge the first input signal sent by the signal input terminal into the first capacitor and the second capacitor under the control of the boost multiple control module. Of course, the charging capacitor module may also be a plurality of capacitors capable of implementing the solution of the present invention, which is not limited here.

Preferably, for the convenience of implementation, in the above-mentioned switched capacitor circuit provided by the embodiment of the present invention, as shown in FIG. 2 , the discharge capacitor module 2 may specifically include: a third capacitor Cst3; wherein,

The first terminal o1 of the third capacitor Cst3 is the second terminal X2 of the discharge capacitor module 2 , and the second terminal o2 of the third capacitor Cst3 is the first terminal X1 of the discharge capacitor module 2 .

Specifically, during implementation, in the above-mentioned switched capacitor circuit provided by the embodiment of the present invention, the discharge capacitor module may specifically include: a third capacitor, so that the discharge control module can charge the voltage of the charge capacitor module to the third capacitor on, and output from the signal output. Of course, the discharge capacitor module may also be a plurality of capacitors capable of implementing the solution of the present invention, which is not limited here.

Specifically, during implementation, in the above switched capacitor circuit provided by the embodiment of the present invention, the reference signal terminal Vref is generally grounded, that is, the voltage of the second input signal sent by the reference signal terminal Vref is 0 volts.

Preferably, for the convenience of implementation, in the above-mentioned switched capacitor circuit provided by the embodiment of the present invention, as shown in FIG. and the third switching device S3; where,

The input terminal S1 _i of the first switching device S1 is respectively connected to the input terminal S2 _i of the second switching device S2 and the second terminal m2 of the first capacitor Cst1; the output terminal S1 _o of the first switching device S1 is connected to the reference signal terminal Vref ;

The input terminal S3 _i of the third switching device S3 is connected to the signal input terminal Vin; the output terminal S3 _o of the third switching device S3 is respectively connected to the output terminal S2 _o of the second switching device S2 and the second terminal n2 of the second capacitor Cst2 ;

In the charging phase, when the first input signal is less than the set threshold voltage, the second switching device S2 is in the off state, the first switching device S1 and the third switching device S3 are in the on state, and the first capacitor Cst1 and the second capacitor Cst2 is in parallel state; in the charging stage, when the first input signal is greater than or equal to the set threshold voltage, the second switching device S2 is in the on state, the first switching device S1 and the third switching device S3 are in the off state, and the second switching device S2 is in the off state. A capacitor Cst1 and a second capacitor Cst2 are connected in series;

In the discharge phase, the first switching device S1 , the second switching device S2 and the third switching device S3 are in an off state.

Specifically, in the specific implementation, in the above-mentioned switched capacitor circuit provided by the embodiment of the present invention, when the first input signal sent by the signal input terminal Vin is lower than the set threshold voltage, the second switching device S2 is in the off state during the charging phase , the first switching device S1 and the third switching device S3 are in a conduction state, and the first capacitor Cst1 and the second capacitor Cst2 are in a parallel state; in the discharge phase, the first switching device S1, the second switching device S2 and the third switching device S3 is closed.

When the first input signal sent by the signal input terminal Vin is greater than or equal to the set threshold voltage, in the charging phase, the second switching device S2 is in the on state, the first switching device S1 and the third switching device S3 are in the off state, The first capacitor Cst1 and the second capacitor Cst2 are connected in series; in the discharge phase, the first switching device S1 , the second switching device S2 and the third switching device S3 are in an off state.

Preferably, for the convenience of implementation, in the above switched capacitor circuit provided by the embodiment of the present invention, as shown in FIG. 2 , the charging control module 4 may specifically include: a fourth switching device S4 and a fifth switching device S5; ,

The input terminal S4 _i of the fourth switching device S4 is respectively connected to the signal input terminal Vin and the input terminal S3 _i of the third switching device S3; the output terminal S4 _o of the fourth switching device S4 is connected to the first terminal m1 of the first capacitor Cst1 connected;

The input terminal S5 _i of the fifth switching device S5 is connected to the first terminal n1 of the second capacitor Cst2; the output terminal S5 _o of the fifth switching device S5 is connected to the reference signal terminal Vref;

In the charging phase, the fourth switching device S4 and the fifth switching device S5 are in the on state; in the discharging phase, the fourth switching device S4 and the fifth switching device S5 are in the off state.

Further, in the above switched capacitor circuit provided by the embodiment of the present invention, the voltage of the first input signal sent by the signal input terminal Vin is set to Vss, and the reference signal terminal Vref is grounded. When the first input signal is less than the set threshold voltage, in the charging phase, the second switching device S2 is in the off state, the first capacitor Cst1 and the second capacitor Cst2 are in a parallel state, the first switching device S1, the third switching device S3 , the fourth switching device S4 and the fifth switching device S5 are in a conduction state; at this time, the first terminal m1 of the first capacitor Cst1 is connected to the signal input terminal Vin, the voltage of the first terminal m1 of the first capacitor Cst1 is Vss, and the first terminal m1 of the first capacitor Cst1 is Vss. The second terminal m2 of a capacitor Cst1 is grounded, the voltage at the second terminal m2 of the first capacitor Cst1 is 0, the second terminal n2 of the second capacitor Cst2 is connected to the signal input terminal Vin, and the voltage at the second terminal n2 of the second capacitor Cst2 is Vss, the first terminal n1 of the second capacitor Cst2 is grounded, and the voltage of the first terminal n1 of the second capacitor Cst2 is 0, so that the first input signal of the signal input terminal Vin is charged to the first capacitor Cst1 and the second capacitor Cst2.

When the first input signal is greater than or equal to the set threshold voltage, in the charging phase, the first switching device S1 and the third switching device S3 are in the off state, the first capacitor Cst1 and the second capacitor Cst2 are in a series state, and the second switch The device S2, the fourth switching device S4 and the fifth switching device S5 are in a conduction state; at this time, the first terminal m1 of the first capacitor Cst1 is connected to the signal input terminal Vin, and the voltage at the first terminal m1 of Cst1 of the first capacitor is Vss, the second terminal m2 of the first capacitor Cst1 is connected to the second terminal n2 of the second capacitor Cst2, the first terminal n1 of the second capacitor Cst2 is grounded, the voltage of the first terminal n1 of the second capacitor Cst2 is 0, the first capacitor The voltages of the second terminal m2 of Cst1 and the second terminal n2 of the second capacitor Cst2 are respectively 0.5Vss, so that the first input signal of the signal input terminal Vin is charged to the first capacitor Cst1 and the second capacitor Cst2.

To sum up, in the above-mentioned switched capacitor circuit provided by the embodiment of the present invention, when the first input signal sent by the signal input terminal Vin is different, the connection relationship between the first capacitor Cst1 and the second capacitor Cst2 is different, so that the first capacitor Cst1 and the second capacitor Cst2 are charged in the first capacitor circuit. The voltages of the first capacitor Cst1 and the second capacitor Cst2 are also different.

Preferably, for the convenience of implementation, in the above switched capacitor circuit provided by the embodiment of the present invention, as shown in FIG. 2 , the discharge control module 5 may specifically include: a sixth switching device S6, a seventh switching device S7, a Eight switching devices S8 and ninth switching devices S9; wherein,

The input terminal S6 _i of the sixth switching device S6 is respectively connected to the signal input terminal Vin and the input terminal S7 _i of the seventh switching device S7; the output terminal S6 _o of the sixth switching device S6 is connected to the second terminal m2 of the first capacitor Cst1 ;

The output terminal S7 _o of the seventh switching device S7 is connected to the first terminal n1 of the second capacitor Cst2;

The input terminal S8 _i of the eighth switching device S8 is connected to the first terminal m1 of the first capacitor Cst1; the output terminal S8 _o of the eighth switching device S8 is respectively connected to the output terminal S9 _o of the ninth switching device S9 and the discharge capacitor module 2 The first terminal X1 is connected to the signal output terminal Vout;

The input terminal S9 _i of the ninth switching device S9 is connected to the second terminal n2 of the second capacitor Cst2;

In the charging stage, the sixth switching device S6, the seventh switching device S7, the eighth switching device S8 and the ninth switching device S9 are in the off state; in the discharging stage, the sixth switching device S6, the seventh switching device S7, the eighth switching device Device S8 and ninth switching device S9 are in a conducting state.

Specifically, in the above switched capacitor circuit provided by the embodiment of the present invention, the selector can be used to realize the control of related switching devices under different input signals. Specifically, when the first input signal sent by the signal input terminal Vin is lower than the set threshold voltage, the selector makes the second switching device S2 in the off state in both the charging phase and the discharging phase; in the charging phase, the selector makes the first The clock control signal controls the first switching device S1, the third switching device S3, the fourth switching device S4, and the fifth switching device S5 to be in a conduction state, and the selector makes the second clock control signal control the sixth switching device S6 and the seventh switching device S6. The device S7, the eighth switching device S8 and the ninth switching device S9 are in the off state; in the discharging phase, the selector makes the first clock control signal control the first switching device S1, the third switching device S3, the fourth switching device S4 and the The fifth switching device S5 is in the off state, and the selector makes the second clock control signal control the sixth switching device S6 , the seventh switching device S7 , the eighth switching device S8 and the ninth switching device S9 to be in the on state.

When the first input signal sent by the signal input terminal Vin is greater than or equal to the set threshold voltage, the selector makes the first switching device S1 and the third switching device S3 in the off state in the charging phase and the discharging phase; in the charging phase, The selector makes the first clock control signal control the second switching device S2, the fourth switching device S4 and the fifth switching device S5 to be in the conduction state, and the selector makes the second clock control signal control the sixth switching device S6 and the seventh switching device S7, the eighth switching device S8 and the ninth switching device S9 are in the off state; in the discharge phase, the selector makes the first clock control signal control the second switching device S2, the fourth switching device S4 and the fifth switching device S5 to be in the off state , the selector makes the second clock control signal control the sixth switching device S6 , the seventh switching device S7 , the eighth switching device S8 and the ninth switching device S9 to be in a conducting state.

Further, in specific implementation, in the above switched capacitor circuit provided by the embodiment of the present invention, the first clock control signal and the second clock control signal are two non-overlapping clock signals, of course, the first clock control signal and the second clock control signal The second clock control signal may also be other signals capable of implementing the solution of the present invention, which is not limited here.

The specific working principle of the above-mentioned switched capacitor circuit provided by the embodiment of the present invention will be described in detail below through specific examples. In the following example, the reference signal terminal Vref is grounded, the capacitance values of the first capacitor Cst1 and the second capacitor Cst2 are equal, and the voltage value of the first input signal sent by the signal input terminal Vin is Vss.

In specific implementation, when the voltage Vss of the first input signal is less than the set threshold voltage: as shown in Figure 3a, in the figure, V _CLK1 is the timing diagram of the first clock control signal CLK1, and V _CLK2 is the timing diagram of the second clock control signal. The timing diagram of the signal CLK2, Vin is the timing diagram of the voltage of the signal input terminal Vin, Vm1 is the timing diagram of the voltage of the first terminal m1 of the first capacitor Cst1, and Vm2 is the timing diagram of the voltage of the second terminal m2 of the first capacitor Cst1, Vn1 is a timing diagram of the voltage at the first terminal n1 of the second capacitor Cst2, Vn2 is a timing diagram of the voltage at the second terminal n2 of the second capacitor Cst2, Vo1 is a timing diagram of the voltage at the first terminal o1 of the third capacitor Cst3, and Vo2 is The timing diagram of the voltage of the second terminal o2 of the third capacitor Cst1, Vout is the timing diagram of the voltage of the signal output terminal Vout.

Charging stage T1: the second switching device S2 is in the off state, the clock signal CLK1 controls the first switching device S1, the third switching device S3, the fourth switching device S4, and the fifth switching device S5 to be in the conducting state, and the clock signal CLK2 controls The sixth switching device S6, the seventh switching device S7, the eighth switching device S8 and the ninth switching device S9 are in an off state.

At this time, the first capacitor Cst1 and the second capacitor Cst2 are in parallel state; the second terminal m2 of the first capacitor Cst1 is grounded, the voltage Vm2 of the second terminal m2 of the first capacitor Cst1 is 0, and the first terminal m1 of the first capacitor Cst1 Connected to the signal input terminal Vin, the voltage Vss of the first input signal sent by the signal input terminal Vin charges the first capacitor Cst1, the voltage Vm1 of the first terminal m1 of the first capacitor Cst1 is Vss; the first terminal of the second capacitor Cst2 n1 is grounded, the voltage Vn1 of the first terminal n1 of the second capacitor Cst2 is 0, the second terminal n2 of the second capacitor Cst2 is connected to the signal input terminal Vin, and the voltage Vss of the first input signal sent by the signal input terminal Vin has an effect on the second capacitor Cst2 is being charged, and the voltage Vn2 of the second terminal n2 of the second capacitor Cst2 is Vss.

Discharging stage T2: the second switching device S2 is in the off state, the clock signal CLK1 controls the first switching device S1, the third switching device S3, the fourth switching device S4, and the fifth switching device S5 to be in the off state, and the clock signal CLK2 controls the The sixth switching device S6 , the seventh switching device S7 , the eighth switching device S8 and the ninth switching device S9 are turned on.

At this time, the first capacitor Cst1 and the second capacitor Cst2 are connected in parallel; the second terminal m2 of the first capacitor Cst1 is connected to the signal input terminal Vin, the voltage Vm2 of the second terminal m2 of the first capacitor Cst1 becomes Vss, and the first capacitor The first terminal m1 of Cst1 is respectively connected to the second terminal o2 of the third capacitor Cst3 and the output signal terminal Vout. According to the principle of capacitance conservation, the voltage Vm1 of the first terminal m1 of the first capacitor Cst1 becomes 2Vss, and the voltage of the second capacitor Cst2 The first terminal n1 is connected to the signal input terminal Vin, the voltage Vn1 of the first terminal n1 of the second capacitor Cst2 becomes Vss, and the second terminal n2 of the second capacitor Cst2 is respectively connected to the second terminal o2 of the third capacitor Cst3 and the output signal terminal Vout is connected, and according to the principle of capacitance conservation of electricity, the voltage Vn2 of the second terminal n2 of the second capacitor Cst2 becomes 2Vss.

Since the first capacitor Cst1 and the second capacitor Cst2 are connected in parallel, the first terminal o1 of the third capacitor Cst3 is grounded, and the second terminal o2 of the third capacitor Cst3 is connected to the first terminal m1 of the first capacitor Cst1 and the second capacitor Cst2 respectively. The second terminal n2 is connected, the voltage 2Vss of the first terminal m1 of the first capacitor Cst1 and the voltage 2Vss of the second terminal n2 of the second capacitor Cst2 respectively charge the third capacitor Cst3 and output it from the signal output terminal Vout, therefore, the third capacitor The voltage Vo2 of the second terminal o2 of Cst3 is 2Vss, and the voltage value of the signal output terminal Vout is also 2Vss.

It can be seen from the above that the switched capacitor circuit provided by the embodiment of the present invention realizes the function of double boosting range when the voltage Vss of the first input signal sent by the signal input terminal Vin is lower than the set threshold voltage.

In specific implementation, when the voltage Vss of the first input signal is greater than or equal to the set threshold voltage: as shown in Figure 3b, in the figure, V _CLK1 is the timing diagram of the first clock control signal CLK1, and V _CLK2 is the timing diagram of the second The timing diagram of the clock control signal CLK2, Vin is the timing diagram of the voltage at the signal input terminal Vin, Vm1 is the timing diagram of the voltage at the first terminal m1 of the first capacitor Cst1, and Vm2 is the timing diagram of the voltage at the second terminal m2 of the first capacitor Cst1 In the figure, Vn1 is a timing diagram of the voltage of the first terminal n1 of the second capacitor Cst2, Vn2 is a timing diagram of the voltage of the second terminal n2 of the second capacitor Cst2, and Vo1 is a timing diagram of the voltage of the first terminal o1 of the third capacitor Cst3, Vo2 is a timing diagram of the voltage at the second terminal o2 of the third capacitor Cst1 , and Vout is a timing diagram of the voltage at the signal output terminal Vout.

Charging stage T1: the first switching device S1 and the third switching device S3 are in the off state, the clock signal CLK1 controls the second switching device S2, the fourth switching device S4, and the fifth switching device S5 to be in the conducting state, and the clock signal CLK2 controls The sixth switching device S6, the seventh switching device S7, the eighth switching device S8 and the ninth switching device S9 are in an off state.

At this time, the first capacitor Cst1 and the second capacitor Cst2 are connected in series; the first terminal n1 of the second capacitor Cst2 is grounded, the voltage Vn1 of the first terminal n1 of the second capacitor Cst2 is 0, and the first terminal m1 of the first capacitor Cst1 Connected to the signal input terminal Vin, the second terminal m2 of the first capacitor Cst1 is connected to the second terminal n2 of the second capacitor Cst2, and the voltage Vss of the first input signal sent by the signal input terminal Vin has an effect on the first capacitor Cst1 and the second capacitor Cst2 is charging, the voltage Vm1 at the first terminal m1 of the first capacitor Cst1 is Vss, the voltage Vm2 at the second terminal m2 of the first capacitor Cst1 is 0.5Vss, and the voltage Vn2 at the second terminal n2 of the second capacitor Cst2 is 0.5Vss.

Discharging stage T2: the first switching device S1 and the third switching device S3 are in the off state, the clock signal CLK1 controls the second switching device S2, the fourth switching device S4, and the fifth switching device S5 to be in the off state, and the clock signal CLK2 controls the The sixth switching device S6, the seventh switching device S7, the eighth switching device S8 and the ninth switching device S9 are in a conducting state.

At this time, the first capacitor Cst1 and the second capacitor Cst2 are connected in parallel; the second terminal m2 of the first capacitor Cst1 is connected to the signal input terminal Vin, the voltage Vm2 of the second terminal m2 of the first capacitor Cst1 becomes Vss, and the first capacitor The first terminal m1 of Cst1 is respectively connected to the second terminal o2 of the third capacitor Cst3 and the output signal terminal Vout. According to the principle of capacitance conservation of electricity, the voltage Vm1 of the first terminal m1 of the first capacitor Cst1 becomes 1.5Vss, and the second capacitor Cst2 The first terminal n1 of the second capacitor Cst2 is connected to the signal input terminal Vin, the voltage Vn1 of the first terminal n1 of the second capacitor Cst2 becomes Vss, and the second terminal n2 of the second capacitor Cst2 is respectively connected with the second terminal o2 of the third capacitor Cst3 and the output signal The terminal Vout is connected, and according to the principle of conservation of electric capacity of the capacitor, the voltage Vn2 of the second terminal n2 of the second capacitor Cst2 becomes 1.5Vss.

Since the first capacitor Cst1 and the second capacitor Cst2 are connected in parallel, the first terminal o1 of the third capacitor Cst3 is grounded, and the second terminal o2 of the third capacitor Cst3 is connected to the first terminal m1 of the first capacitor Cst1 and the second capacitor Cst2 respectively. The second terminal n2 is connected, the voltage 1.5Vss of the first terminal m1 of the first capacitor Cst1 and the voltage 1.5Vss of the second terminal n2 of the second capacitor Cst2 respectively charge the third capacitor Cst3 and output it from the signal output terminal Vout, therefore, the first The voltage Vo2 of the second terminal o2 of the three capacitors Cst3 is 1.5Vss, and the voltage value of the signal output terminal Vout is also 1.5Vss.

It can be seen from the above that the switched capacitor circuit provided by the embodiment of the present invention realizes the function of boosting the voltage by 1.5 times when the voltage Vss of the first input signal sent by the signal input terminal Vin is greater than or equal to the set threshold voltage.

To sum up, the above-mentioned switched capacitor circuit provided by the embodiment of the present invention can not only realize the function of 2 times the boosting range through the first capacitor, the second capacitor and the third capacitor, but also can realize the function of 1.5 times the boosting range. In the existing switched capacitor circuit, only one kind of boosting range can be realized, that is, in the prior art, to realize the function of 2 times the boosting range and 1.5 times the boosting range, it is necessary to design two separate switched capacitor circuits . Therefore, the above-mentioned switched capacitor circuit provided by the embodiment of the present invention can realize the function of boosting amplitude in two cases by multiplexing the first capacitor, the second capacitor and the third capacitor. Compared with the existing switched capacitor circuit, The number of switches can be saved, thereby reducing the chip area and reducing the static power consumption of the switched capacitor circuit.

Preferably, for the convenience of implementation, in the above switched capacitor circuit provided by the embodiment of the present invention, the first switching device, the second switching device, the third switching device, the fourth switching device and the fifth switching device may be doped Metal-oxide-semiconductor MOS transistors with the same polarity.

Preferably, for the convenience of implementation, in the above switched capacitor circuit provided by the embodiment of the present invention, the sixth switching device, the seventh switching device, the eighth switching device and the ninth switching device may be metals with the same doping polarity Oxide semiconductor MOS tube.

Preferably, in the above switched capacitor circuit provided by the embodiment of the present invention, according to the characteristics of each switching device, the first switching device and the fifth switching device are N-type MOS transistors; wherein,

The source and the substrate of the N-type MOS transistor are respectively connected to the reference signal terminal, and the reference signal terminal is grounded.

Since in the above-mentioned switched capacitor circuit provided by the embodiment of the present invention, the voltage at the input terminal of the first switching device and the fifth switching device is always higher than the voltage at the output terminal, the first switching device and the fifth switching device are specifically set to N Type MOS tube, the source and substrate of the N-type MOS tube are respectively connected to the output terminal of the switching device, that is, the reference signal terminal, and the drain of the N-type MOS tube is connected to the input terminal of the switching device. In this way, in the N-type MOS tube, the source potential is always lower than the drain potential, and the substrate is always connected to the source with a lower potential, thus ensuring that the parasitic transistor in the N-type MOS tube is always in the off state, reducing N The substrate current of the type MOS tube can further reduce the static power consumption of the entire switched capacitor circuit.

Preferably, in the above switched capacitor circuit provided by the embodiment of the present invention, according to the characteristics of each switching device, the sixth switching device and the seventh switching device are P-type MOS transistors; wherein,

The source electrode and the substrate of the P-type MOS transistor are respectively connected to the signal input end.

Since in the above-mentioned switched capacitor circuit provided by the embodiment of the present invention, the voltage at the input terminal of the sixth switching device and the seventh switching device is always higher than the voltage at the output terminal, the first switching device and the fifth switching device are specifically set as P Type MOS tube, the source and substrate of the P-type MOS tube are respectively connected to the input terminal of the switching device, that is, the signal input terminal, and the drain of the P-type MOS tube is connected to the output terminal of the switching device. In this way, in the P-type MOS tube, the source potential is always higher than the drain potential, and the substrate is always connected to the source with a higher potential, thus ensuring that the parasitic transistor in the P-type MOS tube is always in the off state, reducing the P The substrate current of the type MOS tube can further reduce the static power consumption of the entire switched capacitor circuit.

Preferably, in the above switched capacitor circuit provided by the embodiment of the present invention, according to the characteristics of each switching device, the second switching device, the third switching device and the fourth switching device are N-type MOS transistors with a composite structure; wherein,

The N-type MOS transistor with a composite structure, as shown in Figure 4a, specifically includes: a first body potential selection transistor M1, a second body potential selection transistor M2, and an N-type MOS transistor M0; wherein, the source S0 of the N-type MOS transistor M0 It is connected to the source S1 of the first body potential selection transistor M1, the drain D0 of the N-type MOS transistor M0 is connected to the source S2 of the second body potential selection transistor M2, and the substrate T0 of the N-type MOS transistor M0 is respectively connected to the first The body potential selection transistor M1 is connected to the drains D1 and D2 of the second body potential selection transistor M2; the substrate T1 of the first body potential selection transistor M1 is connected to the substrate T2 of the second body potential selection transistor M2.

Since in the above-mentioned switched capacitor circuit provided by the embodiment of the present invention, the voltages at the input terminals of the second switching device, the third switching device and the fourth switching device fluctuate up and down relative to the voltage at the output terminal, the second switching device, the third switching device The switching device and the fourth switching device are specifically configured as N-type MOS transistors of a composite structure, and when the source voltage of the N-type MOS transistors in the N-type MOS transistors of the composite structure is higher than the drain voltage, the second body potential selection transistor is turned on , the first body potential selection transistor is turned off, the substrate of the N-type MOS transistor is connected to the drain, when the source voltage of the N-type MOS transistor in the N-type MOS transistor of the composite structure is lower than the drain voltage, the first body potential The selection transistor is turned on, the second body potential selection transistor is turned off, and the substrate of the N-type MOS transistor is connected to the source, so as to ensure that in the N-type MOS transistor of the composite structure, the substrate of the N-type MOS transistor is always in the middle potential of the source and the drain. The lower end is connected to ensure that the parasitic transistor of the N-type MOS transistor is always in the off state, reducing the substrate current of the N-type MOS transistor in the N-type MOS transistor of the composite structure, and further reducing the static state of the entire switched capacitor circuit. power consumption.

Similarly, in the above switched capacitor circuit provided by the embodiment of the present invention, the eighth switching device and the ninth switching device are P-type MOS transistors with a composite structure; wherein,

The P-type MOS transistor with a composite structure, as shown in Figure 4b, specifically includes: the first body potential selection transistor M1, the second body potential selection transistor M2, and the P-type MOS transistor M0; wherein the source S0 of the P-type MOS transistor M0 is connected to The source S1 of the first body potential selection transistor M1 is connected, the drain D0 of the P-type MOS transistor M0 is connected to the source S2 of the second body potential selection transistor M2, and the substrate T0 of the P-type MOS transistor M0 is respectively connected to the first body The potential selection transistor M1 is connected to the drains D1 and D2 of the second bulk potential selection transistor M2; the substrate T1 of the first bulk potential selection transistor M1 is connected to the substrate T2 of the second bulk potential selection transistor M2.

Since in the above switched capacitor circuit provided by the embodiment of the present invention, the voltage at the input terminal of the eighth switching device and the ninth switching device fluctuates up and down relative to the voltage at the output terminal, the eighth switching device and the ninth switching device are specifically set as P-type MOS transistors with a composite structure, when the source voltage of the P-type MOS transistors in the P-type MOS transistors with a composite structure is higher than the drain voltage, the first body potential selection transistor is turned on, the second body potential selection transistor is turned off, and the P The substrate of the P-type MOS tube is connected to the source. When the source voltage of the P-type MOS tube in the P-type MOS tube of the composite structure is lower than the drain voltage, the second body potential selection tube is turned on, and the first body potential selection tube is turned on. Closed, the substrate of the P-type MOS tube is connected to the drain, so as to ensure that in the composite structure of the P-type MOS tube, the substrate of the P-type MOS tube is always connected to the higher potential end of the source and drain, ensuring that the P-type MOS The parasitic transistor of the tube is always in the cut-off state, which reduces the substrate current of the P-type MOS tube in the P-type MOS tube of the composite structure, and further reduces the static power consumption of the entire switched capacitor circuit.

In the switched capacitor circuit provided by the embodiment of the present invention, since the boost multiple control module can control the charging capacitor module to have different capacitance values during the charging phase, therefore, under the control of the boost multiple control module, the charging control module inputs the signal The first input signal sent by the terminal is charged into the charging capacitor module, which can make the charging capacitor module have different charge amounts. Furthermore, since the charging capacitor modules have different charge amounts, in the discharging stage, when the discharge control module controls the charging capacitor module to When the discharge capacitor module is charged, the discharge capacitor module can have different voltages, and the output voltages from the signal output terminals are also different, so as to realize the function of the switched capacitor circuit with different voltage boosting ranges. However, in the existing switched capacitor circuit, one charging capacitor module and one discharging capacitor module can only realize one boosting range, that is, to realize different boosting ranges, multiple switched capacitor circuits are required. Therefore, compared with the existing switched capacitor circuit, the switched capacitor circuit provided by the embodiment of the present invention can reduce the area of the chip and reduce the power consumption of the switched capacitor circuit.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (12)

1. A switched-capacitor circuit, comprising: the device comprises a charging capacitor module, a discharging capacitor module, a boosting multiple control module, a charging control module and a discharging control module; wherein,

in the charging stage: the charging control module receives a first input signal sent by a signal input end and a second input signal sent by a reference signal end, and respectively and correspondingly outputs the first input signal and the second input signal to a first end and a second end of the charging capacitor module to charge the charging capacitor module; and the number of the first and second groups,

when the voltage of the first input signal is smaller than a set threshold voltage, the boost multiple control module receives the first input signal and the second input signal, respectively outputs the first input signal and the second input signal to a third end and a fourth end of the charging capacitor module correspondingly, and charges the charging capacitor module; when the voltage of the first input signal is greater than or equal to a set threshold voltage, the boost multiple control module conducts the third end and the fourth end of the charging capacitor module;

in the discharging stage: the discharging control module receives the first input signal and outputs the first input signal to a second end and a fourth end of the charging capacitor module; the first end and the third end of the charging capacitor module are conducted with the first end and the signal output end of the discharging capacitor module, so that the charging capacitor module charges the discharging capacitor module and outputs signals through the signal output end; wherein a second end of the discharging capacitance module receives the second input signal.

2. The switched-capacitor circuit as claimed in claim 1, wherein the charging-capacitor module specifically comprises: a first capacitor and a second capacitor; wherein,

the first end of the first capacitor is the first end of the charging capacitor module, and the second end of the first capacitor is the fourth end of the charging capacitor module;

the first end of the second capacitor is the second end of the charging capacitor module, and the second end of the second capacitor is the third end of the charging capacitor module.

3. The switched-capacitor circuit as claimed in claim 2, wherein the boost multiple control module specifically comprises: a first switching device, a second switching device and a third switching device; wherein,

the input end of the first switching device is respectively connected with the input end of the second switching device and the second end of the first capacitor; the output end of the first switching device is connected with the reference signal end;

the input end of the third switching device is connected with the signal input end; the output end of the third switching device is respectively connected with the output end of the second switching device and the second end of the second capacitor;

in a charging stage, when the voltage of the first input signal is smaller than a set threshold voltage, the second switching device is in a closed state, the first switching device and the third switching device are in a conducting state, and the first capacitor and the second capacitor are in a parallel state; in a charging stage, when the voltage of the first input signal is greater than or equal to a set threshold voltage, the second switching device is in a conducting state, the first switching device and the third switching device are in a closing state, and the first capacitor and the second capacitor are in a series connection state;

during a discharge phase, the first, second, and third switching devices are in an off state.

4. The switched-capacitor circuit as claimed in claim 3, wherein the charging control module comprises: a fourth switching device and a fifth switching device; wherein,

the input end of the fourth switching device is respectively connected with the signal input end and the input end of the third switching device; the output end of the fourth switching device is connected with the first end of the first capacitor;

the input end of the fifth switching device is connected with the first end of the second capacitor; the output end of the fifth switching device is connected with the reference signal end;

in a charging phase, the fourth switching device and the fifth switching device are in a conducting state; in a discharging phase, the fourth switching device and the fifth switching device are in an off state.

5. The switched-capacitor circuit as claimed in claim 4, wherein said first, second, third, fourth and fifth switching devices are MOS transistors with same doping polarity.

6. The switched-capacitor circuit as claimed in claim 5, wherein said first switching device and said fifth switching device are N-type MOS transistors; wherein,

and the source electrode and the substrate of the N-type MOS tube are respectively connected with a reference signal end, and the reference signal end is grounded.

7. The switched-capacitor circuit as claimed in claim 6, wherein said second switching device, said third switching device and said fourth switching device are N-type MOS transistors of a composite structure; wherein,

the N-type MOS tube with the composite structure specifically comprises: the device comprises a first bulk potential selection tube, a second bulk potential selection tube and an N-type MOS tube; the source electrode of the N-type MOS tube of the composite structure is connected with the source electrode of the first bulk potential selection tube, the drain electrode of the N-type MOS tube is connected with the source electrode of the second bulk potential selection tube, and the substrate of the N-type MOS tube is respectively connected with the drain electrodes of the first bulk potential selection tube and the second bulk potential selection tube; the substrate of the first bulk potential selection tube is connected with the substrate of the second bulk potential selection tube.

8. The switched-capacitor circuit as claimed in claim 2, wherein the discharge control module specifically comprises: a sixth switching device, a seventh switching device, an eighth switching device, and a ninth switching device; wherein,

an input end of the sixth switching device is connected with the signal input end and an input end of the seventh switching device respectively; the output end of the sixth switching device is connected with the second end of the first capacitor;

the output end of the seventh switching device is connected with the first end of the second capacitor;

the input end of the eighth switching device is connected with the first end of the first capacitor; an output end of the eighth switching device is connected with an output end of the ninth switching device, a first end of the discharging capacitor module and the signal output end respectively;

the input end of the ninth switching device is connected with the second end of the second capacitor;

in a charging phase, the sixth switching device, the seventh switching device, the eighth switching device, and the ninth switching device are in an off state; in a discharging phase, the sixth switching device, the seventh switching device, the eighth switching device, and the ninth switching device are in a conducting state.

9. The switched-capacitor circuit as claimed in claim 8, wherein said sixth switching device, said seventh switching device, said eighth switching device and said ninth switching device are MOS transistors with the same doping polarity.

10. The switched-capacitor circuit as claimed in claim 9, wherein the sixth switching device and the seventh switching device are P-type MOS transistors; wherein,

and the source electrode and the substrate of the P-type MOS tube are respectively connected with the signal input end.

11. The switched-capacitor circuit as claimed in claim 10, wherein said eighth switching device and said ninth switching device are P-type MOS transistors of a composite structure; wherein,

the P type MOS pipe of composite construction specifically includes: the device comprises a first bulk potential selection tube, a second bulk potential selection tube and a P-type MOS tube; the source electrode of the P-type MOS tube of the composite structure is connected with the source electrode of the first bulk potential selection tube, the drain electrode of the P-type MOS tube is connected with the source electrode of the second bulk potential selection tube, and the substrate of the P-type MOS tube is respectively connected with the drain electrodes of the first bulk potential selection tube and the second bulk potential selection tube; the substrate of the first bulk potential selection tube is connected with the substrate of the second bulk potential selection tube.

12. The switched-capacitor circuit as claimed in any one of claims 1-11, wherein said discharging-capacitor module, in particular, comprises: a third capacitor; wherein,

the first end of the third capacitor is the second end of the discharge capacitor module, and the second end of the third capacitor is the first end of the discharge capacitor module.