CN103367453B - A kind of ultra-thin lateral double diffusion metal oxide semiconductor field effect transistor and preparation method thereof - Google Patents

Abstract

An ultra-thin lateral double-diffused metal oxide semiconductor field effect transistor, comprising a P-type substrate, a buried oxide layer is arranged on the P-type substrate, an N-type well region and a P-type well region are arranged on the buried oxide layer, An N-type buffer area is provided in the N-type well area, a field oxide layer is provided on the N-type well area, an N-type drain area is provided in the N-type buffer area, and a P-type contact area is provided in the P-type well area and the N-type source region, a P-type well region array composed of P-type well region units is provided under the field oxide layer, and the P-type well region array is located between the N-type buffer region and the P-type well region, and the P-type well region The width of the unit gradually increases from the N-type buffer area to the P-type well region. The invention greatly enhances the ability of the ultra-thin lateral double-diffused metal oxide semiconductor field effect transistor in the level shift circuit to resist the influence of high-voltage parasitic effects, which can be extremely Greatly improve the performance of the intelligent power module. The invention also discloses a preparation method of the ultra-thin lateral double-diffusion metal oxide semiconductor field effect transistor.

Description

An ultra-thin lateral double-diffused metal oxide semiconductor field effect transistor and its preparation method

technical field

The invention relates to a power semiconductor device, in particular to an ultra-thin lateral double-diffused metal oxide semiconductor field effect transistor used in a level shift circuit.

Background technique

Intelligent power modules in high-voltage power integrated circuits can be used in various fields, such as driving and controlling various industrial and residential, single-phase and three-phase motors. The level shift circuit in the intelligent power module provides the output voltage for the high-voltage output circuit, which has become a key part of the entire intelligent power module. The LDMOS used as the switching element in the level shift circuit has high withstand voltage, simple driving circuit, and fast switching speed Fast and other advantages. Because of this, LDMOS has been frequently used in power integrated circuits in recent years. However, when LDMOS is used in a level shift circuit, the drain of LDMOS needs to lead out interconnection lines to provide output voltage for high-voltage output circuits, and this part of interconnection lines with high-voltage signals must pass through LDMOS in the process of being drawn out. In the drift region, the electric field formed around the high-voltage interconnection line will seriously affect the potential distribution in the drift region, which will greatly reduce the breakdown voltage of LDMOS, and eventually cause the level shift circuit to lose its function. How to enhance the ability of LDMOS in the level shifting circuit to resist the influence of high-voltage interconnection becomes the key to improving the performance of the entire integrated circuit. Therefore, the research on the ability of ultra-thin LDMOS to resist the influence of high-voltage interconnection lines in power switching elements is undoubtedly an important content of intelligent power module circuits and processes.

Among the various existing methods to solve the influence of high-voltage interconnection lines at the drain end of LDMOS, the most effective and prominent one is the isolation structure of lateral high-voltage devices in the bulk silicon process mentioned in Mitsubishi's US patent US5894156, which embeds LDMOS in the isolation In the structure, the metal connection lead out from the LDMOS drain end is connected with the high basin end of the entire isolation structure, and finally led out from the high basin end, avoiding the high-voltage interconnection line passing directly above the LDMOS drift region and affecting the drift region The distribution of electric potential in the middle. However, for the level shift circuit implemented under the ultra-thin-film process platform, its isolation structure adopts the isolation of the LOCOS method mentioned in US Patent US7510927B2. Compared with the isolation structure under the bulk silicon process, this isolation technology greatly reduces the Therefore, due to the different isolation structures used by the two, the method of how to lead out the high-voltage interconnection lines in US5894156 is not feasible under the ultra-thin process platform.

Contents of the invention

The invention provides an ultra-thin silicon-on-insulator LDMOS that is resistant to the influence of high-voltage interconnect lines. The invention solves the problem of high-voltage parasitic effects caused by high-voltage interconnect lines in level shift circuits, without sacrificing the breakdown voltage Successfully lead out the drain metal connection of LDMOS.

The present invention adopts following technical scheme:

An ultra-thin lateral double-diffused metal oxide semiconductor field effect transistor, comprising: a P-type substrate, a buried oxide layer is arranged on the P-type substrate, and an N-type well region and a P-type well region are arranged on the buried oxide layer , an N-type buffer area is provided in the N-type well area, an N-type drain area is provided in the N-type buffer area, a P-type contact area and an N-type source area are provided in the P-type well area, and a N-type well area is provided in the N-type well area A field oxide layer is arranged on it, and a boundary of the N-type drain region is offset against a boundary of the field oxide layer, and a polysilicon gate is provided on the surface of the boundary region adjacent to the N-type source region of the field oxide layer, and the polysilicon gate is formed from the field The boundary of the oxide layer extends toward the N-type source region to the top of the N-type source region, and a gate oxide layer is provided under the extended region of the polysilicon gate. In the field oxide layer, polysilicon gate, P-type well region, P-type contact region, N A dielectric isolation oxide layer is provided on the N-type source region, N-type buffer region, and N-type drain region. The source metal connection is connected to the P-type contact region and the N-type source region, and the drain metal connection is connected to the N-type drain region. The line is connected to the gate metal wiring on the polysilicon gate, which is characterized in that a P-type well array composed of P-type well units is provided under the field oxide layer, and the P-type well array is located between the N-type buffer zone and the N-type buffer zone. Between the P-type well regions, the width of the P-type well region units gradually increases from the N-type buffer region to the P-type well region.

The preparation method of the ultra-thin lateral double-diffused metal oxide semiconductor field effect transistor is as follows:

The first step: prepare the P-type silicon substrate,

The second step: deposit a buried oxide layer, and then carry out epitaxial growth, ion implantation of phosphorus to form an N-type well region, ion implantation of arsenic and phosphorus to form an N-type buffer zone, annealing,

Step 3: Deposit photoresist, prepare a mask whose window size starts from N-type buffer zone from small to large, photolithography, ion implantation of boron to generate P-type well area unit, annealing,

Step 4: Deposit silicon nitride, photolithography to form an active region, etch silicon nitride, then grow field oxygen, and perform field implantation, and ion implant boron fluoride to change the channel doping concentration and adjust the channel threshold Voltage, then grow a gate oxide layer with a thickness of 500Å, deposit and etch polysilicon to form polysilicon gate and polysilicon field plate, ion implant boron to form P-type well region,

Step 5: Photolithography, ion implantation of phosphorus and arsenic to generate N-type source region and N-type drain region, photolithography, ion implantation of boron fluoride to generate P-type contact region,

Step 6: Deposit a dielectric isolation oxide layer, etch the contact hole, deposit metal aluminum, etch the aluminum to form the drain metal connection and the drain metal connection is directly above the P-type well region array, etch the aluminum To form source metal wiring and gate metal wiring, and finally conduct dielectric passivation treatment.

In the method of the present invention, the thickness of the photoresist deposited in the third step is 1.2 μm, the implantation energy of boron ions is 50kev, and the implantation dose of boron ions is 8e12cm ^-2 .

Compared with prior art, the present invention has following advantage:

(1) An ultra-thin lateral double-diffused metal oxide semiconductor field effect transistor of the present invention adopts a new structure (Fig. 1), that is, a P-type A P-type well area array composed of well area units, the P-type well area array is located between the N-type buffer area and the P-type well area, and the width of the P-type well area unit gradually increases from the N-type buffer area to the P-type well area increase. Compared with the traditional lateral double-diffused metal-oxide-semiconductor field-effect transistor (Fig. 2) without P-type well region array structure, the present invention realizes that under the normal working condition of the level shift circuit, when the drain metal connection passes high voltage Signal, the high-voltage signal is the same as the voltage applied to the N-type drain region of the LDMOS, but as the potential of the LDMOS from the N-type drain region to the N-type source region gradually decreases, the high-voltage interconnection line and the N-type well region A potential difference will be formed to generate an electric field, and the formed electric field will gradually increase from the N-type drain region to the N-type source region, so a P-type well region unit whose width gradually increases from the N-type drain region to the N-type source region is required to prevent the electric field The effect on the distribution of electrons in the N-type well region (refer to Figure 8) enables the N-type well region to be completely depleted with the P-type well region, ultimately avoiding a decrease in breakdown voltage (refer to Figure 9).

(2) An ultra-thin lateral double-diffused metal oxide semiconductor field effect transistor of the present invention, because the P-type well region array prevents the influence of the high-voltage interconnection line on the electron distribution of the N-type well region, and adopts the LOCOS isolation structure to LDMOS is isolated from the high-voltage area and the low-voltage area (Figure 7). Compared with the traditional isolation, LOCOS isolation greatly reduces the area, and at the same time, it can lead out the high-voltage interconnection without sacrificing the breakdown voltage. Therefore, , under the condition of the same area, the breakdown voltage is greatly improved compared with the traditional structure.

(3) In an ultra-thin lateral double-diffused metal oxide semiconductor field effect transistor of the present invention, the concentration of the P-type well region unit can be gradually increased from the N-type buffer zone to the P-type well region, because the closer to In the N-type source region, the greater the potential difference formed between the high-voltage interconnection line and the N-type well region, therefore, a high-concentration P-type well region unit is required to shield the influence of high electric field on the electron distribution in the N-type well region.

(4) An ultra-thin lateral double-diffused metal-oxide-semiconductor field effect transistor of the present invention is completely based on the existing process for preparing lateral ultra-thin silicon-on-insulator LDMOS, without adding additional process steps, and is simple to prepare.

Description of drawings

Fig. 1 is a schematic diagram of an ultra-thin lateral double-diffused metal oxide semiconductor field effect transistor according to the present invention;

FIG. 2 is a schematic diagram of a traditional ultra-thin lateral double-diffused metal oxide semiconductor field effect transistor;

Fig. 3 is a transverse sectional view along the I-I ' line of Fig. 1;

Fig. 4 is a transverse sectional view along the II-II' line of Fig. 1;

Fig. 5 is a transverse sectional view along the I-I ' line of Fig. 2;

Fig. 6 is a transverse sectional view along the II-II' line of Fig. 2;

7 is a schematic diagram of an ultra-thin lateral double-diffused metal-oxide-semiconductor field effect transistor and its isolation structure according to the present invention;

Fig. 8 is a comparison diagram of the breakdown voltage of an ultra-thin lateral double-diffused metal-oxide-semiconductor field effect transistor according to the present invention when the high-voltage interconnection line has a high-voltage signal after adopting different methods of forming P-type well region units;

Fig. 9 is the impact of an ultra-thin lateral double-diffused MOSFET according to the present invention and a traditional ultra-thin lateral double-diffused MOSFET when there is a high-voltage signal on the high-voltage interconnection line Comparison chart of breakdown voltage;

Fig. 10 is a comparison diagram of the breakdown voltage of an ultra-thin lateral double-diffused metal-oxide-semiconductor field effect transistor P-type well region unit junction depth changed according to the present invention;

Fig. 11 is a comparison diagram of the breakdown voltage of an ultra-thin lateral double-diffused metal-oxide-semiconductor field-effect transistor P-type well region unit concentration changed according to the present invention;

Fig. 12 is a flow chart of the preparation of an ultra-thin lateral double-diffused metal-oxide-semiconductor field-effect transistor according to the present invention;

Detailed ways

Referring to Figures 1, 2, and 3, an ultra-thin lateral double-diffused metal oxide semiconductor field effect transistor includes: a P-type substrate 1, a buried oxide layer 2 is arranged on the P-type substrate 1, and a buried oxide layer 2 is formed on the P-type substrate 1. N-type well region 4 and P-type well region 6a are arranged on it, N-type buffer region 5 is arranged in N-type well region 4, N-type drain region 9 is arranged in N-type buffer region 5, and P-type well region 6a is provided with a P-type contact region 7 and an N-type source region 8, and a field oxide layer 11 is arranged on the N-type well region 4, and a boundary of the N-type drain region 9 is offset against a boundary of the field oxide layer 11, A polysilicon gate 12 is provided on the surface of the boundary region of the field oxide layer 11 adjacent to the N-type source region 8, and the polysilicon gate 12 extends from the boundary of the field oxide layer 11 toward the N-type source region 8 to above the N-type source region 8 A gate oxide layer 10 is provided below the extended region of the polysilicon gate 12, and the field oxide layer 11, the polysilicon gate 12, the P-type well region 6a, the P-type contact region 7, the N-type source region 8, the N-type buffer zone 5 and the N-type A dielectric isolation oxide layer 13 is provided on the drain region 9, a source metal connection 14 is connected to the P-type contact region 7 and an N-type source region 8, and a drain metal connection 15 is connected to the N-type drain region 9. The polysilicon gate 12 is connected with a gate metal wire 16, which is characterized in that a P-type well region array 17 composed of a P-type well region unit 6b is arranged under the field oxide layer 11, and the P-type well region array 17 is located in the N-type well region. Between the buffer region 5 and the P-type well region 6a, the width of the P-type well region unit 6b gradually increases from the N-type buffer region 5 to the P-type well region 6a.

The P-type well region array 17 can adopt a single row and multiple columns. In this embodiment, the P-type well region array 17 composed of the P-type well region unit 6b adopts a P-type well region array with the number of rows being 1, and the number of columns is greater than 1. , can be 3 columns, 4 columns or more, as long as the electric field under the high-voltage interconnection line can be optimized.

This embodiment can also adopt the following technical measures to further improve the breakdown voltage:

(1) The width of the P-type well region unit (6b) in the P-type well region array (17) can gradually increase from the N-type drain region (9) to the N-type source region (8), and the P-type well region unit ( The width of 6b) has an optimal value, because the electric field between the high-voltage interconnection line and the N-type well region (4) gradually increases from the N-type drain region (9) to the N-type source region (8), which is It is required that the closer to the N-type source region, the wider the P-type well region unit (6b) is required to prevent the influence of the strong electric field on the electron distribution in the drift region.

(2) The junction depth of the P-type well unit (6b) in the P-type well array (17) has an optimal value, and the thinner P-type well unit (6b) cannot block the drain metal connection. The impact of the formed strong electric field on the distribution of electrons in the drift region, and the deeper P-type well region unit (6b) will occupy an excessively large drift region area, making the area of the drift region participating in depletion smaller and resulting in a lower withstand voltage. Referring to FIG. 10 , it is a comparison diagram of the breakdown voltage of the P-type well region unit ( 6b ) after the junction depth is changed. Similarly, the concentration of the P-type well unit (6b) also has an optimal value. If the concentration is too light, it cannot effectively isolate the electric field. If the concentration is too thick, it will affect the improvement of the withstand voltage of the device. Referring to Figure 11, the P-type well unit (6b) Comparison graph of breakdown voltage after concentration change.

Referring to Fig. 12, a detailed introduction is given to the preparation method of an ultra-thin lateral double-diffused metal-oxide-semiconductor field-effect transistor in the present invention:

The first step: prepare the P-type silicon substrate 1,

Step 2: Deposit a layer of buried oxide layer 2 with a thickness of 3 μm, and then perform epitaxial growth 3 to generate a layer of epitaxial layer with a thickness of 1.5 μm, deposit photoresist, and prepare to gradually expand the window from the source region to the drain region. Etch the photoresist with the enlarged mask, and implant the phosphorus with the dose of 9e12cm ^-2 to generate the N-type well region 4. Remove the photoresist, deposit the photoresist, photolithography, and implant the arsenic with the dose of 5e13cm ^-2 Form N-type buffer layer 5 with phosphorus, remove photoresist, anneal,

Step 3: Deposit a layer of photoresist with a thickness of 1.2 μm, prepare a mask with the window size starting from the N-type buffer zone from small to large, etch the photoresist according to the window size, and implant ions with an energy of 50keV Boron ions with a dose of 8e12cm ^-2 generate P-type well region unit 6b, remove the photoresist, anneal at high temperature,

Step 4: Deposit silicon nitride, photolithography to form an active region, etch silicon nitride, then grow field oxygen, and perform field implantation, and ion implant boron fluoride to change the channel doping concentration and adjust the channel threshold Voltage, then grow a gate oxide layer 10 with a thickness of 500 Å, deposit and etch polysilicon to form polysilicon gate and polysilicon field plate, and implant boron with a dose of 1.2e13cm ^-2 to form P-type well region 6a,

Step 5: Deposit photoresist, photolithography, ion implantation dose of phosphorus and arsenic with a dose of 4.2e15cm ^-2 to form N-type source region 8 and N-type drain region 9, photolithography, ion implantation dose of 2.5e15cm ^-2 Boron fluoride generates the P-type contact region 7, removes the photoresist,

Step 6: Deposit dielectric isolation oxide layer 13, contact hole etching, deposit metal aluminum, deposit photoresist, photolithography, etch aluminum to form drain metal connection 15 and the drain metal connection is on P Right above the array 17 of well regions, etch aluminum to form source metal wiring 14 and gate metal wiring 16, remove the photoresist, and finally perform dielectric passivation treatment.

Claims (4)

1. an ultra-thin lateral double-diffused metal oxide semiconductor field effect transistor, comprising: a P-type substrate (1), on which a buried oxide layer (2) is provided on the P-type substrate (1), in the buried oxide layer ( 2) An N-type well region (4) and a P-type well region (6a) are arranged on the top, an N-type buffer region (5) is arranged in the N-type well region (4), and an N-type buffer region (5) is arranged in the N-type buffer region (5). There is an N-type drain region (9), a P-type contact region (7) and an N-type source region (8) are arranged in the P-type well region (6a), and a field oxide layer is arranged on the N-type well region (4) (11), and a boundary of the N-type drain region (9) is offset against a boundary of the field oxide layer (11), and a boundary area surface adjacent to the N-type source region (8) of the field oxide layer (11) is set The polysilicon gate (12), and the polysilicon gate (12) extends from the boundary of the field oxide layer (11) toward the N-type source region (8) to the top of the N-type source region (8), on the polysilicon gate (12) A gate oxide layer (10) is provided under the extension region, and a field oxide layer (11), polysilicon gate (12), P-type well region (6a), P-type contact region (7), N-type source region (8), N A dielectric isolation oxide layer (13) is provided on the buffer zone (5) and the N-type drain region (9), and the source metal wiring (14) is connected on the P-type contact region (7) and the N-type source region (8). ), connect the drain metal wiring (15) on the N-type drain region (9), connect the gate metal wiring (16) on the polysilicon gate (12), it is characterized in that, set There is a P-type well area array (17) composed of P-type well area units (6b), and the P-type well area array (17) is located between the N-type buffer area (5) and the P-type well area (6a), The width of the P-type well region unit (6b) gradually increases from the N-type buffer region (5) to the P-type well region (6a), and the drain metal wiring (15) is on the surface of the dielectric isolation oxide layer (13) Extending and crossing the field oxide layer (11), the P-type well region array (17) is located under the drain metal wiring (15). 2. An ultra-thin lateral double-diffused metal-oxide-semiconductor field effect transistor according to claim 1, characterized in that the junction depth of the P-type well region unit (6b) is within 0.5 μm. 3. a kind of preparation method of a kind of ultra-thin lateral double diffused metal oxide semiconductor field effect transistor described in claim 1, is characterized in that, comprises the following steps: The first step: prepare the P-type silicon substrate (1), Step 2: Deposit a buried oxide layer (2), then perform epitaxial growth (3), ion implant phosphorus to form an N-type well region (4), ion implant arsenic and phosphorus to form an N-type buffer zone (5), anneal, Step 3: Deposit photoresist, prepare a mask whose window size starts from N-type buffer zone from small to large, photolithography, ion implantation of boron to generate P-type well region unit (6b), annealing, Step 4: Deposit silicon nitride, photolithography to form an active region, etch silicon nitride, then grow field oxygen, and perform field implantation, and ion implant boron fluoride to change the channel doping concentration and adjust the channel threshold voltage, and then grow a layer with a thickness of Gate oxide layer (10), deposit and etch polysilicon to form polysilicon gate and polysilicon field plate, ion implant boron to form P-type well region (6a), Step 5: Photolithography, ion implantation of phosphorus and arsenic to generate N-type source region (8) and N-type drain region (9), photolithography, ion implantation of boron fluoride to generate P-type contact region (7), Step 6: Deposit a dielectric isolation oxide layer (13), etch the contact hole, deposit metal aluminum, and etch the aluminum to form a drain metal connection (15) across the field oxide layer (11) and the drain metal connection The line is directly above the P-type well region array (17), and the aluminum is etched to form the source metal wiring (14) and the gate metal wiring (16), and finally the dielectric passivation treatment is performed. 4 . The preparation method according to claim 3 , wherein the thickness of the photoresist deposited in the third step is 1.2 μm, the implantation energy of boron ions is 50 keV, and the implantation dose of boron ions is 8e12 cm ⁻² .