CN103310836A - Write processing method and device of phase change memorizer - Google Patents

Abstract

The invention discloses a write processing method and device of a phase-change memory. When a phase-change memory receives a write request, a first pulse corresponding to a first pulse amplitude is generated according to the write request, and from the write request Read data in the storage unit corresponding to the address information included in the address information; if it is determined that the data to be written included in the write request is not the same as the read data, then the first pulse amplitude is increased to the second pulse amplitude value, generating a write pulse according to the second pulse amplitude, and writing the data to be written into the storage unit corresponding to the address information. Since the time required to increase from the first pulse amplitude to the second pulse amplitude is relatively short, the switching time from reading data to writing data is greatly shortened, so that reading data and writing data can be completed at the same time, not only applicable to synchronization The phase-change memory of the interface can also be applied to the phase-change memory of the asynchronous interface, so as to improve the application performance of the phase-change memory.

Description

Write processing method and device for phase change memory

technical field

Embodiments of the present invention relate to the field of communication technologies, and in particular, to a write processing method and device for a phase change memory.

Background technique

Phase change memory is a new type of semiconductor memory that stores information through different states of phase change materials. When phase change memory performs a write operation, if the data to be written is the same as the existing data in the storage unit, it will still be executed again. In the writing process, the phase change material is heated once by generating a writing pulse. Therefore, as the number of times of writing increases, the loss of the phase change material will be caused, and its resistance value will deviate from the rated range, making it impossible to continue programming, thus causing the failure of the memory cell.

In order to solve the loss problem of the phase change memory, in the first method, before performing the write operation on the phase change memory unit, the data to be written is saved to the latch, and then a read pulse is generated, and the corresponding address from the phase change memory The data is read out, and the read data is compared with the data to be written. Only when the two are different, a write pulse is generated to write the data into the phase change memory unit. However, in this method, since the read and compare operations are performed before the data is written, and then the write pulse is output to start the write operation, the separation of the read and write operations increases the delay in the switching time of the read and write data.

In the second method, when the address of the phase change memory is sent first and the data has not been sent, the data is read from the corresponding address of the phase change memory in advance, and the data is directly compared when the data is sent. If the read data and If the data to be written is the same, the current write operation is abandoned, otherwise the write operation is performed. Although this method can shorten the switching time of reading and writing data, this method is only applicable to the phase change memory of the asynchronous interface, not suitable for the synchronous interface The phase change memory has application limitations.

Contents of the invention

Embodiments of the present invention provide a write processing method and device for a phase change memory, which can further shorten the switching time of reading and writing data while reducing the wear and tear of the phase change memory, improve the performance of the phase change memory, and be compatible with asynchronous and synchronous interfaces.

In a first aspect, a write processing method of a phase change memory is provided, including:

receiving a write request, where the write request includes address information and data to be written;

According to the write request, generate a first pulse corresponding to the first pulse amplitude, and read data from the storage unit corresponding to the address information;

If it is determined that the data to be written is different from the data read in the storage unit corresponding to the address information, then the first pulse amplitude is increased to a second pulse amplitude, according to the second pulse amplitude A write pulse is generated to write the data to be written into the storage unit corresponding to the address information.

Based on the first aspect, in a first possible implementation manner, the generating the first pulse according to the first pulse amplitude, after reading data from the storage unit corresponding to the address information, includes:

If it is determined that the data to be written is the same as the data read from the storage unit corresponding to the address information, no write pulse is generated.

Based on the first aspect or the first possible implementation of the first aspect, in a second possible implementation, after writing the data to be written into the storage unit corresponding to the address information, include:

reducing the amplitude of the second pulse to the amplitude of the first pulse, generating a first pulse according to the amplitude of the first pulse, and reading data from the storage unit corresponding to the address information;

If it is determined that the data read from the storage unit corresponding to the address information is different from the data to be written, an error message is generated.

Based on the first aspect or the first or second possible implementation manner of the first aspect, in a third possible implementation manner, the first pulse amplitude is smaller than the second pulse amplitude.

Based on the first aspect or the first or second possible implementation of the first aspect, in a fourth possible implementation, the write pulse includes a first write pulse or a second write pulse; the first write pulse is SET write pulse, the second write pulse is RESET write pulse;

The second pulse amplitude includes the amplitude corresponding to the first write pulse or the amplitude corresponding to the second write pulse.

In a second aspect, a write processing device for a phase change memory is provided, including:

A receiving module, configured to receive a write request, where the write request includes address information and data to be written;

A first processing module, configured to generate a first pulse corresponding to the first pulse amplitude according to the write request, and read data from a storage unit corresponding to the address information;

The second processing module is configured to increase the first pulse amplitude to a second pulse amplitude if it is determined that the data to be written is different from the data read in the storage unit corresponding to the address information, according to The second pulse amplitude generates a write pulse to write the data to be written into the storage unit corresponding to the address information.

Based on the second aspect, in a first possible implementation manner, the second processing module is further configured to, if it is determined that the data to be written is the same as the data read in the storage unit corresponding to the address information, then Write pulses are not generated.

Based on the second aspect or the first possible implementation manner of the second aspect, in a second possible implementation manner, the device further includes:

A third processing module, configured to reduce the amplitude of the second pulse to the amplitude of the first pulse, generate a first pulse according to the amplitude of the first pulse, and read from the storage unit corresponding to the address information data;

The fourth processing module is configured to generate error information if it is determined that the data read from the storage unit corresponding to the address information is different from the data to be written.

Based on the second aspect or the first or second possible implementation manner of the second aspect, in a third possible implementation manner, the first pulse amplitude is smaller than the second pulse amplitude.

Based on the second aspect or the first or second possible implementation of the second aspect, in a fourth possible implementation, the write pulse includes a first write pulse or a second write pulse; the first write pulse is SET write pulse, the second write pulse is RESET write pulse;

The second pulse amplitude includes the amplitude corresponding to the first write pulse or the amplitude corresponding to the second write pulse.

In the present invention, when receiving a write request, the phase change memory generates a first pulse corresponding to the first pulse amplitude according to the write request, and reads data from the storage unit corresponding to the address information included in the write request ; If it is determined that the data to be written included in the write request is different from the read data, then increasing the first pulse amplitude to a preset second pulse amplitude, according to the second pulse amplitude A write pulse is generated to write the data to be written into the storage unit corresponding to the address information. Since the write pulse increases the first pulse amplitude to the second pulse amplitude on the basis of the first pulse amplitude, the time required to increase from the first pulse amplitude to the second pulse amplitude is relatively short , which saves the reading and writing switching delay, shortens the switching time of reading and writing data, can be compatible with the phase change memory of the synchronous interface and the asynchronous interface, improves the application performance of the phase change memory, and solves the problem of application limitations in the prior art .

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will give a brief introduction to the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are For some embodiments of the present invention, those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is a schematic diagram of the operation sequence of a write processing method of a phase change memory in the prior art;

FIG. 2 is a schematic flowchart of a write processing method of a phase change memory provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a phase change memory;

Fig. 4 is the signal sequence diagram of the phase-change memory of synchronous interface;

Fig. 5 is a schematic diagram of the operation sequence of the write processing method of the phase change memory according to the embodiment of the present invention

6 is a schematic diagram of the principle of an in-phase addition circuit applied in an embodiment of the present invention;

7 is a schematic structural diagram of a write processing device for a phase change memory provided by another embodiment of the present invention;

FIG. 8 is a schematic structural diagram of a write processing device for a phase change memory provided by another embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

The phase change memory described in the embodiment of the present invention includes a phase change memory with an asynchronous interface and a phase change memory with a synchronous interface, wherein the asynchronous interface is similar to the interface of a Static Random Access Memory (SRAM), and the synchronous interface is similar to a dynamic random access memory (SRAM) interface. Memory (Dynamic Random Access Memory, DRAM) interface.

Among them, the phase change memory of the asynchronous interface is characterized in that each time a read and write operation is performed, the asynchronous interface is used to first send address information to read the data in the storage unit to be written, wherein the address information also includes the storage unit to be read and written. The row address and column address of the unit, for example, when the address line is 16 bits, that is, A0-A15, where A0-A6 is the row address, and A7-A15 is the column address; after a period of delay, send the write signal and the data to be written, in The rising edge of the write signal latches the data to be written, and if the data to be written is different from the read data, a write pulse is output, and the data to be written is written into the storage unit.

However, the characteristics of the phase change memory with synchronous interface are that the read and write operations are synchronized with the clock signal, and the row and column addresses are sent in time division, that is to say, for each read and write operation, the row address is sent first (such as A0-A12), and then send the column address (such as A0-A9) and the data to be written at the same time in the next clock cycle, because the memory unit to be read and written cannot be uniquely determined only according to the row address sent first, only according to the row address and Only the column address can uniquely determine the storage unit to be read and written. Since the column address and the data to be written are sent at the same time, the data cannot be read in advance.

At this time, if it is necessary to write the data to be written into the storage unit of the phase change memory of the synchronous interface, according to the existing technology, for example, a write pulse can be directly generated, the phase change material is heated once, and the data to be written is directly written Into the storage unit, that is, do not compare whether the data to be written is the same as the data in the storage unit, and directly execute the writing process; however, as the number of writes increases, the loss of the phase change material will be caused, and its resistance value will deviate from the rated range. Continue programming, thereby causing the failure of the memory cell.

For another example, the data to be written can be stored in the latch, and then the data is read from the corresponding address of the phase change memory, and the read data is compared with the data to be written. Only when the two are different, Data is written into the phase change memory cell. Fig. 1 is a schematic diagram of the operation sequence of a write processing method of a phase change memory in the prior art. As shown in Fig. 1, the data to be written is first latched, and then a read pulse is generated to read the row address and the column address For the data in the corresponding storage unit, compare the read data with the data to be written. If they are not the same, restore the read pulse to low level, and then regenerate the write pulse, that is, increase from low level to high level. Flat, write the data to be written into the storage unit, as shown in Figure 1, the generated read pulse and write pulse are separated, which increases the delay in the switching time of read and write data, and the pulse amplitude of the read pulse is far Lower than the amplitude of the write pulse, the write pulse is a pulse generated from the low level to the high level again after the read pulse returns to the low level, and the time required to increase the level amplitude is relatively longer, further Increased latency for writing data.

Wherein, the write pulse described in this embodiment includes the first write pulse (SET write pulse) or the second write pulse (RESET write pulse), wherein the RESET write pulse is used to transform the phase change material into an amorphous state, that is, a high resistance state, such as the stored information corresponds to a digital logic 0. The waveform amplitude of the RESET write pulse is relatively high, such as 2V, and the temperature generated exceeds the melting temperature of the phase change material, but the duration is very short, generally tens of nanoseconds. The SET write pulse is used to convert the phase change material to a crystalline state, ie a low resistance state, eg the stored information corresponds to a digital logic 1. The amplitude of the SET write pulse is low, such as 1V, and the temperature generated exceeds the crystallization temperature of the phase change material, but is lower than the melting temperature, and lasts for a long time, generally more than 100 nanoseconds.

In view of the problems existing in the prior art, a method for reading and writing processing of a phase change memory provided by an embodiment of the present invention can further shorten the switching time of reading and writing data while reducing the wear and tear of the phase change memory, and improve the performance of the phase change memory , and is compatible with asynchronous and synchronous interfaces.

FIG. 2 is a schematic flowchart of a write processing method of a phase change memory provided by an embodiment of the present invention. As shown in FIG. 2 , the write processing method of the phase change memory of this embodiment may include:

201. The phase change memory receives a write request, where the write request includes address information and data to be written.

Fig. 3 is a structural schematic diagram of a phase-change memory. As shown in Fig. 3, the phase-change memory includes, for example, a storage array, a row and column decoder, control logic, read and write circuits, and a latch. The row and column decoders include a row decoder and a column decoder, which respectively translate the row address and the column address into gate signals on the word line and bit line on the corresponding memory cells. It is used to select a storage unit to be read and written; the read and write circuit is used to generate read pulses and write pulses; the latch is used to temporarily latch the data to be written; the control logic is used to generate timing control signals, for example.

Assuming that the phase change memory of this embodiment is a phase change memory of a synchronous interface, when the phase change memory performs a write operation, Fig. 4 is a signal timing diagram of a phase change memory of a synchronous interface, as shown in Fig. 4, the clock signal is a synchronous clock signal, the chip select signal is used to select the phase change memory that needs to be written, first send the row address signal, and then send the column address signal, write signal and data signal at the same time; wherein, the row and column address signals are generated by the row and column decoders respectively The row strobe signal and column strobe signal are used to select a certain storage unit, and the write signal is used to trigger the read-write circuit to receive the write request, and trigger the latch to save the data to be written to the latch.

Therefore, in this embodiment, when step 201 is implemented, the read-write circuit receives a write request, wherein the write request includes at least address information and data to be written. Wherein, the address information includes a row address and a column address of the storage unit to write data into. The data to be written is data that needs to be written into the storage unit.

202. The phase change memory generates a first pulse corresponding to a first pulse amplitude according to the write request, and reads data from a storage unit corresponding to the address information.

Fig. 5 is a schematic diagram of the operation sequence of the write processing method of the phase change memory according to the embodiment of the present invention. As shown in Fig. 5, the amplitude of the first pulse corresponding to the first pulse is slightly smaller than that corresponding to the first write pulse (SET write pulse). Compared with the amplitude of the read pulse shown in FIG. 1 , the amplitude of the first pulse shown in FIG. 5 is much larger than the amplitude of the read pulse shown in FIG. 1 .

As shown in Figure 4, the first pulse generated by the read-write circuit is generated after the rising edge of the clock signal arrives after receiving the column address, and acts on the phase-change material of the phase-change memory, so that the read-write circuit can store data corresponding to the address information. Read data from the unit.

203. If the phase change memory determines that the data to be written is different from the data read in the storage unit corresponding to the address information, increase the first pulse amplitude to a preset second pulse amplitude, A write pulse is generated according to the second pulse amplitude, and the data to be written is written into the storage unit corresponding to the address information.

For example, after the read-write circuit reads data from the storage unit corresponding to the address information, it compares the read data with the data to be written in the latch, and if it is determined that the data to be written is consistent with the The data read in the storage unit corresponding to the address information is different, then the first pulse amplitude is increased to a preset second pulse amplitude, and a write pulse is generated according to the second pulse amplitude, wherein the write pulse Acting on the phase change material of the phase change memory, the read/write circuit writes the latched data to be written into the storage unit corresponding to the address information.

Wherein, the write pulse described in this embodiment includes the first write pulse (SET write pulse) or the second write pulse (RESET write pulse); the second pulse amplitude includes the first write pulse (SET write pulse) corresponding to Amplitude or the amplitude corresponding to the second write pulse (RESET write pulse).

For example, when the data to be written is 1 and the data of the current storage unit is 0, the generated write pulse is the first write pulse (SET write pulse), when the data to be written is 0, the data of the current storage unit is 1 , the generated write pulse is the second write pulse (RESET write pulse).

In this embodiment, the generated write pulse is based on the first pulse amplitude, and the first pulse amplitude is increased to the second pulse amplitude, further, the first pulse amplitude is slightly smaller than the first write pulse ( SET write pulse) corresponding to the amplitude is much larger than the read pulse amplitude shown in Figure 1, therefore, the time required to increase from the first pulse amplitude to the second pulse amplitude is relatively short; the output delay of the write pulse is saved , so that a write pulse can be generated when the rising edge of the clock signal arrives, and the data to be written can be written into the storage unit corresponding to the address information.

However, in the prior art, it is necessary to restore the read pulse to a low level and regenerate the write pulse. Therefore, it takes a long time to increase from the low level to the corresponding amplitude of the write pulse. It can be seen that the implementation of the present invention For example, the switching time from reading data to writing data can be shortened.

In an optional embodiment of the present invention, in order to increase the first pulse amplitude to the preset second pulse amplitude, it can be realized by using an in-phase addition circuit composed of an operational amplifier, as shown in FIG. 6 The schematic diagram of the principle of the in-phase addition circuit applied in the embodiment of the present invention is shown in Figure 6. Vo=V1+V2+V3 can be calculated according to the theory of the in-phase addition circuit, as long as the three input terminals V1, V2 and When the switch of V3 is turned on and off, different output voltages Vo can be obtained. For example, if V2 and V3 are disconnected at the same time, Vo=V1 is obtained, V3 is disconnected, Vo=V1+V2 is obtained, V2 is disconnected, Vo=V1+V3 is obtained .

Connect the outputs V1, V2, and V3 of the three voltage generators to the three input terminals of the non-inverting adder through switches, so that V1 is equal to the first pulse amplitude (first pulse voltage) corresponding to the first pulse, and V2 V3 is equal to the difference between the voltage corresponding to the second write pulse (RESET write pulse) and the first pulse voltage, and V3 is equal to the difference between the voltage corresponding to the first write pulse (SET write pulse) and the first pulse voltage. For example, when it is necessary to generate the first pulse to read data from the storage unit, you can first turn on V1, turn off V2, V3, and output the first pulse voltage; then turn on V2, and output the second write pulse ( RESET write pulse) voltage, or turn on V3, the output is the first write pulse (SET write pulse) voltage.

For example, after the read-write circuit reads data from the storage unit corresponding to the address information, it compares the read data with the data to be written in the latch, and if it is determined that the data to be written is consistent with the When the data read from the memory cells corresponding to the address information are the same, no write pulse is generated, that is, the amplitude of the first pulse can be restored to a low level. Avoid repeated heating of the phase change material, reduce the loss of the phase change material, and prolong the service life of the phase change memory.

In an optional embodiment of the present invention, after the latched data to be written is written into the storage unit corresponding to the address information, in order to ensure that the data is correctly written into the phase change memory, while saving In the switching time from writing data to reading data, the amplitude of the second pulse corresponding to the write pulse can be reduced to the amplitude of the first pulse, and the first pulse is generated according to the amplitude of the first pulse, from the address Read data in the storage unit corresponding to the information; if it is determined that the data read in the storage unit corresponding to the address information is different from the data to be written, an error message is generated, for example, the error message is recorded in the phase change memory In the status register of the software, it can be read and identified by the software and a solution (such as rewriting) can be taken.

In the embodiment of the present invention, when receiving a write request, the phase change memory generates a first pulse corresponding to the first pulse amplitude according to the write request, and reads from the storage unit corresponding to the address information included in the write request. Fetching data; if it is determined that the data to be written included in the write request is different from the read data, then the first pulse amplitude is increased to a preset second pulse amplitude, according to the second pulse The amplitude generates a write pulse to write the data to be written into the storage unit corresponding to the address information.

Since the write pulse generated in this embodiment is based on the first pulse amplitude, the first pulse amplitude is increased to the second pulse amplitude, and further, the first pulse amplitude is slightly smaller than the first write pulse ( SET write pulse) corresponding to the amplitude is much larger than the read pulse amplitude of the prior art, therefore, the time required to increase from the first pulse amplitude to the second pulse amplitude is relatively short; the output delay of the write pulse is saved , so that a write pulse can be generated when the rising edge of the clock signal arrives, and the data to be written can be written into the storage unit corresponding to the address information. Since the time required to increase from the first pulse amplitude to the second pulse amplitude is relatively short, the switching time from reading data to writing data is greatly shortened, and it can be applied not only to phase-change memories with synchronous interfaces, but also to asynchronous The phase change memory of the interface improves the application performance of the phase change memory.

Fig. 7 is a schematic structural diagram of a write processing device of a phase change memory provided by another embodiment of the present invention, which may specifically be a read and write circuit, as shown in Fig. 7, including:

A receiving module 71, configured to receive a write request, where the write request includes address information and data to be written;

The first processing module 72 is configured to generate a first pulse corresponding to the first pulse amplitude according to the write request, and read data from the storage unit corresponding to the address information;

The second processing module 73 is configured to increase the amplitude of the first pulse to a preset second pulse if it is determined that the data to be written is different from the data read in the storage unit corresponding to the address information Amplitude, generating a write pulse according to the second pulse amplitude, and writing the data to be written into the storage unit corresponding to the address information.

For example, the second processing module 73 is further configured to not generate a write pulse if it is determined that the data to be written is the same as the data read from the storage unit corresponding to the address information.

For example, the device also includes:

The third processing module 74 is configured to reduce the amplitude of the second pulse to the amplitude of the first pulse, generate a first pulse according to the amplitude of the first pulse, and read from the storage unit corresponding to the address information fetch data;

The fourth processing module 75 is configured to generate error information if it is determined that the data read from the storage unit corresponding to the address information is different from the data to be written.

For example, the first pulse amplitude is smaller than the second pulse amplitude.

For example, the write pulse includes a first write pulse or a second write pulse; the second pulse amplitude includes an amplitude corresponding to the first write pulse or an amplitude corresponding to the second write pulse.

For specific implementation of each of the above modules, reference may be made to relevant descriptions in the embodiment shown in FIG. 2 , and details are not repeated here.

Since the write pulse generated in this embodiment is based on the first pulse amplitude, the first pulse amplitude is increased to the second pulse amplitude, and further, the first pulse amplitude is slightly smaller than the first write pulse ( SET write pulse) corresponding to the amplitude is much larger than the read pulse amplitude of the prior art, therefore, the time required to increase from the first pulse amplitude to the second pulse amplitude is relatively short; the output delay of the write pulse is saved , so that a write pulse can be generated when the rising edge of the clock signal arrives, and the data to be written can be written into the storage unit corresponding to the address information. Since the time required to increase from the first pulse amplitude to the second pulse amplitude is relatively short, the switching time from reading data to writing data is greatly shortened, and it can be compatible with phase-change memories with synchronous and asynchronous interfaces, improving phase change memory application performance.

Fig. 8 is a schematic structural diagram of a write processing device of a phase change memory provided by another embodiment of the present invention, which may specifically be a read and write circuit, as shown in Fig. 8, including:

a receiver 81, configured to receive a write request, where the write request includes address information and data to be written;

In-phase addition circuit 82, configured to generate a first pulse corresponding to the first pulse amplitude according to the write request;

A processor 83, configured to read data from the storage unit corresponding to the address information according to the first pulse generated by the in-phase addition circuit 82;

The processor 83 is further configured to determine whether the data to be written received by the receiver 81 is the same as the data read in the storage unit corresponding to the address information;

The in-phase addition circuit 82 is also used to increase the amplitude of the first pulse to a preset value when the processor 83 determines that the data to be written is different from the data read in the storage unit corresponding to the address information. a second pulse amplitude, generating a write pulse according to the second pulse amplitude;

The processor 83 is further configured to write the data to be written into the storage unit corresponding to the address information on the basis of the write pulse generated by the in-phase addition circuit 82 .

The in-phase addition circuit 82 is also used for not generating a write pulse when the processor 83 determines that the data to be written is the same as the data read in the storage unit corresponding to the address information, that is, the in-phase addition circuit 82 converts the The amplitude of the first pulse is reduced to a low level (return to zero);

For example, after writing the data to be written into the storage unit corresponding to the address information;

The in-phase addition circuit 82 is also used to reduce the amplitude of the second pulse to the amplitude of the first pulse, and generate the first pulse according to the amplitude of the first pulse;

The processor 83 is further configured to read data from the storage unit corresponding to the address information on the basis of the first pulse generated by the in-phase addition circuit 82;

The processor 83 is further configured to determine that if the data read from the storage unit corresponding to the address information is different from the data to be written, an error message is generated.

For example, the first pulse amplitude is smaller than the second pulse amplitude.

For example, the write pulse includes a first write pulse or a second write pulse; the second pulse amplitude includes an amplitude corresponding to the first write pulse or an amplitude corresponding to the second write pulse.

For specific implementation of each of the above modules, reference may be made to relevant descriptions in the embodiment shown in FIG. 2 , and details are not repeated here.

Since the write pulse generated in this embodiment is based on the first pulse amplitude, the first pulse amplitude is increased to the second pulse amplitude, and further, the first pulse amplitude is slightly smaller than the first write pulse ( SET write pulse) corresponding to the amplitude is much larger than the read pulse amplitude of the prior art, therefore, the time required to increase from the first pulse amplitude to the second pulse amplitude is relatively short; the output delay of the write pulse is saved , so that a write pulse can be generated when the rising edge of the clock signal arrives, and the data to be written can be written into the storage unit corresponding to the address information. Since the time required to increase from the first pulse amplitude to the second pulse amplitude is relatively short, the switching time from reading data to writing data is greatly shortened, and it can be applied to phase-change memory with a synchronous interface, improving the application of phase-change memory performance.

In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware, or in the form of hardware plus software functional units.

The above-mentioned integrated units implemented in the form of software functional units may be stored in a computer-readable storage medium in the form of codes. The above codes are stored in a computer-readable storage medium, and include several instructions for causing a processor or a hardware circuit to execute some or all steps of the methods described in various embodiments of the present invention. The aforementioned storage media include: a miniature high-capacity mobile storage disk without a physical drive, a mobile hard disk, a read-only memory (English: Read-Only Memory, ROM for short), and a random access memory (English: Random Access Memory). AccessMemory, referred to as RAM), magnetic disk or optical disk and other media that can store program code.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the protection scope of the technical solutions of the various embodiments of the present invention.

Claims (10)

1. A phase transition storage write disposal route, it is characterized in that, comprising:

   Receive write request, comprise address information and data to be written in the described write request;

   According to described write request, produce first pulse corresponding with the first pulse amplitude, reading out data from storage unit corresponding to described address information;

   If determine that the data that read in described data to be written and storage unit corresponding to described address information are not identical, then described the first pulse amplitude is increased to the second pulse amplitude, produce write pulse according to described the second pulse amplitude, described data to be written are written in storage unit corresponding to described address information.
2. 2. method according to claim 1 is characterized in that, describedly produces the first pulse according to the first pulse amplitude, after the reading out data, comprising from storage unit corresponding to described address information:

   If determine that the data that read in described data to be written and storage unit corresponding to described address information are identical, then do not produce write pulse.
3. 3. method according to claim 1 and 2 is characterized in that, be written to described data to be written in storage unit corresponding to described address information after, comprising:

   Described the second pulse amplitude is reduced to described the first pulse amplitude, produces the first pulse according to described the first pulse amplitude, reading out data from storage unit corresponding to described address information;

   If determine that the data that read in storage unit corresponding to described address information are not identical with described data to be written, then generation error information.
4. 4. each described method is characterized in that according to claim 1-3, and described the first pulse amplitude is less than the second pulse amplitude.
5. 5. each described method is characterized in that according to claim 1-3, and described write pulse comprises the first write pulse or the second write pulse; The first write pulse is the SET write pulse, and described the second write pulse is the RESET write pulse;

   Described the second pulse amplitude comprises amplitude or amplitude corresponding to the second write pulse that the first write pulse is corresponding.
6. 6. the read/write processing of a phase transition storage is characterized in that, comprising:

   Receiver module is used for receiving write request, comprises address information and data to be written in the described write request;

   The first processing module is used for according to described write request, produces first pulse corresponding with the first pulse amplitude, reading out data from storage unit corresponding to described address information;

   The second processing module, if for determining that the data that storage unit corresponding to described data to be written and described address information reads are not identical, then described the first pulse amplitude is increased to the second pulse amplitude, produce write pulse according to described the second pulse amplitude, described data to be written are written in storage unit corresponding to described address information.
7. 7. device according to claim 6 is characterized in that, described the second processing module is not if also for determining that the data that storage unit corresponding to described data to be written and described address information reads are identical, then produce write pulse.
8. 8. according to claim 6 or 7 described devices, it is characterized in that, also comprise:

   The 3rd processing module is used for described the second pulse amplitude is reduced to described the first pulse amplitude, produces the first pulse according to described the first pulse amplitude, reading out data from storage unit corresponding to described address information;

   The manages module everywhere, if be used for determining that the data that storage unit corresponding to described address information read are not identical with described data to be written, and generation error information then.
9. 9. each described device is characterized in that according to claim 6-8, and described the first pulse amplitude is less than the second pulse amplitude.
10. 10. each described device is characterized in that according to claim 6-8, and described write pulse comprises the first write pulse or the second write pulse; The first write pulse is the SET write pulse, and described the second write pulse is the RESET write pulse;

    Described the second pulse amplitude comprises amplitude or amplitude corresponding to the second write pulse that the first write pulse is corresponding.

Images