CN103295642A - Shifting register and panel display - Google Patents

Abstract

The technical solution of the present invention provides a shift register and a flat panel display device, the control end of the first transistor of the shift register receives the first clock signal, the first end receives the output signal or the start signal of the shift register of the upper stage, The second end is connected to the first end of the capacitor and the control end of the second transistor; the first end of the second transistor receives the second clock signal, and the second end is connected to the second end of the capacitor, the first end of the third transistor, the fourth The first end of the transistor and the control end of the fifth transistor, the second end of the second transistor outputs the output signal of the shift register of the current stage; the control end of the third transistor receives the first clock signal, and the second end is connected to the fourth transistor The second terminal and the second terminal of the fifth transistor, the second terminal of the third transistor receives a low level signal; the control terminal of the fourth transistor is connected to the first terminal of the fifth transistor and the negative terminal of the unit; the positive terminal of the transistor unit Receive a second clock signal.

Description

Shift register and flat panel display device

technical field

The invention relates to the field of liquid crystal display, in particular to a shift register and a flat panel display device.

Background technique

In liquid crystal displays (LCDs), or in other flat panel displays with similar structures such as e-books and organic light-emitting diode flexible displays, gate drive circuits and data drive circuits are attached to the display panel at a later stage during assembly. , and the cost of the drive circuit is high, and the assembly and attachment process also takes a lot of work, manpower and time.

In order to reduce the cost, the Amorphous Silicon Gate (ASG) technology was proposed. ASG technology is to synchronously integrate the gate drive circuit in the non-display area of the display panel, such as the frame area of the liquid crystal display panel, during the manufacturing process of the flat panel display. Since the use of ASG technology can save the original gate drive circuit, improve integration, reduce external components, and reduce manufacturing costs, ASG technology is increasingly used.

Next to each row of pixel units, the circuit structure that independently generates gate driving signals is called an ASG unit. The ASG unit usually has a shift register structure, and the overall ASG driving circuit is the repetition of the ASG unit in all rows, or the interlaced repetition of the ASG unit in odd and even rows. The gate driving signal is connected to the switching element (such as the thin film transistor TFT) of the pixel unit in the pixel array, and controls the switching element to be turned on and off.

As shown in FIG. 1 , the ASG driving circuit is composed of a series of ASG units (shift registers) 121 . The ASG unit 121 includes an input node IN, an output node OUT, a voltage source node V1, and clock signal nodes C1 and C2. The input node IN inputs the start signal or the upper-level output signal STV, the output node OUT outputs the current-level output signal GoutN, the voltage source node V1 inputs the low-level signal VGL, and the clock signal nodes C1 and C2 input the phase-complementary clock signals CLK and CLKB.

As shown in Figure 2 and Figure 3, the low-level signal VGL is always low-level, and the working process of the ASG unit is roughly as follows:

When the output signal STV of the upper stage is high level, the clock signal CLKB is low level, and the clock signal CLK is high level: the high level clock signal CLK turns on the MOS transistor T1 and the MOS transistor T3; the MOS transistor T1 turns on Afterwards, the voltage at point P becomes the same high level as the output signal STV of the previous stage; the high level at point P turns on the MOS transistor T2; the low level signal VGL and the clock signal CLKB pass through the turned on The MOS transistor T2 and the MOS transistor T3 make the output signal GoutN low.

When the output signal STV of the upper stage changes from high level to low level, the clock signal CLKB changes to high level, and the clock signal CLK changes to low level: the low level clock signal CLK turns off the MOS transistor T1 and the MOS transistor T3 ; The high level of point P maintains the conduction of MOS transistor T2, and the high level clock signal CLKB makes the output signal GoutN change from low level to high level, and increases the high level voltage value of point P through the capacitor Ct .

The MOS transistor T3 is usually a pull-down transistor of the ASG unit. It can be seen from the above working process that the pull-down transistor is in an off state when the clock signal CLK is at a low level. The time when the clock signal CLK is at low level accounts for about 50% of the entire cycle, that is to say, the pull-down transistor is in the off state for 50% of the entire cycle, and the cut-off pull-down transistor causes the output node OUT to be in a floating state.

The output node OUT in the floating state is severely crosstalked by external signals, the output signal is unstable, and the output waveform is seriously deformed after a certain number of stages.

Contents of the invention

The technical solution of the present invention solves the problem that the output node of the existing shift register is seriously crosstalked by external signals, and the output signal is unstable.

The technical solution of the present invention provides a shift register, including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a transistor unit, and a capacitor;

The control terminal of the first transistor receives the first clock signal, the first terminal receives the output signal or the start signal of the upper stage shift register, and the second terminal is connected to the first terminal of the capacitor and the control terminal of the second transistor ;

The first end of the second transistor receives the second clock signal, the second end is connected to the second end of the capacitor, the first end of the third transistor, the first end of the fourth transistor, and the control end of the fifth transistor, The second terminal of the second transistor outputs the output signal of the shift register of the current stage;

The control terminal of the third transistor receives the first clock signal, the second terminal is connected to the second terminal of the fourth transistor and the second terminal of the fifth transistor, and the second terminal of the third transistor receives low level signal;

The control terminal of the fourth transistor is connected to the first terminal of the fifth transistor and the negative terminal of the unit;

the positive terminal of the transistor unit receives the second clock signal;

The on-resistance of the transistor unit is greater than the on-resistance of the fifth transistor.

Optionally, the first clock signal is a complementary signal of the second clock signal, and the low-level signal is less than or equal to a low-level voltage value of the first clock signal.

Optionally, the shift register further includes: a seventh transistor, the control terminal of the seventh transistor receives the output signal of the next-stage shift register, the first terminal is connected to the first terminal of the capacitor, and the second terminal receiving the low level signal.

Optionally, the shift register further includes: an eighth transistor, the control terminal of the eighth transistor receives the first clock signal, the first terminal is connected to the control terminal of the fourth transistor, and the second terminal receives the clock signal. low-level signal.

Optionally, the transistor unit includes a sixth transistor, the control terminal of the sixth transistor is connected to the first terminal of the sixth transistor as the positive terminal of the transistor unit, and the second terminal of the sixth transistor serves as On the negative terminal of the transistor unit, the on-resistance of the sixth transistor is greater than the on-resistance of the fifth transistor.

Optionally, the transistor unit includes a diode, the anode of the diode is used as the positive terminal of the transistor unit, and the cathode of the diode is used as the negative terminal of the transistor unit, and the on-resistance of the diode is greater than that of the fifth transistor on-resistance.

Optionally, the transistor is a MOS transistor, and the control terminal of the transistor is the gate of the MOS transistor;

The first end of the transistor is the source of the MOS transistor, and the second end is the drain of the MOS transistor, or the first end of the transistor is the drain of the MOS transistor, and the second end is the drain of the MOS transistor. source of the MOS transistor.

Optionally, the width-to-length ratio of the fifth transistor is greater than the width-to-length ratio of the sixth transistor.

Optionally, the width-to-length ratio of the fifth transistor is greater than five times the width-to-length ratio of the sixth transistor.

The technical solution of the present invention also provides a flat panel display device, comprising: a pixel unit and the above-mentioned shift register, and the shift register is suitable for generating a gate signal required by the pixel unit.

Compared with the prior art, the technical solution of the present invention can continuously maintain the low level of the output signal after the output signal of the shift register generates a pulse, prevent the output node of the shift register from floating, and avoid the output signal being crosstalked by external signals , the output signal is stable.

Description of drawings

Fig. 1 is the structural representation of existing shift register;

Fig. 2 is a structural schematic diagram of an existing shift register unit;

Fig. 3 is a schematic diagram of input and output signal waveforms of the shift register unit shown in Fig. 2;

Fig. 4 is a schematic structural diagram of the implementation of the shift register of the present invention;

Fig. 5 is a schematic diagram of input and output signal waveforms of the shift register shown in Fig. 4;

Fig. 6 is a schematic structural diagram of the second implementation of the shift register of the present invention;

Fig. 7 is the implementation three structure schematic diagrams of the shift register of the present invention;

FIG. 8 is a schematic diagram of input and output signal waveforms of the shift register unit shown in FIG. 7 .

Detailed ways

The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. In the following paragraphs the invention is described more specifically by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description.

As shown in Figure 4, Embodiment 1 of the present invention provides a shift register, including: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a transistor unit 11 and a capacitor C1.

The control terminal of the first transistor M1 receives the first clock signal CLK, the first terminal receives the output signal of the upper stage shift register or the start signal STV, and the second terminal is connected to the first terminal and the second terminal of the capacitor C1. A control terminal of the transistor M2;

The first end of the second transistor M2 receives the second clock signal CLKB, and the second end is connected to the second end of the capacitor C1, the first end of the third transistor M3, the first end of the fourth transistor M4, and the fifth The control terminal of the transistor M5, the second terminal of the second transistor M2 outputs the output signal GoutN of the shift register of the current stage;

The control terminal of the third transistor M3 receives the first clock signal CLK, the second terminal is connected to the second terminal of the fourth transistor M4 and the second terminal of the fifth transistor M5, and the third transistor M3 The second end of the receiving low-level signal VGL;

The control terminal of the fourth transistor M4 is connected to the first terminal of the fifth transistor M5 and the negative terminal of the transistor unit 11;

The positive end of the transistor unit 11 receives the second clock signal CLKB;

The on-resistance of the transistor unit 11 is greater than the on-resistance of the fifth transistor M5.

The capacitor C1 can store charges and act as a switch for the second transistor M2.

The transistor unit 11 may include a sixth transistor M6, the control terminal of the sixth transistor M6 is connected to the first terminal of the sixth transistor M6 as the positive terminal of the transistor unit 11, and the first terminal of the sixth transistor M6 The two terminals serve as negative terminals of the transistor unit 11 , and the on-resistance of the sixth transistor M6 is greater than the on-resistance of the fifth transistor M5 .

The turn-on resistance of the sixth transistor M6 may be greater than the turn-on resistance of the fifth transistor M5. Specifically, the fifth transistor M5 and the sixth transistor M6 are MOS transistors, and the aspect ratio of the fifth transistor M5 is greater than that of the sixth transistor M6. Optionally, the width-to-length ratio of the fifth transistor M5 is greater than five times the width-to-length ratio of the sixth transistor M6.

The transistor unit 11 may also include a diode, the anode of the diode is used as the positive terminal of the transistor unit, and the cathode of the diode is used as the negative terminal of the transistor unit, and the on-resistance of the diode is greater than that of the fifth transistor. on-resistance.

Referring to Fig. 4 and Fig. 5, the first clock signal CLK in the first embodiment is the complementary signal of the second clock signal CLKB, and the low-level signal VGL is less than or equal to the low-level voltage of the first clock signal CLK value. The working process of the shift register is roughly as follows:

When the output signal of the upper-stage shift register or the start signal STV is at a high level, the first clock signal CLK is at a high level, and the second clock signal CLKB is at a low level:

The high-level first clock signal CLK turns on the first transistor M1 and the third transistor M3, and the low-level clock signal CLKB turns off the sixth transistor M6; after the first transistor M1 is turned on, the voltage at point P becomes equal to The output signal of the upper stage shift register or the same high level as the start signal STV; the high level at point P turns on the second transistor M2; the low level signal VGL and the second clock signal CLKB pass through The turned-on third transistor M3 and the second transistor M2 make the output signal GoutN become low level; the low level output signal GoutN makes the fifth transistor M5 cut off; the cutoff of the fifth transistor M5 and the sixth transistor M6 causes the Q point It is in a floating state, and the voltage value of point Q in the floating state is between high level and low level, so that the fourth transistor M4 cannot be turned on, and the fourth transistor M4 is turned off.

When the output signal of the upper-stage shift register or the start signal STV changes from high level to low level, the first clock signal CLK is low level, and the second clock signal CLKB is high level:

The low-level first clock signal CLK turns off the first transistor M1 and the third transistor M3, and the high-level clock signal CLKB turns on the sixth transistor M6; the high level at point P keeps the second transistor M2 turned on; The high-level second clock signal CLKB makes the output signal GoutN change from low level to high level, and increases the high-level voltage value of P point through the capacitor C1; the high-level output signal GoutN makes the fifth transistor M5 is turned on, and since the turn-on resistance of the sixth transistor M6 is greater than that of the fifth transistor M5, the voltage at point Q remains in a floating state, and the fourth transistor M4 is turned off.

When the output signal of the shift register at the upper stage or the start signal STV is kept at low level, the first clock signal CLK is at high level, and the second clock signal CLKB is at low level:

The high-level first clock signal CLK turns on the first transistor M1 and the third transistor M3, and the low-level clock signal CLKB turns off the sixth transistor M6; after the first transistor M1 is turned on, the voltage at point P becomes equal to The output signal of the upper stage shift register or the same low level as the start signal STV; the low level at point P makes the second transistor M2 cut off; the low level signal VGL of the low level passes through the third transistor M3 which is turned on The output signal GoutN is low level; the low level output signal GoutN causes the fifth transistor M5 to be cut off; the fifth transistor M5 and the sixth transistor M6 are cut off so that the Q point voltage is still in a floating state, and the fourth transistor M4 is cut off;

When the output signal of the upper-stage shift register or the start signal STV is kept at low level, the first clock signal CLK is at low level, and the second clock signal CLKB is at high level:

The low-level first clock signal CLK turns off the first transistor M1 and the third transistor M3, and the high-level clock signal CLKB turns on the sixth transistor M6; the low level at point P keeps the second transistor M2 off, and the output The signal GoutN is still low level; the low level output signal GoutN keeps the fifth transistor M5 off; the turned-on sixth transistor M6 makes the Q point voltage become the same high level as the second clock signal CLKB; the high level The flat Q-point voltage turns on the fourth transistor M4; the low-level signal VGL maintains the output signal GoutN at a low level through the turned-on fourth transistor M4.

Thereafter, the sixth transistor M6 is periodically turned on and off according to the second clock signal CLKB, and the Q point changes periodically between a high level and a floating state.

It can be seen from the above working process that the output signal GoutN keeps low level after generating a pulse, and when the first clock signal CLK is high level, the low level signal VGL maintains the low level of the output signal GoutN through the turned-on third transistor M3. When the second clock signal CLKB is at a high level, the low level signal VGL maintains the low level of the output signal GoutN through the turned-on fourth transistor M4. Therefore, applying the technical solution of the first embodiment can prevent the output node of the shift register from being in a floating state, prevent the output signal from being disturbed by external signals, and stabilize the output signal.

As shown in Figure 6, the difference between the second embodiment of the present invention and the first embodiment is that it also includes a seventh transistor M7, the control terminal of the seventh transistor M7 receives the output signal GoutN+1 of the shift register of the next stage, and the first The end is connected to the first end of the capacitor C1, and the second end receives the low-level signal VGL.

Continuing to refer to Fig. 5, the seventh transistor M7 is turned on when the output signal GoutN+1 of the next-stage shift register is at a high level, and the low-level signal VGL makes the low level of point P more stable, which reduces the shift of the previous stage. Glitch effect on the output signal of the bit register or on the start signal STV.

As shown in FIG. 7 , the difference between Embodiment 3 of the present invention and Embodiment 1 is that it further includes an eighth transistor M8, the control terminal of the eighth transistor M8 receives the first clock signal CLK, and the first terminal is connected to the first clock signal CLK. The control terminal and the second terminal of the four transistors M4 receive the low level signal VGL.

As shown in FIG. 8 , when the second clock signal CLKB is at a high level, the sixth transistor M6 is turned on, and the high level second clock signal CLKB makes the voltage at point Q become high through the turned-on sixth transistor M6; When the clock signal CLK is at a high level, the eighth transistor M8 is turned on, and the low level signal VGL passes through the turned-on eighth transistor M8 so that the voltage at point Q becomes low. In this way, the floating state of point Q can be avoided, and the periodic turn-on and turn-off of the fourth transistor M4 is ensured, further stabilizing the output signal GoutN.

The transistor in the above embodiment may be a MOS transistor, the control terminal of the transistor is the gate of the MOS transistor; the first terminal of the transistor is the source of the MOS transistor, and the second terminal is the gate of the MOS transistor. The drain, or the first terminal of the transistor is the drain of the MOS transistor, and the second terminal is the source of the MOS transistor.

An embodiment of the present invention also provides a flat panel display device, including: a pixel unit and the shift register described in the above embodiment, and the shift register described in the above embodiment is suitable for generating a gate signal required by the pixel unit.

Although the present invention has been disclosed above with preferred embodiments, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be defined by the claims.

Claims (10)

1. A shift register, characterized in that, comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a transistor unit and a capacitor; The control terminal of the first transistor receives the first clock signal, the first terminal receives the output signal or the start signal of the upper stage shift register, and the second terminal is connected to the first terminal of the capacitor and the control terminal of the second transistor ; The first end of the second transistor receives the second clock signal, the second end is connected to the second end of the capacitor, the first end of the third transistor, the first end of the fourth transistor, and the control end of the fifth transistor, The second terminal of the second transistor outputs the output signal of the shift register of the current stage; The control terminal of the third transistor receives the first clock signal, the second terminal is connected to the second terminal of the fourth transistor and the second terminal of the fifth transistor, and the second terminal of the third transistor receives low level signal; The control terminal of the fourth transistor is connected to the first terminal of the fifth transistor and the negative terminal of the transistor unit; the positive terminal of the transistor unit receives the second clock signal; The on-resistance of the transistor unit is greater than the on-resistance of the fifth transistor. 2. The shift register according to claim 1, wherein the first clock signal is a complementary signal of the second clock signal, and the low-level signal is less than or equal to that of the first clock signal Low level voltage value. 3. The shift register according to claim 1, further comprising: a seventh transistor, the control terminal of the seventh transistor receives the output signal of the next stage shift register, and the first terminal is connected to the capacitor The first terminal, the second terminal receives the low level signal. 4. The shift register according to claim 1, further comprising: an eighth transistor, the control terminal of the eighth transistor receives the first clock signal, and the first terminal is connected to the fourth transistor. The control terminal, the second terminal receives the low level signal. 5. The shift register according to claim 1, wherein the transistor unit comprises a sixth transistor, and the control terminal of the sixth transistor is connected to the first terminal of the sixth transistor as the transistor unit. The positive terminal, the second terminal of the sixth transistor is used as the negative terminal of the transistor unit, and the on-resistance of the sixth transistor is greater than the on-resistance of the fifth transistor. 6. The shift register according to claim 5, wherein the transistor unit comprises a diode, the anode of the diode is used as the positive terminal of the transistor unit, and the cathode of the diode is used as the negative terminal of the transistor unit, The on-resistance of the diode is greater than the on-resistance of the fifth transistor. 7. The shift register according to any one of claims 1-6, wherein the transistor is a MOS transistor, and the control terminal of the transistor is the gate of the MOS transistor; The first end of the transistor is the source of the MOS transistor, and the second end is the drain of the MOS transistor, or the first end of the transistor is the drain of the MOS transistor, and the second end is the drain of the MOS transistor. source of the MOS transistor. 8. The shift register according to claim 7, wherein the width-to-length ratio of the fifth transistor is greater than the width-to-length ratio of the sixth transistor. 9. The shift register according to claim 8, wherein the width-to-length ratio of the fifth transistor is greater than five times the width-to-length ratio of the sixth transistor. 10. A flat panel display device, characterized in that it comprises: a pixel unit and the shift register according to any one of claims 1-9, and the shift register according to any one of claims 1-9 is suitable for generating the The gate signal required by the above pixel unit.

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