CN103117739B - GaN-based enhancement-depletion type level switch circuit - Google Patents

Abstract

The invention discloses a gallium nitride-based enhanced depletion type level conversion circuit, which mainly solves the disadvantage that the prior art cannot integrate the level conversion circuit and the gallium nitride-based circuit into one substrate. The present invention includes four parts: the first inverting circuit, the first output circuit, the second inverting circuit, and the second output circuit. The first inverting circuit inverts the input level, the first output circuit pulls down the inverted level of the first inverting circuit, the second inverting circuit inverts the output of the first output circuit, and the second output circuit inverts the output of the first inverting circuit. The level is pulled down after the phase inversion of the two inverting circuits. The circuit structure of the invention is simple, the technology of the semiconductor device used is simple to realize, and the level conversion circuit and the gallium nitride base circuit can be integrated on one substrate, thereby improving reliability and reducing crosstalk.

Description

Gallium Nitride-Based Enhanced Depletion Mode Level Shifting Circuit

technical field

The invention relates to the field of electronic technology, and further relates to a gallium nitride-based enhanced depletion type level conversion circuit in the field of semiconductor integrated circuit technology. The invention can be used to control the switch in the gallium nitride-based microwave radio frequency field, so that the radio frequency signal passing through the switch is turned off and on.

Background technique

At present, with the maturity of semiconductor technology, microwave radio frequency monolithic systems are becoming more and more mature, generally composed of digital logic units and microwave radio frequency circuits. Gallium nitride-based microwave radio frequency circuits mostly use relatively mature depletion-mode devices, and the depletion channel of the depletion-mode device is naturally formed by the AlGaN/GaN heterojunction, resulting in a negative turn-on voltage, and Generally, it is -2V--2.5V. As the front-end of the system, GaN-based RF circuits are essential to cooperate with back-end silicon-based circuits. However, most silicon-based integrated circuit interfaces are standard TTL outputs, and their high and low levels are >2.4V and <0.4V respectively, so a special interface-level conversion circuit is required to achieve level conversion to connect GaN Based front-end and silicon-based back-end, thereby ensuring the normal operation of switches composed of depletion-mode devices in gallium nitride-based circuits. Generally, it can be considered that if the converted voltage is less than or equal to -3.5V, the switch is turned off, and when the voltage is greater than or equal to -1V, the switch is turned on. In order to solve the above problems, there are already many silicon-based circuits to realize level conversion.

The patented technology "Double Control Model Level Conversion Circuit" (application number 201120421799.3, authorized announcement number CN 202334487 U) owned by Nima Electronic Product Appearance Design Studio of Chengdu High-tech Zone discloses a level conversion circuit suitable for control switches . The circuit includes a dual-channel NPN transistor, an output signal circuit and a control signal input circuit connected to the dual-channel NPN transistor T2 at the same time. This circuit has minimal cost. However, the shortcomings of this patented technology are: due to the difficulty of p-type doping of gallium nitride materials, the NPN transistors used in this circuit structure cannot be realized on gallium nitride, so the gallium nitride based Circuitry and level conversion circuits are monolithically integrated with the substrate.

The patented technology "digital-analog hybrid multi-channel independent control switch circuit" (application number 200810238937.7, application publication number CN 101753121A) owned by the Institute of Microelectronics, Chinese Academy of Sciences discloses a level conversion circuit suitable for controlling switches. The circuit includes a PWM controller, an input driver, a level conversion circuit, a current-mode switching circuit and an output voltage circuit, etc. The circuit can significantly increase the switching speed of the FET. However, the disadvantage of this patented technology is that although it is technically possible to connect the patented technology and GaN-based circuits through gold wires and then encapsulate them in a housing, the gold wires will cause signal crosstalk, which may affect The normal realization of the circuit function.

Contents of the invention

The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art, and propose a gallium nitride-based enhanced depletion type level conversion circuit. In order to improve the performance of gallium nitride-based circuits, the present invention designs a realizable gallium nitride-based enhanced depletion-type level conversion circuit, which realizes the integration of on-chip systems, reduces crosstalk between connections, and can be combined with TTL circuit connection use.

To achieve the above object, the present invention includes a first inverting circuit, a first output circuit, a second inverting circuit, and a second output circuit. The output end of the first inverting circuit is connected to the input end of the first output circuit, the output end of the first output circuit is connected to the input end of the second inverting circuit, the output end of the second inverting circuit is connected to the second output The input terminals of the circuit are connected.

The drain of the depletion-type high electron mobility transistor T1 in the first inverting circuit unit is connected to the positive bias line. The pole is connected to the gate of the enhanced high electron mobility transistor T3 in the first output circuit unit; the gate of T2 is connected to the input VIN, and the source of T2 is grounded.

The drain of T3 in the first output circuit unit is connected to the positive bias line, the gate of T3 is connected to the drain of T2, the source of T3 is connected to the positive pole of the Schottky diode D1; the negative pole of D1 is connected to the Schottky diode D2 Anode, the cathode of D2 is connected to the anode of Schottky diode D3, the cathode of D3 is connected to the anode of Schottky diode D4; the cathode of D4 is connected to the drain of depletion-type high electron mobility transistor T4, the gate and source of T4 It is connected to the negative bias line, and the drain of T4 is connected to the gate of the depletion-type high electron mobility transistor T6 and the second output VOUT1.

The drain of the enhanced high electron mobility transistor T5 in the second inverting circuit unit is connected to the positive bias line. The gates of the depletion-type high electron mobility transistor T7 are connected; the gate of T6 is connected to the first output VOUT1, and the source of T6 is grounded.

The drain of T7 in the second output circuit unit is connected to the positive bias line, the gate of T7 is connected to the drain of T6, the source of T7 is connected to the positive pole of the Schottky diode D5; the negative pole of D5 is connected to the Schottky diode D6 The positive pole of D6 is connected to the positive pole of Schottky diode D7, the negative pole of D7 is connected to the positive pole of Schottky diode D8; the negative pole of D8 is connected to the drain of enhanced high electron mobility transistor T8, and the gate and source of T8 connected to the negative bias line, and the drain of T8 connected to the second output VOUT2.

Compared with the prior art, the present invention has the following advantages:

First, because the present invention designs a circuit structure, it overcomes the p-type doping difficulty of gallium nitride material in the prior art, and the NPN transistor used in the structure of the prior art cannot be realized on gallium nitride. The shortcomings of the GaN-based circuit system solve the problem that there is no suitable circuit topology in the integration process of the monolithic GaN-based circuit system. The circuit structure of the present invention is simple, and the semiconductor device technology used is simple, so that the present invention can be based on GaN. Enables monolithic circuit integration that matches the output of standard silicon-based circuits.

Second, since the present invention can realize monolithic integration of gallium nitride-based circuit systems, it overcomes the problem of signal crosstalk that may be caused by using gold wires between silicon-based circuits and gallium nitride-based circuits in the prior art, and solves the problem of silicon-based circuits. The problem of normal expression of circuit functions caused by the interconnection between the circuit and the gallium nitride-based circuit chip makes the present invention have the advantages of reduced error rate of the gallium nitride-based system and more stable performance.

Third, since the present invention can realize monolithic integration of gallium nitride-based radio frequency circuit systems, it overcomes the shortcomings of poor radiation resistance of silicon-based circuits in the prior art, and solves the problem of circuit system performance degradation in special environments such as outer space The problem makes the present invention have the advantages of stronger anti-radiation capability and higher reliability of the circuit system.

Description of drawings

Fig. 1 is a schematic circuit diagram of the present invention;

FIG. 2 is a simulation diagram of the response of output terminal voltages VOUT1 and VOUT2 to input terminal voltage VIN according to the present invention.

Detailed ways:

The present invention will be described in further detail below with reference to the accompanying drawings.

With reference to Fig. 1, circuit structure of the present invention is described as follows:

The invention includes a first output circuit, a second inverting circuit and a second output circuit. The output end of the first inverting circuit is connected to the input end of the first output circuit, the output end of the first output circuit is connected to the input end of the second inverting circuit, the output end of the second inverting circuit is connected to the second output The input terminals of the circuit are connected.

The drain of the depletion-type high electron mobility transistor T1 in the first inverting circuit is connected to the positive bias line VDD. The pole is connected to the gate of the enhanced high electron mobility transistor T3 in the first output circuit unit; the gate of T2 is connected to the input terminal VIN, and the source of T2 is connected to the ground line GND.

The drain of T3 in the first output circuit is connected to the positive bias line VDD, the gate of T3 is connected to the drain of T2, the source of T3 is connected to the anode of the Schottky diode D1; the cathode of D1 is connected to the Schottky diode D2 Anode, the cathode of D2 is connected to the anode of Schottky diode D3, the cathode of D3 is connected to the anode of Schottky diode D4; the cathode of D4 is connected to the drain of depletion-type high electron mobility transistor T4, the gate and source of T4 It is connected to the negative bias line VSS, and the drain of T4 is connected to the gate of the depletion-type high electron mobility transistor T6 and the second output terminal VOUT1.

The enhancement mode high electron mobility transistors T2, T3, T5, T8 have the same aspect ratio, the depletion mode high electron mobility transistors T1, T4, T6, T7 have the same aspect ratio, and the Schottky diodes D1, D2, D3 , D4, D5, D6, D7, D8 have the same physical size.

The operating principle of the first inverting circuit and the first output circuit in the present invention is:

If the input terminal VIN is at a low level, the enhanced high electron mobility transistor T2 is turned off, so the channel resistance of T2 is large, but the gate voltage on the depletion high electron mobility transistor T1 is 0, so the channel resistance is relatively The channel resistance of T2 is much smaller, so the output of the first inverting circuit obtains a voltage close to VDD in the divided voltage of the channel. Because the gate voltage of the enhanced high electron mobility transistor T3 is close to VDD, T3 is turned on. Furthermore, the channel resistance of T3 is smaller than that of T4. After four Schottky diodes D1 , D2 , D3 , D4 step down the voltage, the output terminal VOUT1 of the first output circuit can be adjusted to about 0V.

In the embodiment of the present invention, the width-to-length ratio of T3 and the width-to-length ratio of the depletion-type high electron mobility transistor T4 are 5-8 through process adjustment. This choice is to make T3 have a larger transconductance than T4. Within this range, the channel resistance of T3 can be slightly smaller than the channel resistance of T4 when T3 is turned on, and it can also satisfy the condition of T3 when it is turned off. The lower channel resistance is much larger than that of T4. When the width-to-length ratio is less than 5, the transconductance of T3 is too small, and the voltage division is too small when it is turned on, so that the high level of the output VOUT1 is far less than 0V and the function cannot be realized normally; when the width-to-length ratio is greater than 8 , The transconductance of T3 is too large, and the voltage division is too large in the case of shutdown, so that the low level of the output VOUT1 is much higher than -4V and the function cannot be realized normally.

If the input terminal VIN is at a low voltage, T2 is turned on, and since the width-to-length ratio of T2 and T1 is 5 to 8, the channel resistance of T1 is several times that of T2, so the output of the first inverting circuit To be close to 0V, T3 is turned off, so the channel resistance of T3 is much larger than that of T4, so the output terminal VOUT1 of the first output circuit is close to VSS.

The drain of the enhanced high electron mobility transistor T5 in the second inverting circuit unit is connected to the positive bias line. The gates of the depletion-type high electron mobility transistor T7 are connected; the gate of T6 is connected to the first output terminal VOUT1, and the source of T6 is grounded.

The drain of T7 in the second output circuit unit is connected to the positive bias line, the gate of T7 is connected to the drain of T6, the source of T7 is connected to the positive pole of the Schottky diode D5; the negative pole of D5 is connected to the Schottky diode D6 The positive pole of D6 is connected to the positive pole of Schottky diode D7, the negative pole of D7 is connected to the positive pole of Schottky diode D8; the negative pole of D8 is connected to the drain of enhanced high electron mobility transistor T8, and the gate and source of T8 connected to the negative bias line, and the drain of T8 connected to the second output terminal VOUT2.

The working principle of the second inverting circuit and the second output circuit in the present invention is:

The input of this module is the output VOUT1 of the first output circuit. Combining the above principles, it is known that for the output VOUT1 of the first output circuit, VIN is low level, then VOUT1 is high level and close to 0V, and VIN is high level level, VOUT1 is low and close to VSS.

If the input terminal VIN is at a high level, then VOUT1 is at a low level, and the depletion-type high-electron mobility transistor T6 is turned off, so the channel resistance of T6 is relatively large, but the upper gate voltage of the enhancement-type high-electron mobility transistor T5 is 0V , so the channel resistance of T6 is much larger than the channel resistance of T5, so the output of the first inverting circuit obtains close to VSS in the divided voltage of the channel. Because the gate voltage of the depletion-type high electron mobility transistor T7 is close to VSS, T7 is turned on, and the channel resistance of T7 is smaller than that of T8. Through process adjustment, the width-to-length ratio of T7 and the width-to-length ratio of the depletion-type high electron mobility transistor T8 are 5 to 8, and the four diodes of Schottky diodes D1, D2, D3, and D4 are stepped down, which can The output terminal VOUT2 of the second output circuit is adjusted to be about VDD and high level.

If the input terminal VIN is at a low voltage, then the VOUT1 terminal is at a high level, and T6 is turned on, and since the width-to-length ratio of T6 and T5 is 5 to 8, the channel resistance of T5 is several times that of T6, so The output of the first inverting circuit is close to 0V, so that T7 is turned off, so T7 has a larger channel resistance. Since T8 is an enhancement device and the gate voltage is 0, it also has a large channel resistance, but since the width-to-length ratio of T8 is 5 to 8 times that of T7, the channel resistance of T8 is smaller than that of T7. After the Schottky diodes D5 , D6 , D7 , and D8 drop the voltage, the output terminal VOUT2 of the second output circuit is at a low level.

The effect of the present invention will be further described below in conjunction with the simulation diagram of FIG. 2 .

With reference to Fig. 2, the output VOUT2 of the second inverting circuit of the present invention and the output VOUT2 of the second output circuit are respectively described as follows with the simulation graph of input voltage VIN response:

The input terminal VIN input range of the emulation of the present invention is that 0-5V is a direct current scan, and thinks that VIN is input low level when VIN＜0.4V, and VIN is input high level when VIN＞2.4V; VDD=5V, VSS= -5V; It is considered that when the output is >-2V, it is an output high level, and when the output is <-3V, it is an output low level.

The present invention is simulated under the above simulation conditions, and the simulation results are shown in FIG. 2 . In FIG. 2, the horizontal axis represents the input terminal voltage VIN, and the vertical axis represents the output terminal voltage. The dotted line in FIG. 2 represents the output VOUT1, and the solid line represents the output VOUT2.

When the input terminal voltage VIN is low level, the output of the second inverting circuit is low level, and is about 0V, and the output VOUT2 is low level, and is about -4V; when the input terminal voltage VIN is high level, The output of the second inverting circuit is at a high level and is about 0V, and the output VOUT2 is at a high level and is about 0V. Therefore, when VIN changes between low level and high level, both VOUT1 and VOUT2 can change the level between high level and low level. Therefore, the present invention can realize the function of level conversion.

Claims (8)

1. a gallium nitrate based enhancing depletion type level shifting circuit, comprises the first negative circuit, the first output circuit, the second negative circuit, the second output circuit; The output of the first described negative circuit connects with the input of the first output circuit, and the output of the first output circuit connects with the input of the second negative circuit, and the output of the second negative circuit connects with the input of the second output circuit; Wherein:

The drain electrode of the depletion high electron mobility transistors T1 in the first described negative circuit connects positive bias line, after the source electrode of T1 and its grid short circuit, be connected with the grid of the drain electrode of enhancement type high electron mobility transistor T2 with the enhancement type high electron mobility transistor T3 in the first output circuit respectively; The grid of T2 connects the source ground line of input VIN, T2;

The drain electrode of the T3 in the first described output circuit connects positive bias line, and the grid of T3 connects the drain electrode of T2, and the source electrode of T3 connects the positive pole of Schottky diode D1; The negative pole of D1 connects the positive pole of Schottky diode D2, and the negative pole of D2 connects the positive pole of Schottky diode D3, and the negative pole of D3 connects the positive pole of Schottky diode D4; The negative pole of D4 connects the drain electrode of depletion high electron mobility transistors T4, and the grid of T4 and source electrode connect negative bias line, and the drain electrode of T4 meets grid and the first output VOUT1 of depletion high electron mobility transistors T6;

The drain electrode of the enhancement type high electron mobility transistor T5 in the second described negative circuit connects positive bias line, after the source electrode of T5 and its grid short circuit, connects respectively with the grid of depletion high electron mobility transistors T7 in the drain electrode of T6 and the second output circuit; The grid of T6 meets the first output VOUT1, the source ground line of T6;

The drain electrode of the T7 in the second described output circuit connects positive bias line, and the grid of T7 connects the drain electrode of T6, and the source electrode of T7 connects the positive pole of Schottky diode D5; The negative pole of D5 connects the positive pole of Schottky diode D6, and the negative pole of D6 connects the positive pole of Schottky diode D7, and the negative pole of D7 connects the positive pole of Schottky diode D8; The negative pole of D8 connects the drain electrode of enhancement type high electron mobility transistor T8, and the grid of T8 and source electrode connect negative bias line, and the drain electrode of T8 meets the second output VOUT2.

2. gallium nitrate based enhancing depletion type level shifting circuit according to claim 1, it is characterized in that, the breadth length ratio of described enhancement type high electron mobility transistor T2, T3, T5, T8 is identical.

3. gallium nitrate based enhancing depletion type level shifting circuit according to claim 1, is characterized in that, described enhancement type high electron mobility transistor T2, T3, T5, T8 threshold voltage is greater than zero.

4. gallium nitrate based enhancing depletion type level shifting circuit according to claim 1, it is characterized in that, the breadth length ratio of described depletion high electron mobility transistors T1, T4, T6, T7 is identical.

5. gallium nitrate based enhancing depletion type level shifting circuit according to claim 1, it is characterized in that, the threshold voltage of described depletion high electron mobility transistors T1, T4, T6, T7 is less than zero.

6. gallium nitrate based enhancing depletion type level shifting circuit according to claim 1, it is characterized in that, the physical size of described Schottky diode D1, D2, D3, D4, D5, D6, D7, D8 is identical.

7. gallium nitrate based enhancing depletion type level shifting circuit according to claim 1, is characterized in that, described enhancement type high electron mobility transistor breadth length ratio is 5 ~ 8 times of depletion high electron mobility transistors breadth length ratio.

8. gallium nitrate based enhancing depletion type level shifting circuit according to claim 1, is characterized in that, voltage added on described positive bias line is equal with voltage value added on negative bias line, and symbol is contrary.