CN103107139A - Structure of field effect transistor with fin structure and manufacturing method thereof - Google Patents

Abstract

The invention discloses a structure of a field effect transistor with a fin-shaped structure and a manufacturing method thereof. The manufacturing method comprises providing a substrate, forming an ion trap with a first dopant concentration in the substrate, forming at least one fin-shaped structure, arranging on the substrate, performing at least one first ion implantation process to form a first conductive anti-penetration ion implantation region on the substrate, wherein the anti-penetration ion implantation region has a third dopant concentration, and the third dopant concentration is greater than the first dopant concentration, forming at least one channel layer arranged along at least one surface of the fin-shaped structure after the first ion implantation process, forming a gate to cover part of the fin-shaped structure, and forming a source and a drain arranged in the fin-shaped structure at two sides of the gate.

Description

Structure of field effect transistor with fin structure and method of manufacturing the same

technical field

The invention relates to a structure and a manufacturing method of a field effect transistor, in particular to a structure and a manufacturing method of a field effect transistor with a fin structure.

Background technique

As the size of field effect transistors (FETs) continues to shrink, the development of existing planar field effect transistors is facing the limit of the manufacturing process. In order to overcome the manufacturing process limitation, replacing planar transistor devices with non-planar field effect transistor devices, such as fin field effect transistor (Fin FET) devices, has become a mainstream development trend at present. Since the three-dimensional structure of the fin field effect transistor element can increase the contact area between the gate and the fin structure, it can further increase the control of the gate on the carrier channel area, thereby reducing the source-induced damage to small-sized elements. Energy band lowering (drain induced barrierlowering, DIBL) effect, and can suppress the short channel effect (short channel effect, SCE). And because the FinFET device has a wider channel width under the same gate length, doubled drain driving current can be obtained. Even, the threshold voltage of the transistor device can be adjusted by adjusting the work function of the gate.

In the existing fin field effect transistor manufacturing process, after the fin structure is formed, an anti-punch ion implantation process is usually performed to prevent the source/drain from penetrating through the substrate. Effect (punch-through effect) generation. However, for the fin structure whose top surface is covered by the patterned mask layer, since the sidewall of the fin structure is not shielded, in the anti-through ion implantation process, dopants will not only be implanted in the source Under the /drain, it will also be implanted in the carrier channel region on the side of the fin structure, resulting in uncontrollable variation in the dopant concentration of the carrier channel region, which will affect the fin field effect transistor element The poor electrical performance greatly reduces the yield rate of the manufacturing process.

Contents of the invention

The object of the present invention is to provide a structure of a field effect transistor with a fin structure and a manufacturing method thereof, so as to avoid uncontrollable variation of the dopant concentration in the channel region.

In order to achieve the above object, according to an embodiment of the present invention, a method for manufacturing a field effect transistor with a fin structure is provided, including providing a substrate, forming an ion trap of a first conductivity type in the substrate, and the first conductivity type The type ion trap has a first dopant concentration, forms at least one fin structure, is arranged on the substrate, and performs at least one first ion implantation process to form an anti-penetration (anti-penetration) of the first conductivity type on the substrate. punch) ion implantation region, wherein the anti-penetration ion implantation region has a third dopant concentration, and the third dopant concentration is greater than the first dopant concentration, after the first ion implantation process, at least one channel layer is formed along the At least one surface of the fin structure is provided to form a gate, which covers part of the fin structure, and a source and a drain are formed in the fin structure on both sides of the gate.

According to another embodiment of the present invention, there is provided a structure of a field effect transistor having a fin structure, comprising a substrate and a first conductivity type ion trap disposed in the substrate, wherein the first conductivity type ion trap has a First dopant concentration, at least one fin-shaped structure, disposed on the substrate, at least one channel layer, disposed along at least one surface of the fin-shaped structure, wherein the channel layer has a second doping concentration, the second doping concentration The highest concentration is less than the first dopant concentration, and at least one anti-penetration ion implantation region of the first conductivity type is arranged between the substrate and the channel layer, wherein the anti-penetration ion implantation region has a third dopant concentration, and the third dopant The concentration is greater than the first dopant concentration, a gate, covering part of the fin structure, and a source and a drain, which are arranged in the fin structure on both sides of the gate, wherein the source and the drain have a first Two conductivity types.

Description of drawings

Fig. 1 is the preparation flowchart of the field effect transistor with fin structure;

2 to 12 are schematic diagrams illustrating a method for forming a field effect transistor with a fin structure according to a preferred embodiment of the present invention.

Description of main component symbols

Detailed ways

In order to enable those who are familiar with the technical field of the present invention to further understand the present invention, the preferred embodiments of the present invention are listed below, together with the accompanying drawings, to describe in detail the composition of the present invention and the desired effects .

FIG. 1 is a flow chart of manufacturing a field effect transistor with a fin structure according to different embodiments of the present invention. The manufacturing process is as follows: forming a fin structure 1a, forming an insulating layer 1b, implementing a planarization process 1c, implementing an etch-back process 1d, and removing a patterned hard mask 1e. In addition, the present invention further includes a first ion implantation process 2 for forming an anti-punch ion implantation region and a process for forming a channel layer 3 . It should be noted here that the technical feature of the present invention is that the time point of forming the channel layer 3 must be later than the time point of performing the first ion implantation 2 . For example, when the first ion implantation process is performed as shown in the first ion implantation processes 2a, 2b, 2c, 2d, 2e, and 2f, the channel layer is preferably formed when the channel layer 3b is formed. where shown. However, when the first ion implantation process is performed as shown in the first ion implantation processes 2a and 2b, the channel layer is preferably formed at the same time as the channel layer 3b. In order to make the above-mentioned preparation process easier to understand, the following is a detailed statement of different implementation aspects:

The first form of implementation:

Please refer to FIG. 1 to FIG. 8 , wherein FIG. 2 to FIG. 8 are schematic views of forming a fin structure according to a preferred embodiment of the present invention. In the first embodiment, the first ion implantation process 2 is performed before the fin structure 1 a is formed. As shown in FIG. 2 , firstly, a semiconductor substrate 10 covered with a patterned photoresist layer 18 is provided, wherein the patterned photoresist layer 18 is used to define the ion trap 9 and the penetration-resistant ion implantation region 21 The location, that is, the manufacturing process of the ion trap 9 and the anti-through ion implantation region 21 can share the same photomask manufacturing process. However, according to other embodiments, the ion trap 9 and the penetration-resistant ion implantation region 21 can also be fabricated through different photomasks. Next, an ion trap 9 of a first conductivity type (such as P-type) is formed in the semiconductor substrate 10, and the ion trap 9 has a first concentration of 10 ¹² -10 ¹³ atoms/cm 2 (atoms/cm ² ). Dopant concentration. In addition, there may be an ion trap (not shown) of a second conductivity type (for example, N-type) in the semiconductor substrate 10, so that the above-mentioned ion traps respectively correspond to N-type metal oxide semiconductor transistor (NMOS) regions (not shown in the figure). shown) and a P-type metal oxide semiconductor transistor (PMOS) region (not shown). The semiconductor substrate 10 may comprise a silicon (bulk silicon) substrate or a silicon-on-insulator (SOI) substrate, wherein a silicon-on-insulator (SOI) substrate can provide better Heat dissipation and grounding effect, and help to reduce cost and suppress noise.

Next, under the coverage of the patterned photoresist layer 18, a first ion implantation process 2 is performed to form at least one anti-penetration ion implantation region 21 of the first conductivity type in the ion trap 9, Wherein the anti-penetration ion implantation region 21 has a third dopant concentration, and the third dopant concentration is higher than the first dopant concentration of the ion trap 9 . It should be noted here that the first ion implantation process may include multiple ion implantation processes. In addition, according to this embodiment, an oxide layer 16 is further included on the surface of the semiconductor substrate 10 to prevent high-energy ions from directly impacting the surface of the semiconductor substrate 10 to cause defects.

Next, as shown in FIG. 3 , the patterned photoresist layer 18 and the oxide layer 16 are removed to expose the surface of the semiconductor substrate 10 . Then selectively perform an epitaxial growth (epitaxial growth) manufacturing process to form a semiconductor layer 23 on the surface of the semiconductor substrate 10, which may include silicon, silicon carbide, germanium silicide or III-V group compounds in the periodic table, But not limited to this. In addition, according to the requirements of different manufacturing processes, the semiconductor layer 23 with appropriate stress (extension or compression) or doping concentration can also be formed to adjust the electrical performance of the carrier channel layer.

Next, as shown in FIG. 4 , a second patterned mask layer 29 comprising at least one patterned stress buffer layer 25 and at least one patterned hard mask layer 27 is formed on the semiconductor layer 23 to define each The location of the fin structure 11. The patterned stress buffer layer 25 includes silicon oxide, and the patterned hard mask layer 27 includes silicon nitride. Next, an etching process is performed to form at least one fin structure 11 on the semiconductor substrate 10 , and the fin structures 11 are isolated by shallow trenches 13 . At this time, the top surface 12 of the patterned semiconductor layer 23a is provided with a second patterned mask layer 29, and there is an anti-penetration ion implantation region 21 under the patterned semiconductor layer 23a, wherein the anti-penetration ion implantation region 21 and the top surface The distance between faces 12 is preferably less than 400 Angstroms.

Next, as shown in FIG. 5 , an insulating layer 31 , such as a silicon dioxide layer, is formed on the semiconductor substrate 10 . The insulating layer 31 covers each fin structure 11 and fills each shallow trench 13 . The above manufacturing process for forming the insulating layer 31 may include high density plasma chemical vapor deposition (high density plasmaCVD, HDPCVD), sub atmospheric pressure chemical vapor deposition (sub atmosphere CVD, SACVD) or spin on dielectric material (spin on dielectric, SOD) and other production processes. Afterwards, as shown in FIG. 6 , an etch-back process 1 d is performed on the insulating layer 31 to remove part of the insulating layer 31 until the top surface of the insulating layer 31 is lower than the top surface 12 of the fin structure 11 . In addition, a planarization process 1 c may be optionally performed before the etch back, so that the insulating layer 31 is equal to or slightly lower than the second patterned mask layer 29 . Therefore, at least one shallow trench isolation structure 33 is formed on the semiconductor substrate 10 between the fin structures 11 .

As shown in FIG. 7 , an etching process is performed to remove the second patterned mask layer 29 . In an embodiment of the present invention, when the second patterned mask layer 29 includes silicon nitride, it can be removed by hot phosphoric acid, which is a prior art, and will not be repeated here. Next, a channel layer 35 is respectively formed to cover the surface of each fin structure 11 by using an epitaxial manufacturing process. According to different manufacturing process requirements, a second ion implantation process can be selectively performed on the channel layer 35, which can include tilted-angle ion implantation and other manufacturing processes to control the doping of the channel layer 35. impurity concentration, thereby adjusting the threshold voltage (threshold voltage, V _th ) of the transistor. The aforementioned channel layer 35 includes silicon, germanium silicide or other semiconductor materials that can serve as carrier channels. It should be noted here that, according to other embodiments of the present invention, the channel layer 35 may also be directly disposed inside the surface of the fin structure 11 (not shown), that is, the channel layer 35 does not cover on the surface of the fin structure 11.

After that, as shown in FIG. 8 , at least one dielectric layer 37 and a gate material layer 39 covering each fin structure 11 are sequentially formed on the semiconductor substrate 10 . According to different manufacturing process requirements, the above-mentioned dielectric layer 37 may include dielectric materials such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON) or other high dielectric constant materials. The gate material layer 39 may include polysilicon material, metal silicide, or metal.

It should be noted here that the aforementioned channel layer 35 is formed after the insulating layer 31 fills the shallow trench 13 . However, in another embodiment, the channel layer 3 is formed after the fin structure 1a is formed. According to this embodiment, at least one channel layer 35 can be formed on the surface of the fin structure 11 after each fin structure 11 is formed and before the insulating layer 31 fills the shallow trench 13 through an epitaxial growth process, At this time, since the top surface 12 of the fin structure 11 is covered by the second patterned mask layer 29 , the channel layer 35 is only formed on the sidewall of the fin structure 11 (not shown). In addition, according to different manufacturing process requirements, a second ion implantation process can be selectively performed on the channel layer 35 to regulate the doping concentration of the channel layer 35 .

The second form of implementation:

Please refer to FIG. 1, FIG. 3 to FIG. 8, the implementation of the second embodiment is similar to the first embodiment, the only difference is: in the second embodiment, after forming the fin structure 1a and forming the insulating The first ion implantation process 2 is performed before layer 1b. Similar to that shown in FIG. 3 , a semiconductor substrate 10 is provided, and the surface of the semiconductor is optionally covered with a semiconductor layer 23 , and the semiconductor substrate 10 still has no penetration-resistant ion implantation region at this time. Next, as shown in FIG. 4 , a second patterned mask layer 29 is formed on the semiconductor layer 23 to define the positions of the fin structures 11 . An etching process is performed to form at least one fin structure 11 on the substrate 10 , and the fin structures 11 are isolated by shallow trenches 13 . At this time, the top surface 12 of the patterned semiconductor layer 23 a is provided with a patterned mask layer 29 . Next, a first ion implantation process 2 is performed to form an anti-penetration ion implantation region 21 under the patterned semiconductor layer 23a. According to another embodiment of the present invention, if the semiconductor substrate 10 is not covered with the semiconductor layer 23 before forming each fin structure 11 , then the anti-penetration ion implantation region 21 will exist in the fin structure 11 at this time. Next, similar to the first embodiment, an insulating layer 31 is formed, a planarization process 1c is performed, an etching-back process 1d is performed, the second patterned mask layer 29 is removed, and the epitaxial channel layer 35 is grown. The manufacturing process and the subsequent manufacturing process correspond to FIG. 5 to FIG. 8 of the first embodiment, and will not be repeated here. In addition, similar to the first embodiment, the timing of epitaxially growing the channel layer 35 can be advanced to the timing after the first ion implantation process 2 is performed and before the insulating layer 1b is formed.

It should be noted here that in the second embodiment, since the first ion implantation process is performed after the formation of the fin structure 11, in order to avoid the dopant concentration of the carrier channel being affected by the first ion implantation process As a result, the channel layer 35 is preferably additionally covered on the surface of the fin structure 11 by means of an epitaxial manufacturing process, rather than disposed inside the surface of the fin structure 11 by means of ion implantation (not shown in the figure). In addition, according to different manufacturing process requirements, a second ion implantation process can be selectively performed on the channel layer 35 to regulate the doping concentration of the channel layer 35 .

The third implementation mode:

Please refer to FIG. 1, FIG. 3 to FIG. 8, the third embodiment is similar to the second embodiment, the difference is: in the third embodiment, after the formation of the insulating layer 1b and before the planarization process 1c The first ion implantation manufacturing process 2 is performed. Similar to FIGS. 3 to 4 , at least one fin structure 11 is formed on the semiconductor substrate 10 , and there is no anti-penetration ion implantation region 21 in the semiconductor substrate 10 at this time. Next, as shown in FIG. 5 , an insulating layer 31 , such as a silicon dioxide layer, is formed on the substrate 10 . The insulating layer 31 covers the fin structure 11 and fills up the shallow trench 13 . Next, a first ion implantation process 2 is performed to form an anti-penetration ion implantation region 21 under the patterned semiconductor layer 23a. According to another embodiment of the present invention, if the semiconductor substrate 10 is not covered with the semiconductor layer 23 before forming the fin structure 11 , the anti-penetration ion implantation region 21 will exist in the fin structure 11 at this time. Next, similar to the second embodiment, a planarization process 1c is performed, an etching process 1d is performed, the second patterned mask layer 29 is removed, and the channel layer 35 is epitaxially grown. These processes and subsequent processes Corresponding to FIG. 6 to FIG. 8 of the second embodiment, details are not repeated here.

It should be noted that, similar to the second embodiment, since the first ion implantation process 2 is performed after the formation of the fin structure 11, in order to avoid the dopant concentration of the carrier channel being affected by the first ion implantation process The channel layer 35 is preferably additionally covered on the surface of the fin structure 11 by epitaxial manufacturing process, instead of being disposed inside the surface of the fin structure 11 by ion implantation (not shown in the figure). In addition, according to different manufacturing process requirements, a second ion implantation process can be selectively performed on the channel layer 35 to regulate the doping concentration of the channel layer 35 .

The fourth implementation mode:

Please refer to Figure 1, Figure 3 to Figure 8, the implementation of the fourth embodiment is similar to the second embodiment, the difference is: in the fourth embodiment, after the planarization process 1c and after The first ion implantation process 2 is performed before the etch-back process 1d. 3 to 5, at least one fin structure 11 is formed on the semiconductor substrate 10, and an insulating layer 31 is formed on the semiconductor substrate 10, the insulating layer 31 covers the fin structure 11 and fills the shallow trench 13. It should be noted here that there is no penetration-resistant ion-implantation region in the fin structure 11 at this time.

After that, as shown in FIG. 6 , after the planarization process, a first ion implantation process 2 is performed to form an anti-penetration ion implantation region 21 under the patterned semiconductor layer 23 a. According to another embodiment of the present invention, if the semiconductor substrate 10 is not covered with the semiconductor layer 23 before forming the fin structures 11 , the anti-penetration ion implantation region 21 will exist in the fin structures 11 at this time. In addition, in the above-mentioned embodiment, the distance between the anti-penetration ion implantation region 21 and the top surface 12 is preferably less than 400 angstroms. Afterwards, another etching process 1d is performed to remove the second patterned mask layer 29 and the epitaxially grown channel layer 35. These processes and the subsequent processes correspond to FIGS. 6 to 8 of the second embodiment. , will not be described here.

Similarly, in the fourth embodiment, since the first ion implantation process 2 is performed after the formation of the fin structure 11, in order to avoid the influence of the dopant concentration of the carrier channel by the first ion implantation process, the channel The layer 35 is preferably additionally covered on the surface of the fin structure 11 by means of epitaxial manufacturing process, instead of being disposed inside the surface of the fin structure 11 by means of ion implantation (not shown in the figure). In addition, according to different manufacturing process requirements, a second ion implantation process can be selectively performed on the channel layer 35 to regulate the doping concentration of the channel layer 35 .

The fifth embodiment:

Please refer to FIG. 1, FIG. 3 to FIG. 8, the fifth embodiment is similar to the second embodiment, the difference is: in the fifth embodiment, after the etch-back manufacturing process and the removal of the second patterned mask The first ion implantation process is performed before the mold layer 29 . 3 to 6, at least one fin structure 11 is formed on the semiconductor substrate 10, and an insulating layer 31 is formed on the substrate 10, the insulating layer 31 covers the fin structure 11 and fills the shallow trench 13 . Next, an etch-back process 1 d is performed on the insulating layer 31 to remove part of the insulating layer 31 until the top surface of the insulating layer 31 is lower than the top surface 12 of the fin structure 11 . In addition, a planarization process 1 c may be optionally performed before the etch-back process 1 d, so that the insulating layer 31 is equal to or slightly lower than the second patterned mask layer 29 . It should be noted here that there is no penetration-resistant ion-implantation region in the fin structure 11 at this time.

Next, still similar to that shown in FIG. 6 , a first ion implantation process 2 is performed to form an anti-penetration ion implantation region 21 under the patterned semiconductor layer 23 a. According to another embodiment of the present invention, if the semiconductor substrate 10 is not covered with the semiconductor layer 23 before forming the fin structure 11 , the anti-penetration ion implantation region 21 will exist in the fin structure 11 at this time. Afterwards, the second patterned mask layer 29 is removed and the channel layer 35 is epitaxially grown.

Similarly, in the fifth embodiment, since the first ion implantation process 2 is performed after the formation of the fin structure 11, in order to avoid the influence of the dopant concentration of the carrier channel by the first ion implantation process, the channel The layer 35 preferably additionally covers the surface of the fin structure 11 by epitaxial manufacturing process, and is not disposed inside the surface of the fin structure 11 by ion implantation (not shown in the figure). In addition, according to different manufacturing process requirements, a second ion implantation process can be selectively performed on the channel layer 35 to regulate the doping concentration of the channel layer 35 .

The sixth form of implementation:

Please refer to Fig. 1, Fig. 3 to Fig. 8, the sixth embodiment is similar to the second embodiment, the difference is that in the sixth embodiment, the second patterned mask layer 29 is removed and the first patterned mask layer 29 is removed. An ion implantation manufacturing process. 3 to 6, at least one fin structure 11 is formed on the semiconductor substrate 10, and an insulating layer 31, such as a silicon dioxide layer, is formed on the substrate 10. The insulating layer 31 covers the fin structure 11 and The shallow trenches 13 are filled. Next, a planarization process and an etch-back process are performed on the insulating layer 31 to remove part of the insulating layer 31 until the top surface of the insulating layer 31 is lower than the top surface 12 of the fin structure 11 . It should be noted here that there is no penetration-resistant ion-implantation region in the fin structure 11 at this time.

Similar to that shown in FIG. 7 , an etching process is performed to remove the second patterned mask layer 29 . Next, a first ion implantation process is performed to form an anti-penetration ion implantation region 21 under the patterned semiconductor layer 23a. Next, a channel layer 35 is formed to cover the surface of the fin structure 11 by using an epitaxial manufacturing process. According to different manufacturing process requirements, an ion implantation process can be selectively performed on the channel layer 35 to control the doping concentration of the channel layer 35 .

It should be noted here that, in the sixth embodiment, since the first ion implantation process 2 is performed after the formation of the fin structure 1a, in order to prevent the dopant concentration of the carrier channel from being affected by the anti-penetration process Preferably, the channel layer 35 additionally covers the surface of the fin structure 11 by means of epitaxial manufacturing process, instead of being disposed inside the surface of the fin structure 11 by means of ion implantation (not shown in the figure). In addition, according to different manufacturing process requirements, a second ion implantation process can be selectively performed on the channel layer 35 to regulate the doping concentration of the channel layer 35 .

In addition, according to the above-mentioned first embodiment to the sixth embodiment, the surface of the semiconductor substrate 10 has a semiconductor layer 23, and the semiconductor layer 23 can have an appropriate stress (extension or compression) or an appropriate doping concentration. It is used to adjust the electrical performance of the carrier channel layer. However, according to another preferred embodiment of the present invention, the semiconductor layer 23 does not exist on the surface of the semiconductor substrate 10, and the patterned semiconductor layer 23a in the fin structure 11 is replaced by a protruding portion 36, wherein the protruding portion 36 It is obtained by etching the semiconductor substrate 10 . Therefore, the channel layer 35 is disposed along the surface of the protruding portion 36 , and its structure can refer to FIG. 9 .

Seventh form of implementation:

Similar to the first embodiment, in this embodiment, the fin structure 11 is formed on the semiconductor substrate 10 by epitaxial growth. The manufacturing process steps are similar to those shown in FIG. 1 , FIG. 3 to FIG. 9 , and only the differences are described below. First, as shown in FIG. 10 , a semiconductor substrate 10 covered with a patterned mask layer 15 is provided to define the positions of subsequent fin structures 11 . There is an ion trap 9 of a first conductivity type (for example, P-type) in the semiconductor substrate 10, and the ion trap 9 has a first dopant concentration between 10 ¹² -10 ¹³ atoms/cm 2 (atoms/cm ² ). . In addition, there may be an ion trap (not shown) of a second conductivity type (for example, N-type) in the semiconductor substrate 10, so that the above-mentioned ion traps respectively correspond to N-type metal oxide semiconductor transistor (NMOS) regions (not shown in the figure). ) and a P-type metal oxide semiconductor transistor (PMOS) region (not shown). In addition, the above-mentioned patterned mask layer 15 includes a multi-layer structure, which includes at least one stress buffer layer 16, such as silicon oxide, and at least one hard mask layer 18, such as silicon nitride.

Next, as shown in FIG. 10 , the first ion implantation process 2 is performed to form a penetration-resistant ion implantation region 21 of the first conductivity type, and the dopant concentration of the penetration-resistant ion implantation region 21 is higher than that of the ion trap 9 the first dopant concentration. In addition, before a first ion implantation process 2 is performed, an oxide layer (not shown) may be formed on the surface of the semiconductor substrate 10 to prevent high-energy ions from directly impacting the surface of the substrate 10 to cause defects. In this embodiment, the anti-penetration ion implantation region 21 is defined by the patterned mask layer 15, however, according to other preferred embodiments, the anti-penetration ion implantation region 21 can share the same photomask as the ion trap 9, That is, the patterned mask layer 15 is not used to define the anti-penetrating ion implantation region 21 .

Next, as shown in FIG. 11 , a selective epitaxial growth process is performed, using the surface of the substrate 10 exposed to the patterned mask layer 15 as a seed layer to form fin structures 11 in the trenches 32 . Each fin structure 11 grows from the surface of the semiconductor substrate 10 at the bottom of the trench 32 , and grows upward to protrude from the top surface of the patterned mask layer 15 . According to the requirements of the manufacturing process, after the selective epitaxial growth is completed, another cyclic thermal annealing (CTA) process can be performed to reduce defects in the fin structure 11 . The above-mentioned fin structure 11 may include a silicon layer (Si), a silicon germanium layer (SiGe), or a combination thereof. It should be noted here that since in this embodiment, the top surface 12 of the fin structure 11 is not covered with a mask layer (not shown in the figure), therefore no manufacturing process of removing the mask layer is required. In addition, according to other preferred embodiments, if the anti-penetration ion implantation region 21 and the ion trap 9 share the same photomask, an additional patterned mask layer (not shown) needs to be formed to define the fin structure 11 formation areas. Subsequent manufacturing processes are similar to those shown in the corresponding FIG. 4 to FIG. 8 , and will not be repeated here.

In addition, this embodiment can also be applied to the corresponding second to fifth embodiments, that is, after the fin structure 11 is epitaxially grown on the semiconductor substrate 10, the first ion implantation process 2 is performed. The time points may be respectively: after forming the fin structure 1a, after forming the insulating layer 1b, after the planarization process 1c, or after the etch-back process 1d. For the sake of brevity, these similar manufacturing processes may correspond to FIG. 4 to FIG. 9 , and will not be repeated here.

After completing the above first to seventh embodiments, various required semiconductor manufacturing processes, such as MOS manufacturing processes with polysilicon gates or metal gates, can be followed. As shown in FIG. 12 , according to an embodiment of the present invention, it is a schematic structural diagram of a multi-gate field effect transistor integrated in a gate-first manufacturing process. Firstly, a patterned capping layer 46 is formed on the gate material layer 39 with metal components to define positions of gates in at least one NMOS region (not shown) and at least one PMOS region (not shown). Subsequently, using the patterned cover layer 46 as an etching mask to etch the gate material layer 39 and the dielectric layer 37 with a high dielectric constant to form at least one gate covering part of each fin structure 11 on the semiconductor substrate 10. pole structure28. Next, a lightly doped source/drain region (not shown) is selectively formed in the fin structure 11 not covered by the gate. Then, a spacer 47 is formed on the surrounding sidewall of the gate structure 28 . The spacer 47 can be a single-layer or multi-layer structure, or can be composed of a liner and the like. After that, using the spacer wall 47 and the capping layer 46 as a mask, an ion implantation process is performed to dope appropriate dopants. Wherein, the dopant may include N-type or P-type dopant, so as to respectively implant corresponding electrical source/drain on the fin structure 11 exposed on both sides of the gate structure 28 in the NMOS region and the PMOS region. dopant, and cooperate with an annealing process to activate and form source/drain regions (not shown). Although this embodiment preferably sequentially forms lightly doped source/drain regions, spacers 27 and source/drain regions, it is not limited to this, and the present invention can adjust the above-mentioned The sequence of forming the spacer and the doped region is within the scope of the present invention.

According to another embodiment of the present invention, still similar to that shown in FIG. 12 , it is a method for fabricating a gate last multi-gate field effect transistor with a metal gate. When the aforementioned gate material layer 39 shown in FIG. 8 is polysilicon, the post-gate manufacturing process is to undertake the above-mentioned gate first manufacturing process of the polysilicon gate. After replacing the polysilicon gate of the gate structure 28 with a metal gate, at least one high-permittivity gate dielectric layer (not shown) is sequentially covered above the channel region (not shown) of the fin structure 11 , at least one work function metal layer (not shown), and at least one metal conductive layer (not shown). Regardless of the gate-last fabrication process or the gate-first fabrication process, the material of the high-k gate dielectric layer can be selected from, for example, hafnium oxide (HfO ₂ ), hafnium oxide silicate ( hafnium silicon oxide, HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), aluminum oxide (aluminum oxide, Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (tantalum oxide , Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide , ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _{1 -x} O ₃ , PZT) and barium strontium titanate (barium strontium titanate, Ba _x Sr _1-x TiO ₃ , BST), but not limited thereto. The above-mentioned metal conductive layer comprises a low resistance material or a combination thereof. In addition, between the work function metal layer and the high dielectric constant gate dielectric layer and between the work function metal layer and the metal conductive layer, a layer containing titanium (Ti) and titanium nitride (TiN) can also be selectively formed, respectively. , tantalum (Ta), tantalum nitride (TaN) and other materials (barrier layer) (not shown).

Through the above-mentioned gate-first manufacturing process or gate post-manufacturing process, a multi-gate MOSFET with a fin structure has been completed. It should be noted here that, in the above-mentioned embodiment, there are three direct contact surfaces between the fin structure 11 and the dielectric layer 23, such as two contact side surfaces (not shown) and a contact top surface (not shown). , so it can be called a tri-gate field effect transistor (tri-gate MOSFET). Compared with the planar field effect transistor, the tri-gate field effect transistor acts as a carrier flow channel through the above three direct contact surfaces, so it has a wider carrier channel width under the same gate length, so that in Double the drain drive current can be obtained under the same drive voltage. However, the above-mentioned multi-gate field effect transistor is not limited to a tri-gate field effect transistor. According to the requirements of the manufacturing process, there may also be a patterned hard layer between the top surface 12 of the fin structure 11 and the dielectric layer 23 . The mask layer 15 , that is, only the side surfaces 34 on both sides of the fin structure 11 have direct contact with the dielectric layer 23 . Therefore, the multi-gate field effect transistor with two direct contact surfaces constitutes a fin field effect transistor (Fin FET).

To sum up the above, the present invention provides a method for manufacturing a field effect transistor with a fin structure, wherein the timing of performing the first ion implantation manufacturing process 2 is prior to the formation of the channel layer 3, that is, the anti-dopant that penetrates the ion implantation region The distribution of the dopant concentration in the channel layer 35 is not affected, so the variation of the electrical property of the FinFET element can be reduced.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (20)

1. A method for manufacturing a field-effect transistor with a fin structure, comprising: provide a base; forming an ion trap of a first conductivity type in the substrate, and the ion trap has a first dopant concentration; forming at least one fin structure disposed on the base; performing at least one first ion implantation process to form an anti-punch ion implantation region of the first conductivity type on the substrate, wherein the anti-punch ion implantation region has a third dopant concentration, and the a third dopant concentration greater than the first dopant concentration; After the first ion implantation process, at least one channel layer is formed along at least one surface of the fin structure; forming a gate covering a portion of the fin structure; and A source and a drain are formed in the fin structure on both sides of the gate. 2. The manufacturing method of a field effect transistor having a fin structure as claimed in claim 1, wherein the step of forming the fin structure comprises: forming a semiconductor layer on the substrate; and The semiconductor layer is etched to form the fin structure. 3. The manufacturing method of a field effect transistor having a fin structure as claimed in claim 1, wherein the step of forming the fin structure comprises: forming a patterned hard mask layer on the substrate; and A semiconductor layer is grown on the substrate exposed from the patterned hard mask layer to form the fin structure. 4. The method for manufacturing a field effect transistor with a fin structure as claimed in claim 1, wherein after forming the fin structure, further comprising: forming an insulating layer covering the fin structure; performing a grinding process on the insulating layer; and A back etching process is performed on the insulating layer. 5. The method for manufacturing a field effect transistor with a fin structure as claimed in claim 4, wherein after performing the etch-back manufacturing process, further comprising: The patterned hard mask layer is removed. 6. The method for manufacturing a field effect transistor with a fin structure as claimed in claim 1, wherein the first ion implantation process is performed before forming the fin structure. 7. The method for manufacturing a field effect transistor with a fin structure as claimed in claim 4, wherein the first ion implantation process is performed between forming the insulating layer and performing the polishing process. 8 . The method for manufacturing a field effect transistor with a fin structure as claimed in claim 4 , wherein the first ion implantation process is performed between the grinding process and the etch-back process. 9. The method for manufacturing a field effect transistor with a fin structure as claimed in claim 5, wherein the time point for performing the first ion implantation process is after performing the etch-back process and removing the hard mask layer between. 10 . The method for manufacturing a field effect transistor with a fin structure as claimed in claim 5 , wherein the first ion implantation process is performed between removing the hard mask layer and forming the channel region. 11 . 11. The manufacturing method of a field effect transistor having a fin structure as claimed in claim 1, wherein the first ion implantation manufacturing process comprises a multi-channel ion implantation manufacturing process. 12 . The method for manufacturing a field effect transistor with a fin structure as claimed in claim 1 , wherein the channel layer covers the surface of the fin structure in a conformal manner. 13 . 13. The method of manufacturing a field effect transistor with a fin structure as claimed in claim 1, wherein the channel layer is disposed inside the surface of the fin structure. 14. The method for manufacturing a field effect transistor with a fin structure as claimed in claim 1, wherein the channel layer is selected from a silicon layer, a germanium silicide layer, a silicon carbide layer or a combination thereof. 15. The method for manufacturing a field effect transistor with a fin structure as claimed in claim 1, wherein after forming the channel layer, further comprising: A second ion implantation process is performed to regulate the dopant concentration of the channel layer. 16. The method for manufacturing a field effect transistor with a fin structure as claimed in claim 15, wherein the second ion implantation process comprises a tilted-angle ion implantation process. 17. A structure of a field effect transistor having a fin structure, comprising: base; a first conductivity type ion trap disposed in the substrate, wherein the first conductivity type ion trap has a first dopant concentration; at least one fin structure disposed on the base; At least one channel layer is disposed along at least one surface of the fin structure, wherein the channel layer has a second doping concentration, and the highest concentration of the second doping concentration is lower than the first dopant concentration; At least one anti-penetration ion implantation region of the first conductivity type is disposed between the substrate and the channel layer, wherein the anti-penetration ion implantation region has a third dopant concentration, and the third dopant concentration is greater than the first dopant concentration; a gate covering a portion of the fin structure; and A source and a drain are arranged in the fin structure on both sides of the gate, wherein the source and the drain have a second conductivity type. 18. The field effect transistor structure with a fin structure as claimed in claim 17, wherein the substrate comprises an insulating layer adjacent to the fin structure. 19. The field effect transistor structure having a fin structure as claimed in claim 17, wherein the distance between the top surface of the fin structure and the penetration resistant ion implantation region is less than 400 angstroms. 20. The field effect transistor structure with a fin structure as claimed in claim 17, wherein the highest concentration of the second doping concentration is less than 10 ¹² atoms/cm ² .

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