CN103026516B - Light emitting diode - Google Patents

Abstract

Exemplary embodiments of the present invention relate to a light emitting diode including a plurality of light emitting cells on a substrate and adapted for AC driving. The light emitting diode includes a substrate and a plurality of light emitting cells formed on the substrate. Each of the light emitting cells includes a first region at a boundary of the light emitting cell and a second region opposite to the first region. The first electrode pad is formed in a first region of the light emitting cell. The second electrode pad having a linear shape is disposed to face the first electrode pad while defining a peripheral region together with a boundary of the second region. The wiring connects the first electrode pad to the second electrode pad between two adjacent light emitting cells.

Description

led

technical field

Exemplary embodiments of the present invention relate to light emitting diodes including compound semiconductors and light emitting diodes adapted for AC operation.

Background technique

Light emitting diodes (LEDs) can be made of compound semiconductors, including, for example, Group III nitride-based compound semiconductors. Light emitting diodes have been used in a wide range of applications including display devices and backlight units, and have also been used as modern A light source used for general lighting that is an alternative to incandescent and fluorescent bulbs.

Generally, LEDs are repeatedly turned on/off according to the direction of current applied by an AC power source. Therefore, when the LED is directly connected to an AC power source, the LED does not emit light continuously and may be damaged by reverse current. In order to solve this problem of LEDs, International Publication No. WO2004/023568 (A1) entitled "Light-emitting device having light-emitting elements" submitted by Sakai et al. voltage AC power LED.

FIG. 1 shows a conventional AC light emitting diode 1 . Referring to FIG. 1 , an AC light emitting diode 1 includes a plurality of rectangular light emitting units 4 formed on an insulating substrate 2 . Furthermore, bonding pads 3 a , 3 b are formed on the substrate 2 .

A conventional light emitting diode 1 includes an n-type electrode pad 6 and a p-type electrode pad 8 on each light emitting unit 4 . The light emitting unit 4 is partially removed to a predetermined depth to expose a portion of the intermediate layer in the light emitting unit 4 . The exposed layer is usually an n-type semiconductor layer, and the n-type electrode pad 6 is formed on the exposed area of the n-type semiconductor layer. A p-type electrode pad 8 is formed on the p-side region at the top of the light emitting unit 4 . The bonding pads 3 a , 3 b and the light emitting units 4 between the bonding pads 3 a , 3 b are connected in series with each other by wiring 5 . The p-type electrode pads 8 and n-type electrode pads 6 of adjacent light emitting units are connected to each other through wiring 5 .

In such a conventional light emitting diode 1, if the distance between the n-type electrode pad 6 and the p-type electrode pad 8 is large in the corresponding light-emitting unit 4, the current is mainly concentrated near the p-type electrode pad 8 , thereby emitting intense light near the p-type electrode pad 8 . In addition, when the p-type electrode pad 8 is located near the n-type electrode pad 6, the luminance is improved in the area between the p-type electrode pad 8 and the n-type electrode pad 6, but in the area between the p-type electrode pad 8 and the n-type electrode pad 6, the luminance is improved. In the region between the borders of the lighting units 4 there is a marked decrease in brightness. This leads to a significant deterioration of the uniformity of light emission of the light emitting diode, and becomes a major obstacle in the manufacture of large-sized light emitting diodes.

In other types of conventional light emitting diodes, the n-type electrode pad and the p-type electrode pad may be diagonally disposed at opposite corners of the light emitting unit to face each other. However, in these types of LEDs, only the vicinity of the p-type electrode pad has high brightness, resulting in uneven light emission.

Contents of the invention

technical problem

Exemplary embodiments of the present invention provide a light emitting diode having improved current spreading characteristics between electrode pads having different polarities of a light emitting unit to provide uniform light emission.

Additional features of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention.

Technical solutions

Exemplary embodiments of the present invention disclose a light emitting diode including a substrate, a plurality of light emitting units, a first electrode pad, a second electrode pad, and wiring. A plurality of light emitting units are arranged on the base. Each light emitting unit includes a first area at a boundary of the light emitting unit and a second area opposite to the first area. The first electrode pad is disposed at the first region. The second electrode pad has a linear shape and is disposed to face the first electrode pad. The second electrode pad defines a peripheral area together with a boundary of the second area. The wiring connects the first electrode pad of the first light emitting unit to the second electrode pad of the second light emitting unit.

Exemplary embodiments of the present invention disclose a light emitting diode including a light emitting unit, a first electrode pad and a second electrode pad. The first electrode pad is disposed at the first region. The second electrode pad has a linear shape and is disposed to face the first electrode pad. The second electrode pad defines a peripheral area together with a boundary of the second area.

Exemplary embodiments of the present invention disclose a light emitting diode including a substrate, a plurality of light emitting units, a wiring layer, an insulating layer, and a micro lens. The plurality of light emitting units are separated from each other on the substrate. Each light emitting unit includes a lower semiconductor layer, an active layer disposed on at least a portion of the lower semiconductor layer, an upper semiconductor layer, and a transparent electrode layer. The wiring layer electrically connects the lower semiconductor layer of the first light emitting unit to the upper semiconductor layer of the second light emitting unit adjacent to the first light emitting unit. An insulating layer is disposed between the wiring layer and the plurality of light emitting units to prevent a short circuit of the plurality of light emitting units due to the wiring layer. Microlenses are formed on the plurality of light emitting units.

Exemplary embodiments of the present invention disclose a light emitting diode including a substrate, a plurality of light emitting units, a wiring layer and an insulating layer. The plurality of light emitting units are separated from each other on the substrate. Each light emitting unit includes a lower semiconductor layer, an active layer disposed on at least a portion of the lower semiconductor layer, an upper semiconductor layer, and a transparent electrode layer. The wiring layer electrically connects the lower semiconductor layer of the first light emitting unit to the upper semiconductor layer of the second light emitting unit adjacent to the first light emitting unit. An insulating layer is disposed between the wiring layer and the plurality of light emitting units to prevent a short circuit of the plurality of light emitting units due to the wiring layer. Each light emitting unit includes a current shield under the wiring layer.

Beneficial effect

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

Description of drawings

The accompanying drawings illustrate exemplary embodiments of the invention and together with the description serve to explain principles of the invention, are included to provide a further understanding of the invention, and are incorporated in and constitute a document of this specification. part of the manual.

FIG. 1 is a plan view of a conventional light emitting diode including a plurality of light emitting units according to an exemplary embodiment of the present invention.

FIG. 2 is a plan view of a light emitting diode according to an exemplary embodiment of the present invention.

FIG. 3 is an enlarged plan view of a light emitting unit of the light emitting diode shown in FIG. 2 according to an exemplary embodiment of the present invention.

4, 5, 6, 7, 8, 9, and 10 are plan views of light emitting units according to exemplary embodiments of the present invention.

11A and 11B are photographs showing test results of light emitting uniformity of light emitting diodes according to an example of an exemplary embodiment of the present invention and a comparative example, respectively.

12 is a cross-sectional view taken along line I-I of the light emitting diode in FIG. 2 according to an exemplary embodiment of the present invention.

13 , 14 , 15 and 16 are cross-sectional views illustrating a method of manufacturing the light emitting diode of FIG. 12 according to an exemplary embodiment of the present invention.

FIG. 17 shows plan views of various microlenses according to exemplary embodiments of the present invention.

18 and 19 are photographs of various microlenses according to exemplary embodiments of the present invention.

detailed description

The present invention is described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure is thorough, and these exemplary embodiments will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements in the drawings. Descriptions contained herein and detailed descriptions of well-known functions may be omitted to avoid obscuring the subject matter of the present invention.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be Directly on said other element or layer, alternatively, intervening elements may also be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections do not shall be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

For ease of description, spatially relative terms such as "under", "beneath", "under", "above", "on" etc. may be used herein to describe an element as shown or The relationship of a feature to other components or features. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of "above" and "beneath". The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing exemplary embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that when the terms "comprising" and/or "comprising" are used in this specification, it means that the features, integers, steps, operations, elements and/or components exist, but does not exclude the existence or addition of one or more Various other features, integers, steps, operations, elements, components and/or groups thereof.

Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations in the shapes of the illustrations that result, for example, from manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in a certain degree of implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that, unless expressly defined herein, terms (e.g., terms defined in commonly used dictionaries) should be construed to have a meaning consistent with their meaning in the context of the relevant art, and not to be idealized or overly formal meaning to explain what they mean.

Hereinafter, exemplary embodiments of the present invention are described in detail with reference to the accompanying drawings.

FIG. 2 is a plan view of a light emitting diode 100 according to an exemplary embodiment of the present invention.

Referring to FIG. 2 , the light emitting diode 100 may include a substrate 20 and a plurality of light emitting units 40 . The light emitting diode may include a first electrode pad 60 (hereinafter referred to as "n-type electrode pad") and a second electrode pad 80 (hereinafter referred to as "p-type electrode pad") on each light emitting unit 40. ). The light emitting diode 100 may include a first bonding pad 32 and a second bonding pad 34 formed on the substrate 20 .

A plurality of light emitting units 40 may be formed on a single substrate 20 and connected to each other in series via wiring 53 to form an array. Each wire 52 may connect the n-type electrode pad 60 of one light emitting unit 40 to the p-type electrode pad 80 of another light emitting unit adjacent to the n-type electrode pad 60 . The first bonding pad 32 is connected in series to the p-type electrode pad 80 of the light-emitting unit at one end of the array via the wiring 54a, and the second bonding pad 34 is connected in series to the other light-emitting unit at the other end of the array via the wiring 54b. The n-type electrode pad 60 of the cell.

The wiring 52, the n-type electrode pad 60, and the p-type electrode pad 80 may be part of a wiring layer formed through a step cover process. That is, the wiring 52, the n-type electrode pad 60, and the p-type electrode pad 80 may be formed at the same time, and may be included in a single wiring layer in which the wiring layers are separated according to the positions and functions described above. The corresponding parts are divided into wiring 52 , n-type electrode pad 60 and p-type electrode pad 80 .

The array of light emitting cells 40 may be connected in antiparallel to each other between the bond pads 32, 34 to be driven by an AC power source.

In some cases, the wiring 52 may be formed by a step capping process including the following steps: forming an insulating layer to cover the substrate 20 and the light emitting unit 40; forming openings in the insulating layer to expose the electrode pads 60, 80; A linear conductive material layer is formed so that the conductive material layer connects electrode pads of adjacent light emitting units to each other.

The conductive material layer may basically function as the wiring 52 that may connect the light emitting cells to each other. The layer of conductive material may be made of any suitable conductive material.

The substrate 20 may be an insulating substrate that can electrically insulate the light emitting units 40 from each other. A sapphire substrate may be used as a growth substrate for growing a nitride semiconductor layer for the light emitting unit 40 . Each light emitting unit 40 may be configured to have the same area or different areas. Each light emitting unit 40 may include an n-type semiconductor layer, an active layer, and a p-type semiconductor layer sequentially formed on the substrate 20 . Each light emitting unit 40 may further include a transparent electrode layer, for example, an indium tin oxide (ITO) layer on the p-type semiconductor layer. However, an n-type semiconductor layer may be formed at an upper portion of the light-emitting unit 40 and a p-type semiconductor layer may be formed at a lower portion with respect to the active layer of the light-emitting unit 40 .

FIG. 3 is an enlarged plan view of the light emitting unit 40 of the light emitting diode shown in FIG. 2 . Referring to FIG. 3 , the light emitting unit 40 may include a substantially square border, and an n-type electrode pad 60 may be formed along the border of the light emitting unit 40 at one corner. The n-type electrode pad 60 may include two linear portions 62, 64 parallel to the two sides S1, S2 of the one corner of the light emitting unit 40, and at the one corner Near the vertices V1 of , intersect each other at right angles (ie, 90 degrees). The one corner of the light emitting unit 40 may correspond to a region of the light emitting unit on which the p-type semiconductor layer and the active layer are removed to expose the n-type semiconductor layer.

The p-type electrode pad 80 may be formed such that the central area of the p-type electrode pad 80 has a certain distance from the opposite corner portion opposite to the one corner portion of the light emitting unit 40, and the two corners of the p-type electrode pad 80 The end portion may be adjacent to a boundary of the light emitting unit 40 . The p-type electrode pad 80 may surround the peripheral area A of the opposite corner together with the boundary of the opposite corner (ie, the two sides S3 , S4 of the light emitting unit 40 ). The p-type electrode pad 80 may include two linear portions 82 and 84, and the two linear portions 82, 84 may extend from the two ends of the p-type electrode pad 80 adjacent to the two sides S3, S4 toward the n The n-type electrode pads 60 extend, and may intersect each other in the middle of the n-type electrode pads 60 . With this configuration, the distance between the p-type electrode pad 80 and the n-type electrode pad 60 can be sufficiently shortened without significantly increasing the area of the region behind the p-type electrode pad 80 (that is, the relative The area of the peripheral area A of the corner). This configuration substantially prevents uneven light emission caused by current crowding near the p-type electrode pad 80 .

The peripheral area A can be divided into two areas by an imaginary diagonal line (indicated by a chain line in FIG. 3 ) connecting vertices V1 , V2 at two corners of the light emitting unit 40 . Since these two regions are adjacent to both ends of the p-type electrode pad 80, the reduction in luminance is not severe. The angle defined between the two linear portions 82, 84 of the p-type electrode pad 80 may be greater than 90 degrees.

The shapes of the light emitting unit 40 and the electrode pads 60, 80 in plan view and the arrangement of the electrode pads 60, 80 on the light emitting unit may be modified in various ways without departing from the scope and spirit of the present invention. For example, the shape of the light emitting unit 40 is not limited to a square or a rectangle, and other shapes such as a circular shape, a parallelogram shape, or a trapezoidal shape may be used. Furthermore, it should be understood that the n-type electrode pad 60 and the p-type electrode pad 80 may be formed of one or more suitable electrode materials. 4, 5, 6, 7, 8, 9, 10, and 11 show various shapes and arrangements of light emitting units 40 and electrode pads 60, 80 according to exemplary embodiments of the present invention. .

In FIG. 4 , the n-type electrode pad 60 and the p-type electrode pad 80 may be arranged on the substantially square (or rectangular) light emitting unit 40 as shown in FIG. 3 . However, the angle defined between the two linear portions 82 , 84 of the p-type electrode pad 80 may be the same as the angle defined between the two linear portions 62 , 64 of the n-type electrode pad 60 . For example, the angle defined between the two linear portions 82, 84 of the p-type electrode pad 80 may be 90 degrees.

In FIG. 5, the p-type electrode pad 80 may be composed of a single linear portion. The p-type electrode pad 80 may include two end portions disposed adjacently with respect to two sides S3 , S4 of a corner portion opposite to the n-type electrode pad 60 . Although the p-type electrode pad 80 is composed of a single linear portion, the p-type electrode pad 80 may be defined as surrounding the peripheral area A of the opposite corner together with the sides S3, S4 of the opposite corner. In addition, since the two ends of the p-type electrode pad 80 are adjacent to the sides S3 and S4 of the opposite corners, and the central area of the p-type electrode pad 80 is adjacent to the n-type electrode pad 60, the luminescence of FIG. The device also has improved uniformity of light emission.

FIG. 6 shows a modification of the light emitting device shown in FIG. 5, wherein both ends of the linear portion of the p-type electrode pad 80 are bent to form extension arms 85a, 85b, similar to the light emitting device in FIG. Than, the extension arms 85a, 85b are closer to the two sides S3, S4 of the opposite corner. The extension arms 85a, 85b may be oriented perpendicularly towards the sides S3, S4. The extension arms 85 a , 85 b may form an obtuse angle with the central portion of the p-type electrode pad 80 .

FIG. 7 shows a light emitting unit 40 having a parallelogram shape.

FIG. 8 shows two adjacent light emitting units 420 , 430 in which a single n-type electrode pad 60 is commonly included in the two adjacent light emitting units 420 , 430 . 8, a linear portion 64 of the n-type electrode pad 60 is commonly included in two adjacent light emitting units 420, 430, and another linear portion 62 of the n-type electrode pad 60 in one light emitting unit 420 can be The linear portion 66 connected to the n-type electrode pad 60 in the other light emitting unit 430 forms a straight line.

FIG. 9 shows a light emitting unit 40 having a circular shape. In FIG. 9, the n-type electrode pad 60 may have an arc shape formed along a part of the circumference of the light-emitting unit 40, and the p-type electrode pad 80 may be formed on the light-emitting unit 40 in parallel with the n-type electrode pad 60. On the upper surface, the peripheral area A of the light emitting unit 40 can be surrounded and defined by the p-type electrode pad 80 together with the arc-shaped boundary of the light emitting unit 40 . Both ends of the p-type electrode pad 80 may be located near the border or circumference of the light-emitting unit 40, and the central area of the p-type electrode pad 80 facing the n-type electrode pad 60 may be positioned to be smaller than that of the p-type electrode pad 80. Both ends are closer to the n-type electrode pad 60 . In some cases, lighting unit 40 may have an oval shape or any other suitable geometric shape including curves.

FIG. 10 shows a light emitting unit 40 having an octagonal shape. The light emitting unit 40 may be formed by removing a region indicated by a dashed-dotted line from a tetragonal shaped light emitting unit to form an octagon. Therefore, the n-type electrode pad 60 is disposed at one corner of the octagonal light emitting unit 40 . The n-type electrode pad 60 may have a shape corresponding to this corner of the light emitting unit 40 . For example, two short linear portions may be connected to both ends of a single extended linear portion at the center of the n-type electrode pad 60, and the p-type electrode pad 80 may have the same shape as the n-type electrode pad 60. shape, and can be arranged parallel to the n-type electrode pad 60. The p-type electrode pad 80 may surround the peripheral area A of the opposite corner of the octagonal light emitting device 40 together with the boundary of the opposite corner. Both ends of the p-type electrode pad 80 may be perpendicular to the boundary of the light emitting unit 40 and/or be closer to the boundary of the light emitting unit 40 than the central area of the p-type electrode pad 80 .

11A and 11B are images showing luminosity test results of light emitting diodes. 11A is an example (“Example”) of luminance test results of a light emitting diode (eg, the light emitting diode according to FIG. 2 ) according to an exemplary embodiment of the present invention. FIG. 11B is an example ("comparative example") of a luminosity test result of a light emitting diode according to a conventional light emitting diode (for example, the light emitting diode according to FIG. 1 ). Table 1 shows the electrical characteristics of the example in FIG. 11A and the comparative example in FIG. 11B . The material of the semiconductor layer for the light emitting unit and the size of the light emitting unit are the same in FIGS. 11A and 11B , but the arrangement of the electrode pads is different in FIGS. 11A and 11B . Each light emitting unit may include an the ITO layer.

In the light emitting diode of the example shown in FIG. 11A , the light emitting diode has uniform luminance. In contrast, in the light emitting diode of the comparative example shown in FIG. 11B , there is a difference in luminance between the region near the p-type electrode pad and the region away from the p-type electrode pad. Relatively dark areas in FIGS. 11A and 11B emit light brighter than other areas.

As is clear from Table 1 below, the light emitting diode of the example in FIG. 11A has better power efficiency than that of the comparative example. In addition, the example light emitting diodes had lower forward voltage, higher power, and higher power efficiency than the comparative examples.

Table 1

[Table 1]

FIG. 12 is a cross-sectional view taken along line I-I of the light emitting diode 100 of FIG. 2 according to an exemplary embodiment of the present invention.

Referring to FIG. 12 , a light emitting diode 100 may include a single substrate 20 and a plurality of light emitting units 40 as described above formed on the single substrate 20 . Each light emitting unit 40 may include an n-type lower semiconductor layer 43, a p-type upper semiconductor layer 44 that may be formed on at least a portion of the n-type lower semiconductor layer 42, and an organic layer interposed between the lower semiconductor layer 42 and the upper semiconductor layer 44. source layer 43 . The lower semiconductor layer 42 may be disposed on the substrate 20 , or alternatively, the lower semiconductor layer 42 may be formed on the buffer layer 41 disposed on the substrate 20 in some cases. The light emitting diode 100 may include a transparent electrode layer 46 in each light emitting unit 40 . The light emitting diode 100 may include an insulating layer 99 , a wiring layer 130 , a microlens 110 and a protective insulating film 120 . The wiring layer 130 may be formed through a step covering process, and may integrally include the n-type electrode pad 60 , the p-type electrode pad 80 and the wiring 52 , as shown in FIG. 2 .

Referring to FIG. 12, the lower semiconductor layer 42, the active layer 43, and the upper semiconductor layer 44 may be made of gallium nitride-based semiconductor materials such as boron (B), aluminum (Al), indium (In), or gallium (Ga) nitrides. form. The material and composition of the active layer 43 may be selected according to a desired emission wavelength (eg, ultraviolet light or blue light). The lower semiconductor layer 42 and the upper semiconductor layer 44 may be formed of a material having a bandgap energy higher than that of the active layer 43 . The lower semiconductor layer 42 and/or the upper semiconductor layer 44 may have a single-layer structure or a multi-layer structure. In addition, the active layer 43 may have a single quantum well structure or a multiple quantum well structure.

In FIG. 12 , the lower semiconductor layer 42 may have a stepped portion formed along the sidewall of the light emitting diode 100 . A region of the light emitting unit 40 on the stepped portion of the lower semiconductor layer 42 may be defined as a mesa. The mesa sidewalls may be sloped such that the width of the mesa may gradually decrease away from the substrate 20 . The inclination angle of the sidewall of the mesa with respect to the upper surface of the substrate 20 may range from 15 degrees to 80 degrees. The region of the lower semiconductor layer 42 below the mesa may also have sidewalls that are sloped to have widths that gradually decrease away from the substrate 20 . The inclination angle of the sidewall of the lower semiconductor layer 42 with respect to the upper surface of the substrate 20 may range from 15 degrees to 80 degrees.

Such an inclined configuration of the lower semiconductor layer 42 may facilitate conformal deposition of other layers (eg, the insulating layer 99 and the wiring layer 130 ) to be formed on the light emitting unit 40 .

The inclination angle of the sidewall of the mesa may be the same as that of the sidewall of the lower semiconductor layer 42 located below the sidewall of the mesa. However, exemplary embodiments of the present invention are not limited thereto, and these inclination angles may be adjusted to any various and suitable angles. For example, the inclination angle of the sidewall of the mesa may be smaller than the inclination angle of the sidewall of the lower semiconductor layer 42 . As a result, light generated from the active layer 43 can be easily emitted through the mesa sidewall, thereby improving light extraction efficiency while securing a relatively wide area for the light emitting unit.

Each light emitting unit 40 may include a current shield 48 under at least a portion of the wiring layer 130 (specifically, under the p-type electrode pad 60 ). A current shield 48 may be provided to the lower semiconductor layer 42 , the active layer 43 and/or the upper semiconductor layer 44 of each light emitting unit 40 . The current shield 48 may shield a direct flow of current from the wiring layer 130 formed on the upper semiconductor layer 44 to allow wide current diffusion on the transparent electrode layer 46 . The current shield 48 may be formed of an insulating material such as silicon dioxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), silicon nitride (Si ₃ N ₄ ), or titanium dioxide (TiO ₂ ), and may be formed by alternating A distributed Bragg reflector (DBR) is formed by stacking materials with different refractive indices. The DBR may have a structure in which a layer with a relatively low refractive index and a layer with a relatively high refractive index are repeatedly stacked on top of each other. A layer with a relatively low refractive index may be formed of SiO ₂ or Al ₂ O ₃ , and a layer with a relatively high refractive index may be formed of Si ₃ N ₄ or TiO ₂ .

The buffer layer 41 may be employed to alleviate lattice mismatch between the substrate 20 and the lower semiconductor layer 42 . Specifically, if the substrate 20 is a growth substrate (specifically, a sapphire substrate), lattice mismatch may occur.

The transparent electrode layer 46 may be located on the upper semiconductor layer 44 and may have an area smaller than that of the upper semiconductor layer 44 . The transparent electrode layer 46 may be recessed from the edge of the upper semiconductor layer 44 . Accordingly, it is possible to prevent current crowding at the edge of the transparent electrode layer 46 through the sidewall of the light emitting unit 40 .

The insulating layer 99 covers the light emitting unit 40 . The insulating layer 99 may have openings formed on the lower semiconductor layer 42 and openings formed on the upper semiconductor layer 44 or the transparent electrode layer 46 . Sidewalls of the light emitting unit 40 may be covered with an insulating layer 99 . The insulating layer 99 may also cover the substrate 20 in regions between the light emitting units 40 . The insulating layer may be formed of any suitable material including, for example, silicon dioxide (SiO ₂ ) or silicon nitride.

A wiring layer 130 may be formed on the insulating layer 99 . The wiring layer 130 may be formed (partially, through the opening) on the lower semiconductor layer 42 , the upper semiconductor layer 44 , the current shield 48 and/or the transparent electrode layer 46 . The part of the wiring layer 130 formed on the lower semiconductor layer 42 and the upper semiconductor layer 44 through the opening may be the n-type electrode pad 60 and the p-type electrode pad 80, and the wiring layer 130 is connected to the electrode pad of the adjacent light emitting unit. The portion located on the insulating layer 99 may be the wiring 52 .

The wiring layer 130 may be electrically connected to the upper semiconductor layer 44 via the transparent electrode layer 46 . The wiring layer 130 may connect the lower semiconductor layer 42 of the light emitting unit 40 to the upper semiconductor layer 44 of an adjacent light emitting unit to form a series array of the light emitting unit 40 . According to an exemplary embodiment of the present invention, the light emitting diode 100 may have a plurality of series arrays connected in antiparallel to each other and driven by an AC power source. A bridge rectifier (not shown) may be connected to the series array of lighting units to enable the lighting units to be driven by AC power. The bridge rectifier can be formed by connecting light emitting units having the same configuration as that of the light emitting unit 40 via a wiring layer or wiring. The wiring layer or wiring may be formed from any suitable conductive material, doped semiconductor material (eg, polysilicon) or metal.

The microlens 110 may be formed on the wiring layer 130 and the insulating layer 99 . The microlens 110 may have a hemispherical convex surface to function as a convex lens. The microlens 110 may have a horizontal diameter on the order of micrometers, for example, 9 micrometers (μm). The microlens 110 may be formed of a material having a lower refractive index than that of the transparent electrode layer 140 . For example, the microlens 110 may be formed of a polymer. Examples of polymers may include polyimide (PI), epoxy (SU-8), spin-on-glass (SOG), methyl methacrylate (PMMA), polydimethylsiloxane (PDMS), Polycarbonate (PC), silicone gels and resins. The refractive index of the transparent electrode layer 46 and/or the microlens 10 may vary according to the refractive index of the material adjacent to the transparent electrode layer 46 and/or the microlens 110 . For example, if a gallium nitride semiconductor layer with a refractive index of 2.45 is used as the upper semiconductor layer 44 , an ITO layer with a refractive index of 2.04 can be used as the transparent electrode layer 46 . In addition, if a _SiO2 layer with a refractive index of 1.54 is used as the protective insulating layer 120, the microlens 110 may have a refractive index ranging from 1.67 to 1.8, which is between the refractive index of the transparent electrode layer 46 and the protective insulating layer. The index of refraction is between 120 and 120. Therefore, the microlenses may have insulating properties. However, in some cases the microlenses may be conductive.

A protective insulating layer 120 may be formed to cover the microlens 110 . The protective insulating layer 120 may prevent the microlens 110 and the wiring layer 130 from being contaminated by, for example, moisture, and prevent the wiring layer 130 from being damaged by external force. The protective insulating layer 120 may be formed of a light-transmissive material such as, for example, a silicon dioxide film (SiO ₂ ) or a silicon nitride film.

13 , 14 , 15 and 16 are cross-sectional views illustrating a method of manufacturing the light emitting diode shown in FIG. 12 .

Referring to FIG. 13 , a lower semiconductor layer 42 , an active layer 43 and an upper semiconductor layer 44 may be formed on a substrate 20 . The buffer layer 41 may be formed on the substrate 20 before forming the lower semiconductor layer 42 .

The substrate 20 can be sapphire (Al ₂ O ₃ ), silicon carbide (SiC), zinc oxide (ZnO), silicon (Si), gallium arsenide (GaAs), gallium phosphide (GaP), lithium-alumina (LiAl ₂ O ₃ ), boron nitride (BN), aluminum nitride (AlN) or gallium nitride (GaN) substrate, or any suitable material. The substrate 20 can be selected from various materials according to the materials forming the semiconductor layers 42 , 43 , 44 .

The buffer layer 41 may be formed to alleviate lattice mismatch between the substrate 20 and the lower semiconductor layer 42 . For example, the buffer layer 41 may be formed of gallium nitride (GaN) or aluminum nitride (AlN). If the substrate 20 is a conductive substrate, the buffer layer 41 may be an insulating layer or a semi-insulating layer. For example, the buffer layer 41 may be formed of AlN or semi-insulating GaN.

For example, the lower semiconductor layer 42, the active layer 43, and the upper semiconductor layer 44 may be formed of a GaN-based compound semiconductor material such as nitride of B, Al, In, or Ga. The lower semiconductor layer 42, the upper semiconductor layer 44, and the active layer 43 may be formed discontinuously or continuously by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy, or hydride vapor phase epitaxy (HVPE).

The upper semiconductor layer 44 and the lower semiconductor layer 42 may be an n-type semiconductor layer or a p-type semiconductor layer, respectively, or vice versa. The n-type semiconductor layer can be formed by doping n-type impurities such as silicon (Si) into the GaN-based compound semiconductor layer, and can be formed by doping p-type impurities such as magnesium (Mg) into the GaN-based compound semiconductor layer. The p-type semiconductor layer is formed in the semiconductor layer.

The current shield 48 may be formed on a portion of the upper semiconductor layer 44 located below the wiring layer 130 (eg, below the p-type electrode pad 80 ) (see FIG. 2 ). In some cases, current shield 48 may be formed on regions of lower semiconductor layer 42 , active layer 43 , and/or upper semiconductor layer 44 . The current shield 48 may be formed of an insulating material such as SiO ₂ , Al ₂ O ₃ , Si ₃ N ₄ , or TiO ₂ , and the current shield 48 may be formed by alternately stacking materials with different refractive indices on top of each other. The distributed Bragg reflector (DBR).

A transparent electrode layer 46 may be formed on the current shield 48 and the upper semiconductor layer 44 . For example, transparent electrode layer 46 may be formed from any suitable conductive oxide, such as indium tin oxide (ITO). Portions of the transparent electrode layer 46 , the upper semiconductor layer 44 , the active layer 43 and the lower semiconductor layer 42 may be etched using a photoresist pattern (not shown) as an etching mask. As a result, the photoresist pattern can be transferred to the semiconductor layers 42, 44, 44 to form mesas with sloped sidewalls.

While the photoresist pattern remains on the mesa, the transparent electrode layer 46 may be recessed by wet etching. The transparent electrode layer 46 may be recessed from the edge of the upper semiconductor layer 44 on the mesa using an etchant by adjusting the etching time, and then the photoresist pattern is removed.

The lower semiconductor layer 42 may be etched using a photoresist pattern (not shown) as an etch mask to form divided light emitting units 40, wherein the photoresist pattern may cover a plurality of mesas while defining a plurality of light emitting unit regions. The buffer layer 41 may also be etched to expose the upper surface of the substrate 20 .

While the lower semiconductor layer 42 is etched through the photoresist pattern, the mesas may be covered with the photoresist pattern. Therefore, the mesas can be prevented from being damaged during the isolation process. In addition, a stepped portion may be formed on the lower semiconductor layer 42 as shown in the drawing through an isolation process. Then, the photoresist pattern can be removed.

Referring to FIG. 14 , a continuous insulating layer 99 may be formed on the light emitting unit 40 . The insulating layer 99 may cover sidewalls and upper surfaces of the light emitting cells 40 and the upper surface of the substrate 20 in regions between the light emitting cells 40 . The insulating layer 99 may be formed of silicon oxide or silicon nitride by chemical vapor deposition (CVD).

Since the sidewall of the light emitting unit 40 is inclined and the lower semiconductor layer 42 is formed with a stepped portion, the insulating layer 99 can easily cover the sidewall of the light emitting unit 40 .

The insulating layer 99 may be patterned to have openings exposing the lower semiconductor layer 42 and openings exposing the transparent electrode layer 46 by photolithography and etching. The opening may also expose the upper semiconductor layer 44 .

Referring to FIG. 15 , a wiring layer 130 may be formed on the insulating layer 99 having an opening. A part of the wiring layer 130 can be electrically connected to the lower semiconductor layer 42 and the upper semiconductor layer 44 through the opening, so that the lower semiconductor layer 42 of the adjacent light emitting unit can be electrically connected to the upper semiconductor layer 44 of the light emitting unit 40 through the wiring layer 130 .

The wiring layer 130 may be formed by plating or vapor deposition such as electron beam deposition. Since a stepped portion can be formed on the side wall of each light emitting unit 40 (for example, on the side wall of the lower semiconductor layer 42), the wiring layer 130 can be stably formed on the side wall of the light emitting unit 40, thereby preventing wiring open circuit and/or short circuit. The light emitting units 40 may be connected to each other on the substrate through the wiring layer 130 .

Referring to FIG. 16 , microlenses 110 may be formed on the light emitting unit 40 . The microlens 110 may be formed by wet etching after forming a polymer layer on the wiring layer 130 on the substrate 20 . The microlens 110 may cover some regions of the lower semiconductor layer 42 and mesa sidewalls exposed by the mesa etching. In some cases, after forming the polymer layer, a photoresist pattern (not shown) may be formed into a lens shape by a reflow technique, and then the polymer layer may be subjected to dry etching using the photoresist pattern as an etching mask to Microlenses 110 are formed.

FIG. 17 shows plan views of various microlenses according to exemplary embodiments of the present invention.

As shown in (a) of FIG. 17 , the microlens 110 may have a circular or elliptical shape in plan view. For example, the horizontal cross-section of the microlens 110 may have a circular or elliptical shape. However, the horizontal cross-section of the microlens 110 may not be limited to a circular or elliptical shape, but may have a shape including, for example, a hexagonal shape as shown in (b) and (c) of FIG. 17 , Any suitable shape including triangular or quadrilateral shapes. When the horizontal cross-section of the microlenses has a hexagonal shape or a triangular shape, the microlenses 110 may be arranged in a denser arrangement.

The shape of the microlens 110 can be any suitable combination of horizontal and vertical cross-sectional shapes, and can be selected based on various factors such as manufacturing and light extraction efficiency. For example, when the microlens 110 has a vertical cross section of a triangular shape as shown in (c) in FIG. 17 and a horizontal cross section of a triangular shape as shown in (c) in FIG. 17 , the microlens 110 may have Tetrahedral shape. As a result, light entering the microlens 110 may be easily reflected to the outside.

In addition, the microlens 110 may have a smooth surface as shown in FIG. 18 , or may have an uneven surface as shown in FIG. 19 .

In FIG. 12, when microlenses 110 having various shapes are disposed on the transparent electrode 46 and mesa sidewalls, light generated in the active layer 43 can be emitted through the microlenses 110, thereby improving light extraction efficiency.

A protective insulating film 120 may be formed on the microlens 110 . The protective insulating film 120 may be formed of a light-transmitting material such as silicon oxide or silicon nitride by chemical vapor deposition.

The light emitting diode 100 according to an exemplary embodiment of the present invention has significantly improved uniformity of light emission and power efficiency through improved current spreading characteristics between the first electrode pad and the second electrode pad in the light emitting unit. In particular, a light emitting diode (eg, an AC light emitting diode) including a plurality of light emitting units on a single substrate enables the light emitting unit to emit uniform light with significantly improved power efficiency.

While the invention has been described with reference to some exemplary embodiments in conjunction with the accompanying drawings, it will be apparent to those skilled in the art that various modifications and effects may be made in the invention without departing from the spirit and scope of the invention. Change. Therefore, it should be understood that the examples are provided by way of illustration only, and that the examples are not given to provide complete disclosure of the invention and to provide a thorough understanding of the invention to those skilled in the art. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the claims and their equivalents.

Claims (18)

1. a light emitting diode, including:

Substrate；

Multiple luminescence units, are arranged in substrate, first area that each luminescence unit includes being in the boundary of luminescence unit and the second area relative with first area；

First electrode pad, is arranged on first area place；

Second electrode pad, has linearity configuration and is arranged in the face of the first electrode pad, and the second electrode pad limits outer peripheral areas together with the border of second area；And

Wiring, is connected to the second electrode pad of the second luminescence unit by the first electrode pad of the first luminescence unit,

Wherein, the second electrode pad includes two linear segments extending towards the first electrode pad with the two of second area ends that limit is adjacent and intersecting each other at the mid portion of the second electrode pad from the second electrode pad.

2. light emitting diode as claimed in claim 1, wherein, the end of the second electrode pad is adjacent with the border of second area.

3. light emitting diode as claimed in claim 2, wherein, wiring forms with the first electrode pad and the second electrode pad.

4. light emitting diode as claimed in claim 1, wherein, the first electrode pad includes at least two linear segment or at least one sweep that are connected to each other along the profile of first area.

5. light emitting diode as claimed in claim 1, wherein, each luminescence unit includes quadrangle form, and the first electrode pad includes two limits being respectively parallel to first area and two linear segments intersected each other near the summit of first area.

6. light emitting diode as claimed in claim 5, wherein, the angle limited between the linear segment of the second electrode pad is more than or equal to the angle limited between the linear segment of the first electrode pad.

7. light emitting diode as claimed in claim 5, wherein, a linear segment in two linear segments of the first electrode pad of one luminescence unit is included in another luminescence unit adjacent with one luminescence unit, and another linear segment of the first electrode pad of one luminescence unit is connected to the linear segment in another luminescence unit described and forms straight line.

8. light emitting diode as claimed in claim 1, wherein, each luminescence unit includes polygonal shape, and the first electrode pad is parallel to the second electrode pad.

9. light emitting diode as claimed in claim 1, described light emitting diode also includes:

First bond pad and the second bond pad, be arranged in substrate,

Wherein, the plurality of luminescence unit includes: the first luminescence unit, including the first electrode pad being connected to the first bond pad；Second luminescence unit, including the second electrode pad being connected to the second bond pad via wiring.

10. light emitting diode as claimed in claim 1, described light emitting diode also includes the lenticule being arranged on luminescence unit.

11. light emitting diode as claimed in claim 10, described light emitting diode also includes the protection dielectric film being arranged on lenticule.

12. light emitting diode as claimed in claim 1, wherein, each luminescence unit includes the current shielding part preventing electric current from spreading below the second electrode pad.

13. light emitting diode as claimed in claim 12, wherein, current shielding part includes at least one material selected from silicon dioxide, aluminium oxide, silicon nitride and titanium dioxide.

14. light emitting diode as claimed in claim 13, wherein, the structure of current shielding part includes being alternately stacked the low-index layer above each other and high refractive index layer, and low-index layer includes silicon dioxide or aluminium oxide, and high refractive index layer includes silicon nitride or titanium dioxide.

15. a light emitting diode, including:

Luminescence unit, including being in the first area of boundary of luminescence unit and the second area relative with first area；

First electrode pad, is arranged on first area place；And

Second electrode pad, including linearity configuration and be arranged in the face of the first electrode pad, the second electrode pad limits outer peripheral areas together with the border of second area,

Wherein, the second electrode pad includes two linear segments extending towards the first electrode pad with the two of second area ends that limit is adjacent and intersecting each other at the mid portion of the second electrode pad from the second electrode pad.

16. light emitting diode as claimed in claim 15, wherein, the first electrode pad includes at least two linear segment or at least one sweep that are connected to each other along the profile of first area.

17. light emitting diode as claimed in claim 15, wherein, luminescence unit includes quadrangle form, and the first electrode pad includes two limits being respectively parallel to first area and two linear segments intersected each other near the summit of first area.

18. light emitting diode as claimed in claim 17, wherein, the angle limited between the linear segment of the second electrode pad is more than or equal to the angle limited between the linear segment of the first electrode pad.