CN102969303A - Semiconductor package structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a semiconductor packaging structure and a manufacturing method thereof, wherein in the manufacturing method, a substrate is provided, and a plurality of grounding pads are arranged on the substrate; then, arranging a first semiconductor element and a second semiconductor element on the substrate, wherein the grounding pad is positioned between the first semiconductor element and the second semiconductor element; then, a plurality of conductive bonding wires are connected to the grounding pad. The semiconductor packaging structure can effectively shield electromagnetic interference by using the conductive bonding wire.

Description

Semiconductor package structure and manufacturing method thereof

technical field

The invention relates to a semiconductor packaging structure and a manufacturing method thereof, in particular to a semiconductor packaging structure with an electromagnetic signal shielding structure and a manufacturing method thereof.

Background technique

In the semiconductor production process, integrated circuit packaging (IC package) is one of the important steps in the manufacturing process. It is used to protect the IC chip and provide external electrical connections to prevent damage from external forces or environmental factors during transportation and placement. In addition, integrated circuit components also need to be combined with passive components such as resistors and capacitors to form a system in order to perform the intended function, and electronic packaging (Electronic Packaging) is used to establish the protection and organizational structure of integrated circuit components. Generally speaking, electronic packaging begins after the integrated circuit chip manufacturing process, including IC chip bonding and fixing, circuit connection, structural sealing, bonding with circuit boards, system assembly, and all processes until product completion.

At present, in the semiconductor packaging structure, there will be unnecessary noise or interference between chips, such as electromagnetic interference (EMI), especially on chips for wireless communication, this problem is more obvious. At this time, a metal lid is generally used to shield electromagnetic signal interference. However, the disposition of the metal cover will increase the weight and thickness of the semiconductor package structure, and will increase the manufacturing cost of the metal cover.

Therefore, it is necessary to provide a semiconductor packaging structure and a manufacturing method thereof to solve the problems existing in the prior art.

Contents of the invention

An object of the present invention is to provide a semiconductor package structure, which includes a substrate, a first semiconductor element, a second semiconductor element, and a plurality of conductive bonding wires. One surface of the substrate is provided with a plurality of ground pads, and the first and second semiconductor elements are arranged on the substrate, wherein the first semiconductor element includes a first surface close to the substrate, a second surface away from the substrate and a conductive layer, the conductive layer is formed on the second surface of the first semiconductor element. A plurality of ground pads are arranged between the first and second semiconductor elements, and a plurality of conductive bonding wires are connected between the conductive layer of the first semiconductor element and the ground pads.

Another object of the present invention is to provide a semiconductor package structure, which includes a substrate, a first semiconductor element, a second semiconductor element, and a plurality of conductive bonding wires. One surface of the substrate is provided with a plurality of ground pads, the first and second semiconductor elements are arranged on the substrate, the plurality of ground pads are arranged on both sides of the first semiconductor element, and at least part of the ground pads are located on the first and second semiconductor elements. Between the elements, a plurality of conductive bonding wires are connected between the ground pads on both sides of the first semiconductor element.

Another object of the present invention is to provide a method for manufacturing a semiconductor package structure. In the manufacturing method of this semiconductor package structure, first, a substrate is provided, wherein a plurality of ground pads are arranged on the substrate, and then, a first semiconductor element and a second semiconductor element are arranged on the substrate, wherein the ground pads are located on the first semiconductor Between the element and the second semiconductor element, the first semiconductor element includes a first surface close to the substrate, a second surface away from the substrate and a conductive layer, the conductive layer is formed on the second surface of the first semiconductor element, and then, A plurality of conductive bonding wires are connected between the ground pad and the conductive layer of the first semiconductor element.

The semiconductor package structure of the present invention can shield unnecessary interference, such as electromagnetic interference (EMI/EMC), by grounding conductive bonding wires between semiconductor elements, thereby effectively isolating electromagnetic signals of adjacent semiconductor elements. Because the semiconductor packaging structure of the present invention can reduce or omit the existing metal cover to shield electromagnetic wave interference, the overall weight and process cost are reduced.

In order to make the above content of the present invention more obvious and understandable, the preferred embodiments are specifically cited below, and in conjunction with the accompanying drawings, the detailed description is as follows:

Description of drawings

1 shows a cross-sectional view of a semiconductor package structure according to a first embodiment of the present invention;

2 shows a top view of a semiconductor package structure according to a first embodiment of the present invention;

FIG. 3 shows the relationship between the pitch of the conductive bonding wires and the coupling effect of the semiconductor package structure according to an embodiment of the present invention;

4A to 4C show a manufacturing flow chart of a packaging substrate according to an embodiment of the present invention;

5 shows a top view of a semiconductor package structure according to a second embodiment of the present invention;

FIG. 6A, FIG. 6B and FIG. 6C show top views of semiconductor package structures according to third to fifth embodiments of the present invention;

7 shows a top view of a semiconductor package structure according to a sixth embodiment of the present invention;

FIG. 8, which shows a top view of a semiconductor package structure according to a seventh embodiment of the present invention;

9 shows a cross-sectional view of a semiconductor package structure according to an eighth embodiment of the present invention; and

FIG. 10 shows a perspective view of a semiconductor package structure according to an eighth embodiment of the present invention.

Detailed ways

The following descriptions of the various embodiments refer to the accompanying drawings to illustrate specific embodiments in which the present invention can be practiced. The directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are for reference only The orientation of the attached schema. Therefore, the directional terms used are used to illustrate and understand the present invention, but not to limit the present invention.

In the figures, structurally similar units are denoted by the same reference numerals.

Please refer to FIG. 1 and FIG. 2 , FIG. 1 shows a cross-sectional view of a semiconductor package structure according to a first embodiment of the present invention, and FIG. 2 shows a top view of a semiconductor package structure according to a first embodiment of the present invention. The semiconductor package structure 100 of this embodiment includes a substrate 110 , a first semiconductor element 120 , a second semiconductor element 130 , a plurality of ground pads 140 , a plurality of conductive bonding wires 150 and an encapsulant 160 . The first semiconductor element 120 , the second semiconductor element 130 and the ground pad 140 are disposed on the substrate 110 , and the ground pad 140 is at least located between the first semiconductor element 120 and the second semiconductor element 130 . The conductive bonding wire 150 is connected between the ground pad 140 and the first semiconductor element 120 for forming a shielding effect. The encapsulant 160 is formed on the substrate 110 and covers the first semiconductor device 120 , the second semiconductor device 130 and the plurality of conductive bonding wires 150 .

As shown in FIGS. 1 and 2 , the substrate 110 includes at least one circuit layer 111 and at least one conductive hole 112 . When the substrate 110 includes multiple circuit layers 111 , these circuit layers 111 are electrically connected by conductive holes 112 . The ground pad 140 on the substrate 110 is electrically connected to the circuit layer 111 of the substrate 110 . The substrate 110 may be, for example, a multilayer printed circuit substrate.

The first semiconductor device 120 includes a bump 121 , a conductive layer 122 , a first surface 123 close to the substrate, and a second surface 124 away from the substrate. The first semiconductor element 120 and the second semiconductor element 130 can be respectively selected from a semiconductor chip (chip) or a semiconductor package (package). ) packaging technology, chip scale packaging (ChipScale Package) technology, flip chip (Flip chip) technology or other packaging methods to be disposed on the substrate 110 . At this time, the active surface (first surface 123 ) of the first semiconductor element 120 is a surface facing the substrate 110 . The first semiconductor element 120 and the second semiconductor component 130 can be disposed on the substrate 110 through bumps 121 , 131 , respectively, and electrically connected to circuits in the substrate 110 through the bumps 121 , 131 .

The first semiconductor device 120 has a conductive layer 122 formed on the back side (second surface 124 ) of the first semiconductor device 120 , and the conductive layer 122 can be a metal (eg, copper, nickel, gold, silver) thin film. In this embodiment, the first semiconductor element 120 is a semiconductor element (chip or package) to be shielded, and the second semiconductor element 130 can be any semiconductor element (chip or package) or electronic element (such as a passive element). ).

As shown in Figures 1 and 2, in this embodiment, the ground pads 140 can be arranged around the first semiconductor element 120 and electrically connected to the ground circuit inside the substrate, while the conductive bonding wire 150 is soldered to the first semiconductor element 120. Between the conductive layer 122 of a semiconductor device 120 and the ground pad 140 . Wherein, the material of the conductive bonding wires 150 may be copper, gold or other metal materials, the line width of each conductive bonding wire 150 may be 15 microns (μm) to 30.5 microns, and the pitch between the conductive bonding wires 150 may be Less than 300 microns (μm), for example, 60 μm˜280 μm, when the distance between the conductive bonding wires is greater than 300 μm, the shielding effect on electromagnetic wave interference is poor.

As shown in FIGS. 1 and 2 , the encapsulant 160 of this embodiment can be used to cover and protect the first semiconductor device 120 , the conductive bonding wire 150 and the second semiconductor device 130 . The insulating base material of the encapsulant 160 can be epoxy resin (epoxy), polymethyl methacrylate (PMMA), polycarbonate (Polycarbonate) or silicone, which is used to protect the components inside the encapsulation structure from the outside world. Effects of temperature, humidity or atmosphere.

The conductive layer 122 and the conductive bonding wire 150 not only have the function of electromagnetic signal shielding, but also have the function of improving the heat dissipation of the semiconductor device.

Please refer to FIG. 3 , which shows a relationship diagram between the pitch of the conductive bonding wires and the coupling effect of the semiconductor package structure according to an embodiment of the present invention. The line L1 represents the coupling effect of the package structure without the conductive bonding wire 150 , and the line L2 represents the relationship between the line pitch and the coupling effect of the semiconductor package structure 100 with the conductive bonding wire 150 . Compared with the package structure without the conductive bonding wire 150 (as shown by the line L1), the semiconductor package structure 100 with the conductive bonding wire 150 may have a lower coupling effect (as shown by the line L2), that is, the conductive bonding wire 150 can effectively shield the electromagnetic coupling effect between electronic components, and has the effect of shielding electromagnetic signals.

Please refer to FIG. 4A to FIG. 4C , which show a manufacturing flow chart of a packaging substrate according to an embodiment of the present invention. When manufacturing the semiconductor package structure 100 of this embodiment, first, as shown in FIG. 4A , the substrate 110 is provided. At this time, the ground pads 140 can be pre-arranged on the substrate 110 and electrically connected to the internal ground circuit of the substrate. Next, as shown in FIG. 4B , the first semiconductor device 120 and the second semiconductor device 130 are disposed on the substrate 110 . At this time, the ground pad 140 is at least located between the first semiconductor device 120 and the second semiconductor device 130 . Next, as shown in FIG. 4C , a wire bonding step is performed to connect the conductive bonding wire 150 between the ground pad 140 and the conductive layer 122 of the first semiconductor device 120 . Next, an encapsulant 160 is formed to cover the first semiconductor device 120 , the second semiconductor device 130 and the conductive bonding wire 150 .

Please refer to FIG. 5 , which shows a top view of a semiconductor package structure according to a second embodiment of the present invention. In the second embodiment, the conductive bonding wires 150 can be alternately connected between the ground pads 140 and the conductive layer 122 .

Please refer to FIG. 6A , FIG. 6B and FIG. 6C , which show top views of semiconductor package structures according to third to fifth embodiments of the present invention. The ground pad 140 is at least arranged between the first semiconductor element 120 and the second semiconductor element 130 . In the third to fifth embodiments, the ground pad 140 may be disposed on only one side, two sides or three sides of the first semiconductor element 120 .

Please refer to FIG. 7 , which shows a top view of a semiconductor package structure according to a sixth embodiment of the present invention. In the sixth embodiment, each ground pad 140 can be in the shape of a strip, which surrounds the first semiconductor element 120 , and multiple conductive bonding wires can be bonded on the same ground pad at the same time.

Please refer to FIG. 8 , which shows a top view of a semiconductor package structure according to a seventh embodiment of the present invention. In another embodiment, the first semiconductor element 120 may be disposed on the substrate 110 through, for example, the surface adhesive layer 125 instead of the solder ball 121 . At this time, the first semiconductor element 120 may be disposed on the substrate 110 by, for example, Land Grid Array (LGA) packaging technology, Quad Flat No-lead Package (Quad Flat No-lead Package) technology or other packaging methods.

Please refer to FIG. 9 and FIG. 10 , FIG. 9 shows a cross-sectional view of a semiconductor package structure according to an eighth embodiment of the present invention, and FIG. 10 shows a perspective view of a semiconductor package structure according to an eighth embodiment of the present invention. In the eighth embodiment, the first semiconductor element 220 may not have the conductive layer 122, the ground pads 240 are disposed on both sides of the first semiconductor element 220, and at least part of the ground pads 240 are located between the first semiconductor element 220 and the second Between semiconductor elements 130 . A plurality of conductive bonding wires 250 are connected between the ground pads 240 on both sides of the first semiconductor element 220 and cross over the first semiconductor element 220 to shield the first semiconductor element 220 .

In summary, although the present invention has been disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present invention, and those of ordinary skill in the art can make various modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the claims.

Claims (10)

1. semiconductor package, it is characterized in that: described semiconductor package comprises:

One substrate, a surface of described substrate is provided with a plurality of ground mats;

One first semiconductor element, be arranged on the described substrate, wherein said the first semiconductor element comprises one near the first surface of substrate, away from second surface and a conductive layer of substrate, and described conductive layer is to be formed on the described second surface of described the first semiconductor element;

One second semiconductor element is arranged on the described substrate, and wherein said a plurality of ground mats are arranged between described first and second semiconductor element; And

Many conduction bonding wires are connected between the described conductive layer and described ground mat of described the first semiconductor element.

2. semiconductor package according to claim 1, it is characterized in that: described the first semiconductor element is selected from semiconductor chip or semiconductor package body.

3. semiconductor package according to claim 1, it is characterized in that: the spacing between the described conduction bonding wire is less than 300 microns.

4. semiconductor package according to claim 1, it is characterized in that: the live width of each described conduction bonding wire is 15 microns～30.5 microns.

5. semiconductor package according to claim 1, it is characterized in that: described conductive layer is metallic film.

6. semiconductor package according to claim 1 is characterized in that: described ground mat be arranged in described the first semiconductor element around.

7. semiconductor package according to claim 1, it is characterized in that: each described ground mat is elongated, and around described the first semiconductor element, wherein a plurality of conduction bonding wires are beaten simultaneously on same ground mat.

8. semiconductor package according to claim 1, it is characterized in that: described conduction bonding wire is to be connected in alternately between described ground mat and the described conductive layer.

9. semiconductor package, it is characterized in that: described semiconductor package comprises:

One substrate, a surface of described substrate is provided with a plurality of ground mats;

One first semiconductor element is arranged on the described substrate;

One second semiconductor element is arranged on the described substrate, and wherein said a plurality of ground mats are arranged at the both sides of described the first semiconductor element, and at least part of described ground mat is between described first and second semiconductor element; And

Many conduction bonding wires are connected between the described ground mat of described the first semiconductor element both sides.

10. the manufacture method of a semiconductor package, it is characterized in that: described manufacture method comprises:

One substrate is provided, and wherein a plurality of ground mats are arranged on the described substrate;

The first semiconductor element and the second semiconductor element are set on described substrate, wherein said ground mat is between described first and second semiconductor element, described the first semiconductor element comprises a first surface near substrate, away from second surface and a conductive layer of substrate, described conductive layer is to be formed on the described second surface of described the first semiconductor element; And

Many conduction bonding wires are connected between the described conductive layer of described ground mat and described the first semiconductor element.

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