CN102800606A - A Stress Sensor Transfer Method for Wafer Level Packaging Stress Measurement - Google Patents

Abstract

The invention relates to a stress sensor transfer method for measuring wafer level packaging stress, which comprises the following steps: manufacturing a stress sensor on the top silicon of the SOI silicon chip; the stress sensor is attached to a test wafer with the same size as the wafer to be packaged face to face by using an organic adhesive film; and corroding and removing the stress sensor substrate silicon, and transferring the stress sensor chip unit onto the test wafer. The stress sensor is manufactured on the small-size silicon wafer, the processing cost of the small-size silicon wafer is obviously lower than that of the large-size silicon wafer, the chip cut from one sensor wafer can meet the use amount of a plurality of test wafers, and the use cost is far lower than that of the large-size test wafer directly manufactured.

Description

A Stress Sensor Transfer Method for Wafer Level Packaging Stress Measurement

technical field

The invention relates to the technical fields of integrated circuit manufacturing, packaging and measurement, in particular to a stress sensor transfer method for wafer-level packaging stress measurement.

Background technique

The packaging process of the integrated circuit introduces stress in the integrated circuit chip. Since the carrier mobility of semiconductor materials such as silicon will change with stress, packaging stress will have a significant impact on the performance of integrated circuits. In addition, material fatigue caused by package stress changing with temperature is an important cause of integrated circuit failure. It is generally necessary to reduce packaging stress through optimization of materials, packaging structures, and processes.

The stress sensor fabricated by utilizing the piezoresistive effect of silicon is a powerful tool for package stress measurement. The piezoresistive stress sensor uses the piezoresistive effect of silicon (that is, the effect that carrier mobility changes with stress), and calculates the stress distribution state on the chip surface by measuring the change in resistance value caused by stress.

The stress sensor can be well applied to the process optimization and daily monitoring of traditional chip-scale packaging. The so-called chip-level packaging means that the integrated circuit wafer to be packaged is first cut into small-sized chips, and then the cut chips are packaged. Chip-scale packaging is a traditional packaging method for integrated circuits.

The general method of using stress sensors in chip-level packaging is as follows: first, make a dedicated test chip, and make a stress sensor on the test chip, and the size and pad layout of the test chip are the same as the chip to be packaged; use the packaging process to be optimized for the test The chip is packaged, and the stress introduced by the packaging process can be obtained by measuring the output change of the stress sensor on the test chip before and after packaging; optimize the packaging process and package the test chip again and measure the stress; repeat the above steps until the stress reaches the target value.

Since the test chip with the stress sensor is only used for process optimization and monitoring, its usage is small. In order to reduce the cost, it is generally produced by cheap processing technology, and its minimum line width and silicon wafer size are significantly different from the integrated circuit chip to be packaged. For example, the size of the integrated circuit chip to be packaged is 10 mm × 10 mm, and it is fabricated on a 12-inch silicon wafer using an advanced process with a minimum line width of 0.09 microns, while the stress sensor can be manufactured on a 4-inch silicon wafer with a minimum line width of 1 micron. As long as the chip size of the stress sensor is 10mm×10mm, and the thickness and pad arrangement are the same as those of the integrated circuit chip to be tested, the accuracy of the stress measurement results can be guaranteed.

With the development of integrated circuit packaging technology, wafer level packaging (Wafer Level Package) is becoming more and more popular. The so-called wafer-level packaging refers to the packaging process of packaging uncut integrated circuit wafers and then cutting them into small chips.

Existing stress sensor technologies are difficult to be widely used for process validation and monitoring of wafer-level packaging. If the existing stress sensor technology is used to study the stress of wafer-level packaging, it is necessary to make a test wafer with the same size as the silicon wafer of the integrated circuit to be packaged, and to fabricate a stress sensor on the test wafer. That is to say, when performing WLP verification of 8-inch wafers, it is necessary to manufacture 8-inch test wafers, and when performing WLP verification of 12-inch wafers, it is necessary to manufacture 12-inch test wafers. The processing cost of an 8-inch or 12-inch integrated circuit process line is high, and its development cost is high due to the small amount of test wafers used. High development costs limit the application of stress sensors in wafer-level packaging.

Contents of the invention

The technical problem to be solved by the present invention is to provide a stress sensor transfer method for wafer-level packaging stress measurement, which can reduce processing costs.

The technical solution adopted by the present invention to solve the technical problem is: provide a stress sensor transfer method for wafer-level package stress measurement, comprising the following steps:

(1) Make a stress sensor on the top silicon of the SOI silicon wafer;

(2) Mount the stress sensor face-to-face on the test wafer of the same size as the wafer to be packaged by using an organic film;

(3) Erosion removes the stress sensor substrate silicon, and transfers the stress sensor chip unit to the test wafer.

The step (1) also includes the following sub-steps:

(11) Etch the top layer of silicon by reactive ion etching technology, and make a stress sensing unit on the top layer of silicon;

(12) Make a lead window on the buried silicon dioxide through a photolithographic etching process;

(13) A thin film layer is deposited by sputtering and metal leads are formed by photolithography and corrosion techniques.

In the step (2), the organic adhesive film is manufactured on the stress sensor silicon wafer by mechanical spin coating or dry film lamination, and the thickness of the organic adhesive film is less than 10 microns.

In the step (2), the stress sensor chip is mounted face-to-face on the test wafer having the same size as the wafer to be packaged by means of chip-to-wafer bonding.

In the step (3), the substrate silicon of the stress sensor is removed by a dry etching process, wherein the etching rate of the integrated circuit passivation layer and the metal layer is much lower than that of silicon.

The organic film is BCB glue, polyimide film, PerMX dry film.

Beneficial effect

Due to the adoption of the above-mentioned technical solution, the present invention has the following advantages and positive effects compared with the prior art: the present invention makes the stress sensor on the small-sized silicon wafer, and the processing cost of the small-sized silicon wafer is significantly lower than that of the large-sized silicon wafer. The size of the silicon wafer, and the chip cut out of a sensor wafer can meet the amount of multiple test wafers, and the cost of use is much lower than the direct production of large-size test wafers. This technology can be used not only for the research of wafer level packaging process, but also for daily stress monitoring of wafer level packaging.

Description of drawings

Fig. 1 is the sectional view of stress sensor among the present invention;

Fig. 2 is the top view of stress sensor among the present invention;

Fig. 3 is the schematic diagram after the spin-coating organic thin film of stress sensor in the present invention;

Fig. 4 is the schematic diagram that the stress sensor is flipped on the silicon wafer among the present invention;

Fig. 5 is the schematic diagram after removing stress sensor substrate silicon in the present invention;

Fig. 6 is a schematic diagram of the device after thinning in the present invention;

Fig. 7 is a schematic cross-sectional view of a silicon wafer to be packaged;

8 is a schematic diagram of a cross-sectional structure of wafer-level packaging;

FIG. 9 is a schematic diagram of a cross-sectional structure of the test wafer after packaging;

Fig. 10 is a schematic cross-sectional view of the silicon wafer to be packaged after removing the test point solder bump;

Fig. 11 is a schematic cross-sectional view after the stress sensor is fabricated by transferring the test point;

FIG. 12 is a schematic diagram of a cross-sectional structure after packaging.

Detailed ways

Below in conjunction with specific embodiment, further illustrate the present invention. It should be understood that these examples are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the teachings of the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of the present application.

Embodiments of the present invention relate to a stress sensor transfer method for wafer-level packaging stress measurement, including the following steps: first, a dedicated test chip is fabricated, a stress sensor is fabricated on the test chip, and the size of the test chip and the arrangement of the pads are consistent with The chip to be packaged is the same; the test chip is packaged with the package process to be optimized, and the stress introduced by the package process can be obtained by measuring the output change of the stress sensor on the test chip before and after package; optimize the package process and package the test chip again and Measure the stress; repeat the above steps until the stress reaches the target value.

The specific steps are as follows: (1) Fabricate the stress sensor on the top silicon layer of the SOI silicon wafer; (2) Mount the stress sensor face-to-face on the test wafer with the same size as the wafer to be packaged by using an organic film; (3) Etch and remove Stress sensor substrate silicon, transfer the stress sensor chip unit to the test wafer.

That is to say, the sensor unit is first prepared on the SOI silicon wafer, and the organic film is spin-coated or pasted on the sensor unit, and the SOI silicon wafer is cut into chips. The size of the chip is the same as that of the chip on the wafer to be packaged; The sensor chip is mounted face-to-face on the stress wafer to be tested by a welding machine or a placement machine, and the mounting temperature, pressure and process time are selected according to the bonding conditions of the organic film. The top layer of silicon is removed by dry etching, leaving only a thin layer of stress sensor unit, buried silicon dioxide and metal wiring on the wafer to be tested.

As shown in FIG. 1 , the stress sensor 1 is fabricated on the top silicon layer of the SOI silicon wafer 3 on the crystal plane. The stress sensor 1 is made by etching the top layer silicon 3 into the shape shown in Figure 2 by reactive ion etching technology and doping with boron and phosphorus with a concentration of 1015/ ^cm3-1019 / ^cm3 respectively. The P-type force-sensitive resistor unit and the N-type force-sensitive resistor unit. Then, a lead window 6 is made on the buried silicon dioxide by photolithography and etching processes. A metal aluminum (Al) thin film layer 5 is deposited by sputtering, and metal leads are formed by using photolithography processing technology and aluminum corrosion technology. The process of making the lead window 6 on the buried silicon dioxide 4 is different from the general stress sensor chip manufacturing process.

The organic adhesive film 2 used in the described stress sensor transfer method is Benzocyclobutene (BCB) adhesive film, polyimide adhesive film, PerMX dry film etc., adopts the method for mechanical rotation gluing or dry film bonding to make on the stress sensor on a silicon wafer and scribed into individual stress sensor chips. In order to accurately obtain the stress on the surface of the silicon wafer, the thickness of the adhesive film should generally be controlled within 10 microns.

The chip to wafer bonding process (Chip to Wafer bonding) is processed by flip-chip welding machine or chip mounter. The temperature and pressure applied during the bonding process are determined according to the selected organic film. For example, the bonding temperature of BCB film is 200°C-250°C, the bonding pressure is 4 kPa-10 kPa, and the bonding time is 1 hour. Hour.

The method for etching the bottom silicon of the sensor chip is dry etching. The etching rate of the selected dry etching process for the passivation layer and the metal layer of the integrated circuit is much lower than the etching rate for silicon, such as xenon difluoride gas phase etching and other methods. Since the lead window 6 is pre-opened on the buried silicon dioxide layer, after the substrate silicon is etched away, the aluminum pad 5 is exposed, and there is no need to perform photolithography and etching of the oxide layer.

In order to meet the miniaturization of devices and the multi-layer stacking process in packaging, generally the entire silicon wafer needs to be thinned before packaging.

Firstly, the 0.2-micron-thick top layer silicon of SOI silicon wafer is etched into an island shape by sulfur hexafluoride deep reactive ion etching technology, and doped with 1018/ ^cm3 boron and phosphorus ions to make the force-sensitive resistor unit, using sputtering Technology deposits a 0.7 micron metal Al thin film layer and uses photolithography technology and ion beam etching technology to make metal wiring 5 . Then a 0.3 micron BCB thin film 2 is spin-coated on the manufactured sensor wafer to form the structure shown in FIG. 3 . After cutting into chips, mount them on the test wafer 7 by flip-chip welding. The process conditions are heating to 230°C, adding 100 grams of force to achieve pressure, and holding time for 1 hour, forming the structure shown in Figure 4. . The top silicon 3 is removed by xenon difluoride vapor phase etching. 5 is a schematic diagram of the silicon test wafer before being thinned after the transfer of the sensor is completed, and the thickness of the silicon test wafer before thinning is 500 microns. Test the zero point voltage output of the strain sensor unit 1. After the wafer is thinned to 100 microns (as shown in Figure 6), the voltage output of the sensor is tested again, and the stress generated by the test wafer during the thinning process can be calculated by comparing the two voltage signals.

This technology can not only be used for the optimization of wafer-level packaging process, but also for daily stress monitoring of wafer-level packaging. Reserve a test chip position on the surface of the wafer to be packaged, or remove the original bonding pad at the test position of the wafer to be packaged by selective etching. The stress sensor was transferred to the test site by the transfer process described above. By measuring the stress change of the stress sensor before and after packaging, the daily stress monitoring of wafer-level packaging can be realized.

The stress sensor transfer method can be used in wafer-level packaging process research. The silicon wafer to be packaged is shown in FIG. 7 . The wafer 8 is bonded together with the cover plate 12 through the organic adhesive film 11, and the electrical lead-out from the back is realized through the through-silicon via interconnection 13 and the solder ball 10, and the wafer-level packaging structure produced is shown in FIG. 8 .

In order to measure the stress of the packaging structure, a stress sensor chip is made, and the arrangement of its pads is the same as that of the pads 9 on the wafer to be packaged. A 0.3 micron BCB thin film 2 is spin-coated on the prepared sensor wafer, cut into chips, and mounted on the test wafer 7 by flip-chip welding. Determine the number and location of stress sensors according to the needs of process testing and optimization. The test wafer after the stress sensor transfer is completed is shown in FIG. 9 . The output of the stress sensor is measured using a probe station.

The test wafer is packaged using the structure and process shown in Figure 8, and the output of the stress sensor after packaging is measured. The difference between the output of the stress sensor before and after packaging corresponds to the stress introduced by the wafer-level packaging process.

Stress sensor transfer technology can be used for routine monitoring of wafer-level packaging stress. The silicon wafer to be packaged is shown in Figure 7, the wafer is bonded together with the cover plate 12 through the organic film 11, and the electrical lead-out from the back is realized through the silicon via interconnection 13 and the solder ball 14. The structure of the wafer-level package is shown in Figure 8.

In order to monitor the stress of the packaging structure, a stress sensor chip is fabricated, and the arrangement of its bonding pads is the same as that of the bonding pads on the wafer to be packaged. Spin-coat a 0.3-micron BCB film on the prepared sensor wafer and cut it into a sensor chip. Select test points on the wafer to be packaged according to monitoring requirements, and remove the pads at the positions of the test points by selective etching, as shown in FIG. 10 . Attach the sensor chip to the test point of the wafer to be packaged by flip-chip welding. The test wafer after the transfer of the stress sensor is shown in FIG. 11 . The output of the stress sensor is measured using a probe station.

The wafer to be packaged is packaged, and the fabricated structure is shown in FIG. 12 . Measure the post-package stress sensor output. The difference between the output of the stress sensor before and after packaging corresponds to the stress introduced by the wafer-level packaging process.

It is not difficult to find that the present invention manufactures stress sensors on small-sized silicon wafers, the processing cost of small-sized silicon wafers is significantly lower than that of large-sized silicon wafers, and the chips cut out from one sensor wafer can meet the requirements of multiple test wafers. The usage cost is much lower than the direct production of large-size test discs. This technology can be used not only for the research of wafer level packaging process, but also for daily stress monitoring of wafer level packaging.

Claims (6)

1. A stress sensor transfer method for wafer-level packaging stress measurement, characterized in that, comprising the following steps: (1) Make a stress sensor on the top silicon of the SOI silicon wafer; (2) Mount the stress sensor face-to-face on the test wafer of the same size as the wafer to be packaged by using an organic film; (3) Erosion removes the stress sensor substrate silicon, and transfers the stress sensor chip unit to the test wafer. 2. The stress sensor transfer method for wafer-level packaging stress measurement according to claim 1, wherein the step (1) further comprises the following sub-steps: (11) Etch the top layer of silicon by reactive ion etching technology, and make a stress sensing unit on the top layer of silicon; (12) Make a lead window on the buried silicon dioxide through a photolithographic etching process; (13) A thin film layer is deposited by sputtering and metal leads are formed by photolithography and corrosion techniques. 3. The stress sensor transfer method for wafer-level packaging stress measurement according to claim 1, characterized in that, in the step (2), the organic adhesive film is made by mechanical rotary gluing or dry film lamination On the silicon chip of the stress sensor, the thickness of the organic adhesive film is less than 10 microns. 4. The stress sensor transfer method for wafer-level packaging stress measurement according to claim 1, characterized in that, in the step (2), the stress sensor chip is mounted face-to-face by chip-to-wafer bonding onto a test wafer of the same size as the wafer to be packaged. 5. The stress sensor transfer method for wafer-level packaging stress measurement according to claim 2, characterized in that, in the step (3), a dry etching process is used to remove the substrate silicon of the stress sensor, wherein, for The etch rate of IC passivation and metal layers is much lower than that of silicon. 6. The stress sensor transfer method for wafer-level packaging stress measurement according to claim 3, wherein the organic film is a BCB film, a polyimide film, or a PerMX dry film.

Images