CN102650981A - Synchronous structure between programmable operational level parallel units - Google Patents
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Abstract
一种新型的基于邻接互连的阵列结构以及阵列单元之间的同步结构,该阵列中的每个单元,是通过软件可编程的,称为可编程处理元PPE(Programmable Processing Element)。每个单元与它邻接单元之间的连线只有东、西、南、北四个方向,是一种固定连接关系。PPE单元之间通过标志寄存器来实现数据的同步。每个PPE单元,称之为本地PPE,包含了东、西、南、北四个不同方向寄存器,称之为方向标志寄存器。当某个方向的数据准备好之后,给相应方向标志寄存器设置指示(高或者低电平)。相邻单元读取后将标志恢复,以此机制以完成数据同步。
A new array structure based on adjacent interconnection and synchronization structure between array units, each unit in the array is programmable through software, called Programmable Processing Element (PPE). The connection between each unit and its adjacent units has only four directions of east, west, south and north, which is a fixed connection relationship. The data synchronization is realized through the flag register between the PPE units. Each PPE unit, called local PPE, contains four different direction registers of east, west, south, and north, called direction flag registers. When the data in a certain direction is ready, set an indication (high or low level) to the corresponding direction flag register. After the adjacent unit is read, the flag is restored, and this mechanism is used to complete data synchronization.
Description
一、技术领域 1. Technical field
本发明涉及一种新型基于邻接互连的阵列处理器结构以及阵列单元之间的同步结构,属于计算机体系结构领域。The invention relates to a novel array processor structure based on adjacent interconnection and a synchronous structure between array units, belonging to the field of computer architecture.
二、背景技术 2. Background technology
由于半导体技术的不断进步,一个芯片内集成的晶体管数目已经到几十亿只,传统的单处理器计算机体系结构面临这个几个技术屏障:存储墙(MemoryWall)、ILP墙(Instruction Level Parallel Wall)、功耗墙(Power Wall)等。已有的并行计算机体系结构只是部分解决了上述问题,但是无法应对深亚微米技术下出现的红砖墙(Red Brick Wall)的问题。本发明的目的就是通过新型的体系结构来解决上述问题。Due to the continuous advancement of semiconductor technology, the number of transistors integrated in a chip has reached billions. The traditional single-processor computer architecture faces several technical barriers: memory wall (Memory Wall), ILP wall (Instruction Level Parallel Wall) , Power Wall (Power Wall), etc. Existing parallel computer architectures only partially solve the above problems, but cannot cope with the red brick wall (Red Brick Wall) problem that occurs under deep submicron technology. The purpose of the present invention is to solve the above-mentioned problems through a novel architecture.
三、发明内容 3. Contents of the invention
本发明提出一种新型的基于邻接互连的阵列结构以及阵列单元之间的同步结构,如图1所示。该阵列中的每个单元,是通过软件可编程的,称为可编程处理元PPE(Programmable Processing Element),说明如下:The present invention proposes a new array structure based on adjacent interconnection and a synchronization structure between array units, as shown in FIG. 1 . Each unit in the array is programmable by software and is called Programmable Processing Element (PPE), which is described as follows:
(1)连接关系:图1是一个由N*N的结构,除了四周的单元外,每个单元与它邻接单元之间的连线只有东、西、南、北四个方向,是一种固定连接关系。(1) Connection relationship: Figure 1 is a structure consisting of N*N. Except for the surrounding units, the connection between each unit and its adjacent units is only in four directions: east, west, south, and north. It is a kind of Fixed connection relationship.
(2)PPE单元:PPE单元,如附图1所示,是一种通过指令编程的可编程单元,可以是同质的,也可以是异质的,具有现在单CPU中的控制单元、数据通路,还包括数据存储器、指令存储器或者包含两者。(2) PPE unit: PPE unit, as shown in Figure 1, is a programmable unit programmed by instructions, which can be homogeneous or heterogeneous, and has the control unit and data in the current single CPU. Path, also includes data memory, instruction memory, or both.
(3)PPE单元之间的数据同步:PPE单元之间通过标志寄存器来实现数据的同步。每个PPE单元,称之为本地PPE,包含了东、西、南、北四个不同方向寄存器,称之为方向标志寄存器。当某个方向的数据准备好之后,给相应方向标志寄存器设置指示(高或者低电平)。本地PPE单元根据方向寄存器中指示来读取它四个邻接方向上的数据,当本地PPE读取数据后,将相应方向标志寄存器的标准设置为复位(高或者低电平),以此机制以完成数据同步。(3) Data synchronization between PPE units: data synchronization is realized between PPE units through a flag register. Each PPE unit, called local PPE, contains four different direction registers of east, west, south, and north, called direction flag registers. When the data in a certain direction is ready, set an indication (high or low level) to the corresponding direction flag register. The local PPE unit reads the data on its four adjacent directions according to the indication in the direction register. After the local PPE reads the data, the standard of the corresponding direction flag register is set to reset (high or low level). Complete data synchronization.
(4)PPE单元之间的数据传递:PPE单元包含了东西南北四个方向四个寄存器组,称之为数据传递寄存器组。本地PPE处理完后,根据指令中数据传输方向的要求,将数据写入到相应的传递寄存器组中。(4) Data transfer between PPE units: The PPE unit includes four register groups in four directions, east, west, north, south, called data transfer register groups. After the local PPE is processed, according to the requirements of the data transmission direction in the instruction, write the data into the corresponding transfer register group.
(5)指令存储器(Instruction Memory):图1中的指令寄存器用于存放数据并行级指令或者用于存放启动各个PE单元的Call指令。(5) Instruction Memory: The instruction register in Figure 1 is used to store data parallel level instructions or to store Call instructions for starting each PE unit.
四、附图说明: 4. Description of drawings:
图1本发明的阵列结构图;The array structure diagram of Fig. 1 the present invention;
图2本发明的单元同步结构示意图Fig. 2 is a schematic diagram of unit synchronization structure of the present invention
五、具体实施方式 5. Specific implementation
下面结合附图具体介绍本发明的具体工作方式。The specific working mode of the present invention will be described in detail below in conjunction with the accompanying drawings.
图2为PPE内部结构及同步结构示意图。如图2所示,所述同步结构通过独立的数据线在上下左右四个方向上与处理单元的ALU相连。输出数据线带有端口寄存器,以便存储输出数据供本地处理单元或相邻处理单元使用。同步结构内部有数据选择器,用以实现处理单元内部指令对各方向端口寄存器的访问。端口寄存器内带有标志位,相邻处理单元通过对标志位的判断来实现相邻PPE单元的数据交互和通信。这种相邻单元的数据同步结构不仅和标志位有关,还和本地及相邻PPE单元内部的指令有关,本地PPE根据本地指令确定操作后的数据送入哪个方向端口寄存器,是只向一个方向传送数据,还是向多个方向传送数据。相邻PPE单元不仅要根据标志位判断数据是否到达,还要判断到达的数据是一个还是多个方向都有数据到达,同时根据指令确定是需要的是那个方向的数据。有的内部指令需要根据来数据的方向和值来确定是否忽略某个方向的值。FIG. 2 is a schematic diagram of the internal structure and synchronization structure of the PPE. As shown in FIG. 2 , the synchronization structure is connected to the ALU of the processing unit in four directions: up, down, left, and right through independent data lines. The output data lines have port registers to store output data for use by the local processing unit or adjacent processing units. There is a data selector inside the synchronization structure, which is used to realize the access of the internal instructions of the processing unit to the port registers of each direction. There are flag bits in the port register, and the adjacent processing units realize data interaction and communication between adjacent PPE units by judging the flag bits. The data synchronization structure of this adjacent unit is not only related to the flag bit, but also related to the instructions inside the local and adjacent PPE units. The local PPE determines which direction the operated data is sent to the port register according to the local instructions, which is only in one direction. Send data, or send data in multiple directions. Adjacent PPE units not only need to judge whether the data has arrived according to the flag bit, but also judge whether the arriving data has data arriving in one or more directions, and at the same time determine whether the data in that direction is needed according to the instruction. Some internal instructions need to determine whether to ignore the value of a certain direction according to the direction and value of the incoming data.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106502923B (en) * | 2016-09-30 | 2018-08-24 | 西安邮电大学 | Storage accesses ranks two-stage switched circuit in cluster in array processor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5535365A (en) * | 1993-10-22 | 1996-07-09 | Cray Research, Inc. | Method and apparatus for locking shared memory locations in multiprocessing systems |
| US5630162A (en) * | 1990-11-13 | 1997-05-13 | International Business Machines Corporation | Array processor dotted communication network based on H-DOTs |
| CN101454755A (en) * | 2005-05-26 | 2009-06-10 | Vns组合有限责任公司 | Computer system with increased operating efficiency |
| CN101546302A (en) * | 2009-05-07 | 2009-09-30 | 复旦大学 | Interconnection structure of multicore processor and hierarchical interconnection design method based on interconnection structure |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5630162A (en) * | 1990-11-13 | 1997-05-13 | International Business Machines Corporation | Array processor dotted communication network based on H-DOTs |
| US5535365A (en) * | 1993-10-22 | 1996-07-09 | Cray Research, Inc. | Method and apparatus for locking shared memory locations in multiprocessing systems |
| CN101454755A (en) * | 2005-05-26 | 2009-06-10 | Vns组合有限责任公司 | Computer system with increased operating efficiency |
| CN101546302A (en) * | 2009-05-07 | 2009-09-30 | 复旦大学 | Interconnection structure of multicore processor and hierarchical interconnection design method based on interconnection structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106502923B (en) * | 2016-09-30 | 2018-08-24 | 西安邮电大学 | Storage accesses ranks two-stage switched circuit in cluster in array processor |
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