CN102646710A - A Superjunction Vertical Double-Diffused Metal-Oxide Semiconductor Transistor - Google Patents

Abstract

The invention provides a super-junction vertical double-diffusion metal oxide semiconductor tube, comprising an N-type heavily-doped silicon substrate which is used as a drain region, wherein drain electrode metal is arranged on the lower surface of the N-type heavily-doped silicon substrate; an N-type doped silicon epitaxial layer is arranged on the upper surface of the N-type heavily-doped silicon substrate; a discontinuous P-type doped columnar semiconductor region is arranged in the N-type doped silicon epitaxial layer; a first P-type doped semiconductor region is arranged on the P-type doped columnar semiconductor region; the first P-type doped semiconductor region is arranged in the N-type doped silicon epitaxial layer; and the first P-type doped semiconductor region is internally provided with a second P-type doped semiconductor contact region and an N-type doped semiconductor source region. The super-junction vertical double-diffusion metal oxide semiconductor tube is characterized in that: the N-type doped semiconductor source region is connected with active electrode metal; the second P-type doped semiconductor contact region is connected with substrate metal; polycrystalline silicon which is used as an resistor is arranged below the active electrode metal and the substrate metal; and the polycrystalline silicon is respectively connected with the active electrode metal and the substrate metal, and top layer metal is connected with the substrate metal.

Description

A Superjunction Vertical Double-Diffused Metal-Oxide Semiconductor Transistor

technical field

The invention belongs to the technical field of semiconductor power devices, relates to silicon high-voltage power devices affected by movable ion contamination, and is particularly suitable for silicon superjunction vertical double-diffused metal oxide field effect transistors (Superjunction VDMOS, namely superjunction VDMOS, as follows Both are abbreviated as super-junction VDMOS), more specifically, it relates to a silicon-made super-junction VDMOS terminal structure with high reliability under high-temperature reverse bias conditions.

Background technique

At present, power devices are more and more widely used in daily life, production and other fields, especially power metal oxide semiconductor field effect transistors, because they have faster switching speed, smaller drive current, and wider safe operating area , so it has been favored by many researchers. Nowadays, power devices are developing towards higher working voltage, higher working current, lower on-resistance and integration. The invention of the superjunction was a milestone in power MOSFET technology.

Power devices are not only favored in the cutting-edge technology fields such as national defense, aerospace, and aviation, but also in the fields of industry and civilian household appliances. With the increasing development of power devices, their reliability has become the focus of people's general attention. Power devices provide the required form of power supply for electronic equipment and drive for electrical equipment. Almost all electronic equipment and electrical equipment require power devices, so the research on device reliability is of great significance.

The definition of reliability is the ability of the product to complete the specified functions under specified conditions and within a specified time. The so-called prescribed conditions mainly refer to the conditions of use and environmental conditions. Service conditions refer to those stress conditions that will enter into the product or material, such as electrical stress, chemical stress and physical stress. The scope of reliability test is very wide, and its purpose is to assess various complex mechanical and environmental conditions that electronic products such as electronic components may encounter during storage, transportation and work.

Under the condition that the drain terminal voltage of the device rises rapidly, the change of voltage reacts to form a displacement current on the parasitic capacitance, and the displacement current acts on the base resistance of the parasitic triode to generate a voltage, causing the parasitic triode to turn on and damage the device. Therefore, it is extremely important to improve the reliability of the device drain terminal voltage variation.

Contents of the invention

The present invention provides a super junction metal oxide field effect transistor with high reliability. In the structure involved, when the parasitic triode is turned on, the current flows through the resistance connected to the source, so that the potential of the emitter rises, so that the base of the parasitic triode The potential difference between the region and the emitter is reduced, thereby suppressing the opening of the parasitic triode and improving the reliability of the device drain voltage change.

The present invention adopts following technical scheme:

A super-junction vertical double-diffused metal oxide semiconductor tube, comprising: an N-type heavily doped silicon substrate serving as a drain region, a drain metal is arranged on the lower surface of the N-type heavily doped silicon substrate, and the N-type The upper surface of the heavily doped silicon substrate is provided with an N-type doped silicon epitaxial layer, and an intermittent and discontinuous P-type doped columnar semiconductor region is arranged in the N-type doped silicon epitaxial layer, and in the P-type doped columnar semiconductor region A first-type doped semiconductor region is provided on it, and the first P-type doped semiconductor region is located in an N-type doped epitaxial layer, and a second P-type heavily doped semiconductor contact is arranged in the first P-type doped semiconductor region. Region and N-type heavily doped semiconductor source region, a gate oxide layer is provided above the N-type doped silicon epitaxial layer, and the gate oxide layer is located in the N-type doped silicon epitaxial layer between adjacent P-type doped columnar semiconductor regions Above the part, a polysilicon gate is provided above the gate oxide layer, and a first-type oxide layer is provided on the polysilicon gate, which is characterized in that the source metal is connected to the N-type heavily doped semiconductor source region, and the second P The substrate metal is connected to the heavily doped semi-conductor contact region, and polysilicon as a resistor is provided under the source metal and the substrate metal, and the polysilicon is respectively connected to the source metal and the substrate metal, and connected to the substrate metal. Has top metal.

Compared with prior art, the present invention has following advantage:

1. Compared with the traditional superjunction vertical double-diffused metal oxide semiconductor tube structure, the superjunction vertical double-diffused metal oxide semiconductor tube structure involved in the present invention separates the substrate metal and the source metal, and uses polysilicon resistors to separate the substrate metal and the source metal. The substrate metal and the source metal are connected. When the parasitic triode is turned on, the current flows through the resistance connected to the source, which increases the potential of the emitter and reduces the potential difference between the base area of the parasitic triode and the emitter, thereby inhibiting the opening of the parasitic triode and improving the leakage of the device. Reliability of terminal voltage variation; at the same time, compared with the traditional superjunction vertical double-diffused metal-oxide-semiconductor structure of a super-junction vertical double-diffused metal-oxide semiconductor structure involved in the present invention, the area of the device will not increase .

Description of drawings

FIG. 1 is a schematic diagram of the overall structure of a super-junction vertical double-diffused metal-oxide-semiconductor transistor involved in the present invention.

FIG. 2 is a top-level schematic diagram of a superjunction vertical double-diffused metal-oxide-semiconductor transistor structure involved in the present invention.

FIG. 3 is a cross-sectional view of an active region of a superjunction vertical double-diffused metal-oxide-semiconductor transistor structure involved in the present invention in FIG. 2 .

FIG. 4 is a cross-sectional view of a transition region of a superjunction vertical double-diffused metal-oxide-semiconductor transistor structure in FIG. 2 according to the present invention.

FIG. 5 is a schematic cross-sectional schematic diagram of a super-junction vertical double-diffused metal-oxide-semiconductor tube structure involved in the content of the invention.

Detailed ways

A super-junction vertical double-diffused metal oxide semiconductor tube, comprising: an N-type heavily doped silicon substrate 2 serving as a drain region, a drain metal 1 is arranged on the lower surface of the N-type heavily doped silicon substrate 2, An N-type doped silicon epitaxial layer 3 is arranged on the upper surface of the N-type heavily doped silicon substrate 2, and an intermittent and discontinuous P-type doped columnar semiconductor region 4 is arranged in the N-type doped silicon epitaxial layer 3. The P-type doped columnar semiconductor region 4 is provided with a first P-type doped semiconductor region 5, and the first P-type doped semiconductor region 5 is located in the N-type doped epitaxial layer 3, and in the first P-type doped semiconductor region 5 is provided with a second P-type heavily doped semiconductor contact region 7 and an N-type heavily doped semiconductor source region 6, and a gate oxide layer 8 is provided above the N-type doped silicon epitaxial layer 3, and the gate oxide layer 8 is located in the phase Above the N-type doped silicon epitaxial layer between the adjacent P-type doped columnar semiconductor regions 4, a polysilicon gate 9 is provided above the gate oxide layer 8, and a first-type oxide layer 10 is provided on the polysilicon gate 9. A source metal 11 is connected to the N-type heavily doped semiconductor source region 6, a substrate metal 12 is connected to the second P-type heavily doped semiconductor contact region 7, and the source metal 11 and the substrate metal 12 are provided below There is polysilicon 13 as a resistor, and the polysilicon 13 is respectively connected to the source metal 11 and the substrate metal 12 , and the top layer metal 14 is connected to the substrate metal 12 .

Below with reference to accompanying drawing, specific embodiment of the present invention is described in more detail:

FIG. 1 is a schematic diagram of the overall structure of a super-junction metal oxide field effect transistor with high reliability involved in the present invention. Among them, I is the terminal region, II is the transition region, III is the active region, and IV is a specific reference range.

Fig. 2 is a schematic plan view of the superjunction metal oxide field effect transistor structure with high reliability of the present invention, the top layer is represented by a solid line, and the layers below the top layer are represented by a dotted line, along the lines AA' and BB' in Fig. 2 The cross-sectional schematic diagrams are shown in Figure 3 and Figure 4 respectively. Through Figures 3 and 4, you can see the arrangement relationship of each level from top to bottom. In FIG. 2 , 15 is a hole connecting the top layer metal 14 and the substrate metal 12 , and 16 is a hole connecting the polysilicon resistor 13 to the source metal 11 and the substrate metal 12 .

Claims (1)

1. A super-junction vertical double-diffused metal oxide semiconductor tube, comprising: an N-type heavily doped silicon substrate (2) serving as a drain region, arranged on the lower surface of the N-type heavily doped silicon substrate (2) There is a drain metal (1), an N-type doped silicon epitaxial layer (3) is provided on the upper surface of an N-type heavily doped silicon substrate (2), and an N-type doped silicon epitaxial layer (3) is provided with An intermittent and discontinuous P-type doped columnar semiconductor region (4), a first P-type doped semiconductor region (5) is arranged on the P-type doped columnar semiconductor region (4), and the first P-type doped semiconductor region (5) Located in the N-type doped epitaxial layer (3), a second P-type heavily doped semiconductor contact region (7) and an N-type heavily doped semiconductor region (7) are provided in the first P-type doped semiconductor region (5) In the source region (6), a gate oxide layer (8) is provided above the N-type doped silicon epitaxial layer (3), and the gate oxide layer (8) is located between adjacent P-type doped columnar semiconductor regions (4) Above the N-type doped silicon epitaxial layer part, a polysilicon gate (9) is provided above the gate oxide layer (8), and a first-type oxide layer (10) is provided on the polysilicon gate (9), characterized in that, A source metal (11) is connected to the N-type heavily doped semiconductor source region (6), a substrate metal (12) is connected to the second P-type heavily doped semiconductor contact region (7), and the source metal ( 11) polysilicon (13) as a resistor is provided under the substrate metal (12), and the polysilicon (13) is respectively connected to the source metal (11) and the substrate metal (12), and the substrate metal (12) A top layer metal (14) is connected thereto.

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