CN102332427A - Method for manufacturing first copper interconnection layer - Google Patents
Method for manufacturing first copper interconnection layer Download PDFInfo
- Publication number
- CN102332427A CN102332427A CN201110310442A CN201110310442A CN102332427A CN 102332427 A CN102332427 A CN 102332427A CN 201110310442 A CN201110310442 A CN 201110310442A CN 201110310442 A CN201110310442 A CN 201110310442A CN 102332427 A CN102332427 A CN 102332427A
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- China
- Prior art keywords
- etching
- ultralow dielectric
- copper
- protective film
- ground floor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 15
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 15
- 239000010949 copper Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 18
- 230000001681 protective effect Effects 0.000 claims abstract description 16
- 238000005516 engineering process Methods 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000001259 photo etching Methods 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 238000009713 electroplating Methods 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 14
- 210000001951 dura mater Anatomy 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 229920000620 organic polymer Polymers 0.000 claims description 3
- 238000004062 sedimentation Methods 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 3
- 230000008021 deposition Effects 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000005498 polishing Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 235000019994 cava Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
Images
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a method for manufacturing a first copper interconnection layer, comprising the following steps of: depositing an ultra-low dielectric constant film, a protective film of the ultra-low dielectric constant film and a metal hard mask on a silicon wafer in sequence; coating a photoresist and carrying out photoetching to form a first etching window; etching the metal hard mask in the first etching window, forming a second etching window in the metal hard mask, and etching the protective film of the ultra-low dielectric constant film and the ultra-low dielectric constant film in the second etching window to form a groove; and adopting an electroplating technology to carry out copper filling and deposition on the groove, and carrying out chemically mechanical polishing to form the first copper interconnection layer. In the method, the metal hard mask is taken as a mask, so that the selection ratio of the etching is improved, thus reducing the thickness of the photoresist, avoiding the photoresist at a high position from collapsing with narrowing of the line width and preventing the generation of a rounded corner at the top of the groove, thereby lessening leakage current and improving the reliability.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of manufacture method of ground floor copper-connection.
Background technology
Along with the continuous progress of very lagre scale integrated circuit (VLSIC) technology, the characteristic size of semiconductor device is constantly dwindled, and chip area continues to increase, and can compare with the device gate delay time time of delay of interconnecting line.People are faced with how to overcome the problem that the RC (R refers to resistance, and C refers to electric capacity) that brings owing to the rapid growth that connects length postpones remarkable increase.Particularly, cause device performance to descend significantly, become the crucial restraining factors that semi-conductor industry further develops because the influence of metal line line capacitance is serious day by day.The RC that causes in order to reduce to interconnect postpones, and has adopted multiple measure at present.
Parasitic capacitance between the interconnection and interconnection resistance have caused the transmission delay of signal.Because copper has lower resistivity, superior electromigration resistance properties and high reliability can reduce the interconnection resistance of metal, and then reduce total interconnect delay effect, change into low-resistance copper-connection by the aluminium interconnection of routine at present.The electric capacity that reduces simultaneously between the interconnection can reduce to postpone equally, and parasitic capacitance C is proportional to the relative dielectric constant k of circuit layer dielectric, therefore uses low-k materials to replace traditional SiO as the dielectric of different circuit layers
2Medium has become the needs of the development of satisfying high-speed chip.
In order to reduce the parasitic capacitance between the metal interconnecting layer; Prior art has use low-k (low-k) material even ultralow dielectric (untra-low-k) material; And in order to reduce dielectric constant, advanced low-k materials and ultra-low dielectric constant material generally are made into porous, loose structure.Yet the ultra-low dielectric constant material weak point of porous, open structure is: frangible, be prone to be caused in follow-up manufacturing process, combining difficulty with other layer by contaminating impurity, profile, damage, the reliability of interconnection layer are not easy control simultaneously;
The Damascus technics of prior art is made in the copper interconnection layer; Along with the characteristic size of semiconductor device is constantly dwindled, existing photoresist thickness can not reach the precision of control small-feature-size, in order to obtain accurate characteristic size; Thickness through increasing photoresist prolongs the photoetching time; Yet thick photoresist layer caves on the narrow line as a groove part easily and the profile of narrow line is not easy control, is prone at narrow line top form fillet, makes that distance diminishes between the narrow line; Thereby the leakage current between the narrow line increases, and then reliability decrease.
Summary of the invention
The manufacture method that the purpose of this invention is to provide a kind of ground floor copper-connection to avoid fillet occurring as the narrow line top of a groove part, reduces leakage current, improves reliability.
Technical solution of the present invention is a kind of manufacture method of ground floor copper-connection, may further comprise the steps:
On silicon chip, deposit ultralow dielectric film, ultralow dielectric thin protective film and metal die successively;
On the metal die, apply photoresist and form first etching window through photoetching;
Etching metal dura mater in first etching window, etching stopping is removed photoresist again on the ultralow dielectric thin protective film, in the metal dura mater, form second etching window, and said second etching window is used at the window of subsequent step as etching groove;
Ultralow dielectric thin protective film and ultralow dielectric film in etching second etching window form the groove that is communicated with silicon chip;
The inculating crystal layer of sputtering sedimentation metal barrier and copper in groove; Adopt electroplating technology to carry out copper and fill deposit; Remove metal die, ultralow dielectric thin protective film and part ultralow dielectric film through cmp, form the ground floor copper interconnection layer.
As preferably: said ultralow dielectric thin protective film material is a silicon dioxide.
As preferably: said ultralow dielectric film adopts the organic polymer spin coating proceeding or adopts based on SiO
2The CVD technology of material forms, and the dielectric constant of said ultralow dielectric film is 2.2-2.8.
As preferably: the thickness of said ultralow dielectric film is
As preferably: the material of said metal die is Ta or Ti or W or TaN or TiN or WN.
Compared with prior art, it is mask that the present invention adopts the metal dura mater, has improved the selection ratio of etching; Compare the situation that makes with photoresist as mask; Make the present invention in photoetching process, reduce the thickness of photoresist, avoid narrowing down the possibility that high photoresist collapses along with live width; Avoid the groove top fillet to occur simultaneously, thereby reduce leakage current and then improve reliability.
Description of drawings
Fig. 1 is that the present invention makes flow chart.
Fig. 2 a-Fig. 2 f is the profile that one embodiment of the invention is made each processing step in the flow process.
Embodiment
The present invention below will combine accompanying drawing to do further to detail:
A lot of details have been set forth in the following description so that make much of the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed practical implementation.
Secondly, the present invention utilizes sketch map to be described in detail, when the embodiment of the invention is detailed; For ease of explanation; The profile of expression device architecture can be disobeyed general ratio and done local the amplification, and said sketch map is instance, and it should not limit the scope of the present invention's protection at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
As shown in Figure 1, the manufacture craft of said ground floor copper-connection is following:
In step 1; Shown in Fig. 2 a; Deposition ultralow dielectric film 201 and ultralow dielectric thin protective film 202 on silicon chip 200; Plated metal die 203 on ultralow dielectric thin protective film 202, the material of said metal die 203 are Ta or Ti or W or TaN or TiN or WN, and said ultralow dielectric film 201 adopts the organic polymer spin coating proceeding or adopts based on SiO
2The CVD technology of material forms, and the dielectric constant of said ultralow dielectric film 201 is 2.2-2.8.
In step 2, shown in Fig. 2 b, on metal die 203, apply photoresist 204 and form the first etching window 204a through photoetching;
In step 3; Shown in Fig. 2 c; Metal die 203 in the etching first etching window 204a; Etch-stop is stayed metal die 203, removes photoresist 204 and in metal die 203, forms the second etching window 203a, and the said second etching window 203a is used at the window of subsequent step as etching groove;
In step 4, shown in Fig. 2 d, the ultralow dielectric thin protective film 202 in the etching second etching window 203a forms groove 205 with ultralow dielectric film 201.
In step 5, shown in Fig. 2 e, the inculating crystal layer of sputtering sedimentation metal barrier and copper in groove 205; Adopt electroplating technology to carry out copper and fill deposit, form metal level 206, shown in Fig. 2 f; Adopting cmp to remove metal level 206, metal die 203, ultralow dielectric thin protective film 202 and part ultralow dielectric film 201, form ground floor copper interconnection layer 207, is mask because the present invention adopts the metal dura mater; Improved the selection ratio of etching, compared and make with photoresist, reduced the thickness of photoresist as the situation of mask; Avoid narrowing down the possibility that high photoresist collapses along with live width; Avoid the groove top fillet to occur simultaneously, thereby reduce leakage current and then improve reliability.
The above is merely preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to the covering scope of claim of the present invention.
Claims (5)
1. the manufacture method of ground floor copper-connection may further comprise the steps:
On silicon chip, deposit ultralow dielectric film, ultralow dielectric thin protective film and metal die successively;
On the metal die, apply photoresist and form first etching window through photoetching;
Etching metal dura mater in first etching window, etching stopping is removed photoresist again on the ultralow dielectric thin protective film, in the metal dura mater, form second etching window, and said second etching window is used at the window of subsequent step as etching groove;
Ultralow dielectric thin protective film and ultralow dielectric film in etching second etching window form the groove that is communicated with silicon chip;
The inculating crystal layer of sputtering sedimentation metal barrier and copper in groove; Adopt electroplating technology to carry out copper and fill deposit; Remove metal die, ultralow dielectric thin protective film and part ultralow dielectric film through cmp, form the ground floor copper interconnection layer.
2. according to the manufacture method of the said ground floor copper-connection of claim 1, it is characterized in that: said ultralow dielectric thin protective film material is a silicon dioxide.
3. according to the manufacture method of the said ground floor copper-connection of claim 1, it is characterized in that: said ultralow dielectric film adopts the organic polymer spin coating proceeding or adopts based on SiO
2The CVD technology of material forms, and the dielectric constant of said ultralow dielectric film is 2.2-2.8.
4. according to the manufacture method of the said ground floor copper-connection of claim 1, it is characterized in that: the thickness of said ultralow dielectric film is
5. according to the manufacture method of the said ground floor copper-connection of claim 1, it is characterized in that: the material of said metal die is Ta or Ti or W or TaN or TiN or WN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110310442A CN102332427A (en) | 2011-10-13 | 2011-10-13 | Method for manufacturing first copper interconnection layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110310442A CN102332427A (en) | 2011-10-13 | 2011-10-13 | Method for manufacturing first copper interconnection layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102332427A true CN102332427A (en) | 2012-01-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110310442A Pending CN102332427A (en) | 2011-10-13 | 2011-10-13 | Method for manufacturing first copper interconnection layer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117316763A (en) * | 2023-09-12 | 2023-12-29 | 湖北江城实验室 | Semiconductor structure and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030087518A1 (en) * | 2001-11-08 | 2003-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for preventing photoresist poisoning |
| CN1419277A (en) * | 2001-11-13 | 2003-05-21 | 联华电子股份有限公司 | Method for manufacturing dual damascene plug by using metal hard mask layer |
| CN1732561A (en) * | 2000-09-18 | 2006-02-08 | Acm研究公司 | Integrating Metals and Ultra-Low-K Dielectrics |
| CN1933124A (en) * | 2005-09-14 | 2007-03-21 | 索尼株式会社 | Method of manufacturing semiconductor device |
| CN101295667A (en) * | 2007-04-24 | 2008-10-29 | 中芯国际集成电路制造(上海)有限公司 | Method for forming double mosaic structure |
-
2011
- 2011-10-13 CN CN201110310442A patent/CN102332427A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1732561A (en) * | 2000-09-18 | 2006-02-08 | Acm研究公司 | Integrating Metals and Ultra-Low-K Dielectrics |
| US20030087518A1 (en) * | 2001-11-08 | 2003-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for preventing photoresist poisoning |
| CN1419277A (en) * | 2001-11-13 | 2003-05-21 | 联华电子股份有限公司 | Method for manufacturing dual damascene plug by using metal hard mask layer |
| CN1933124A (en) * | 2005-09-14 | 2007-03-21 | 索尼株式会社 | Method of manufacturing semiconductor device |
| CN101295667A (en) * | 2007-04-24 | 2008-10-29 | 中芯国际集成电路制造(上海)有限公司 | Method for forming double mosaic structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117316763A (en) * | 2023-09-12 | 2023-12-29 | 湖北江城实验室 | Semiconductor structure and manufacturing method thereof |
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Application publication date: 20120125 |