CN102301606A - 对分布式天线系统中的信号进行数字均衡的方法和装置 - Google Patents
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Abstract
本发明提供对分布式天线系统中的信号进行数字均衡的系统和方法。在一个实施例中，分布式天线系统内的信号处理装置包括信号处理板内的信号路径，所述信号路径具有无补偿失真函数G(ω)，其中系统响应由y(n)表示；以及耦接至所述信号路径的补偿器，所述补偿器具有有限脉冲响应(FIR)滤波器，所述滤波器具有由H(ω)表示的脉冲响应函数，所述补偿器具有通过所述信号路径对梳状输入信号x(n)的估算系统响应y(n)来确定的FIR滤波器参数矢量，其中y(n)通过所述信号路径对多个扫频信号测试输入的内插式测量输出响应来估算。
Description
相关申请的交叉引用
本申请要求2009年1月27日提交的名称为"METHOD AND APPARATUS FOR DIGITALLY EQUALIZING A SIGNAL IN A DISTRIBUTED ANTENNA SYSTEM"的序列号为61/147,560的美国临时申请的权益，该申请据此以引用的方式并入本文。
本申请与2007年1月25日提交的名称为"MODULAR WIRELESS COMMUNICATIONS PLATFORM"的序列号为11/627,251的美国专利申请相关，该申请据此以引用的并入本文。
背景技术
分布式天线系统(DAS)是一种空间上分开的天线节点的网络，所述天线节点经由传输媒介连接至公共节点，该系统可在地理区域或结构内提供无线服务。公共无线通信系统的配置采用位于中央位置（例如，在无线服务提供商控制的设施中）的主机单元作为公共节点。位于远离主机单元位置（例如，在无线服务提供商不能控制的设施或场所中）的天线节点以及相关广播和接收设备也称为“远程单元”。射频(RF)信号在主机单元和一个或多个远程单元之间传送。在此类DAS中，主机单元通常通信地耦接至一个或多个基站（例如，经由有线连接或无线连接），所述基站可在DAS服务区内的无线用户单元和通信网络（诸如，但不限于移动电话网络、公共交换电话网络(PSTN)和因特网）之间提供双向通信。因此，DAS可从其本质上在社区内提供可将远程单元分散在整个地理区域内的基础设施，从而为该地区提供无线服务。
与具有模拟传输器的DAS相比，具有用于将下行链路传输信号和上行链路传输信号发送至主机单元和远程单元之间的数字传输器的DAS具有许多优点。然而，将下行链路RF信号和上行链路RF信号数字化可能会给RF信号带来不利的影响。
发明内容
本发明提供了对分布式天线系统中的信号进行数字均衡的系统和方法。在一个实施例中，分布式天线系统内的信号处理装置包括信号处理板内的信号路径，所述信号路径具有无补偿失真函数G(ω)，其中系统响应由y(n)表示；以及耦接至所述信号路径的补偿器，所述补偿器具有有限脉冲响应(FIR)滤波器，所述滤波器具有由H(ω)表示的脉冲响应函数，所述补偿器具有通过所述信号路径对梳状输入信号x(n)的估算系统响应y(n)来确定的FIR滤波器参数矢量 
，其中y(n)通过所述信号路径对多个扫频信号测试输入的内插式测量输出响应来估算。
附图说明
应理解附图仅描述本发明的示例性实施例而不应视为对本发明的范围进行限制，将使用附图并通过其它特征和细节来描述这些示例性实施例，其中：
图1为包括主机单元和多个远程单元的分布式天线系统(DAS)的一个实施例的框图；
图2为图1的远程单元的一个实施例的框图；
图3为图1的主机单元的一个实施例的框图；
图4示出了用于图2所示的主机单元或图3所示的远程单元的DART模块的一个实施例的示意图；
图5A为示出通过图1所示的DAS的信号路径失真的框图；
图5B为示出用于图4所示的DART模块的接收路径的测试系统的框图；
图5C为示出用于图4所示的DART模块的发送路径的测试系统的框图；
图6为确定滤波器响应的方法的框图；
图7提供了本发明的一个实施例的MATLAB代码，以及
图8为示出用于校准信号处理板的本发明的一个实施例的方法的流程图。
根据惯例，所述各种结构并未按比例绘制，而是绘制来突出与本发明的示例性实施例相关的特定结构。
具体实施方式
本公开涉及一种用于在传送的RF信号在数字化RF样本流和模拟RF信号之间转换时对RF信号进行均衡的方法和装置。对RF信号进行均衡，以使该RF信号的频率响应平稳。换言之，频带中给定频率上的RF信号的功率与该频带中其它频率上的RF信号的功率类似，以便在整个频带上实现（理论上）平坦响应。在一个实施例中，通过有限脉冲响应(FIR)滤波器对RF信号进行数字均衡。
图1为分布式天线系统(DAS) 100的一个实施例的框图。DAS 100包括主机单元102和多个远程单元106。在物理层上，主机单元102与远程单元106经由通信链路130通信地耦接，以形成包括多个点对点通信链路130的双向通信网络。在一个实施例中，一个或多个通信链路130为如图1所示的光纤电缆。任选地，主机单元102和远程单元106可经由同轴电缆或同轴电缆与光纤电缆的组合互连。此外，在其它实施例中，一个或多个通信链路130为无线毫米波链路（例如，E频带/70GHz无线电）。在此，毫米波信号收发器耦接至主机单元102和通信链路130每端上的每个远程单元106。在另一个实施例中，一个或多个通信链路130为微波无线电链路，其中微波无线电收发器耦接至主机单元102和远程单元106。
每个远程单元106容纳用于经由天线107来无线发送和接收调制射频(RF)通信的电子装置和系统，其中所述通信是与一个或多个移动用户单元108进行的。主机单元102耦接至至少一个基站收发台(BTS) 110，该基站收发台110通常称为基站。BTS 110经由网关124在各个主机单元102和较大的通信网络之间传送声音信号和其它数据信号，该网关124耦接至电话系统网络122（例如，公共交换电话网络和/或无线服务提供商网络）和互联网协议(IP)网络120（诸如，因特网）。在一个实施例中，DAS 100包括移动电话网络的一部分，且用户单元108为移动电话。
在主机单元102处从BTS 110接收下行链路RF信号，其中主机单元102用于生成一个或多个下行链路传输信号，以传送至一个或多个远程单元106。每个此类远程单元106容纳至少一个下行链路传输器，并通过下行链路传输信号重构下行链路RF信号，且使重构的下行链路RF信号从远程天线107中发射，远程天线107耦接至此远程单元106或包括在其中。在上行链路方向上进行类似的过程。在一个或多个远程单元106处从用户108接收的上行链路RF信号用于生成从各个远程单元106发送至主机单元102的各个上行链路传输信号。主机单元102接收并合并从多个远程单元106发送的上行链路传输信号。主机单元102通过宽带信号将合并的上行链路RF信号传送至BTS 110。
DAS 100包括DAS数字传输器，这意味着经由通信链路130在主机单元102和远程单元106之间发送的下行链路传输信号和上行链路传输信号是通过分别数字化下行链路RF信号和上行链路RF信号生成的。换言之，下行链路传输信号和上行链路传输信号不是模拟RF信号，而是表示调制RF信号的数字RF样本的数字数据信号。例如，如果旨在发送至用户单元108的特定通信信号为900MHz频带中的调制RF信号，则主机单元102将生成来自BTS 110的调制900MHz RF信号的基带数字样本，然后所述基带数字样本由主机单元102分配至远程单元106。或者，全数字化BTS也可直接生成基带数字样本。在远程单元处，将调制RF信号的数字样本从数字RF信号转换成模拟RF信号，以从天线107中进行无线发射。对在远程单元106处接收的上行链路模拟RF信号进行数字采样，以生成上行链路传输信号的数字RF数据样本。BTS 110、主机单元102和远程单元106每个均同时提供多个频带和多种调制方案的处理通信信号。
图2为远程单元106的一个实施例的框图。远程单元106包括串行射频(SeRF)模块220、数模射频收发器(DART)模块208、远程DART接口板(RDI) 224、线性功率放大器210、天线212、双工器211、低噪声放大器214。在一个实施例中，本文中描述的SeRF模块和DART模块通过FPGA、ASIC、数字信号处理(DSP)板或类似装置实现。
DART模块208为发送至主机单元102和远程单元106之间的下行链路传输信号和上行链路传输信号提供在模拟RF信号和数字采样RF信号之间的双向转换。在上行链路中，天线212从用户208接收无线RF信号，并经由低噪声放大器214将该RF信号传送至DART模块208。DART模块208接收进入的模拟RF信号，并对该模拟RF信号进行采样，以生成SeRF模块220使用的数字数据信号。在下行链路中，DART模块208从SeRF模块220接收数字采样RF数据，将该采样RF数据向上转换成广播频率，并将数字RF样本转换成模拟RF，以进行无线传输。在DART模块208将信号转换成模拟RF信号后，将该模拟RF信号发送至功率放大器210，以经由天线212进行广播。功率放大器210将从DART模块208接收的RF信号放大，以通过双工器211输出至天线212。双工器211提供信号的双工传输，这对将发送信号和接收信号连接至共用天线212十分必要。在一个实施例中，低噪声放大器214被集成于双工器211中。本领域的普通技术人员在阅读本说明书之后将理解，DART模块可用来任选地将数字RF样本转换成中频(IF)样本来替代或补充基带数字样本。
远程单元中的DART模块专用于特定频带。不管采用何种调制技术，单个DART模块在限定的FDD频带上运行。因此，可通过以覆盖不同频带的DART模块代替覆盖一个频带的DART模块来实现远程单元中的频带调整。例如，在一个实施例中，DART模块208被设计来发送850MHz蜂窝式传输。作为另一个实例，在另一个实施例中，DART模块208发送1900MHz PCS信号。DART模块208的一些其它选项包括Nextel 800频带、Nextel 900频带、PCS全频带、PCS半频带、BRS、WiMax、长期演进(LTE)以及欧洲GSM 900、GSM 1800和UMTS 2100。通过使不同种类的DART模块208插入RDI 224中，远程单元106可被配置成任何上述频带和技术以及所开发的任何新技术或频带。
SeRF模块220提供在数字数据流和高速串行光数据流之间的双向转换。在上行链路中，SeRF模块220从DART模块208接收进入的数字数据流，并通过通信链路130将串行光数据流发送至主机单元102。在下行链路中，SeRF模块202从主机单元102接收串行光数据流，并将数字数据流提供至DART模块208。
将SeRF模块220耦接至RDI 224。RDI 224具有多个连接器，其中每一个均被配置来接收可插式DART模块208，并将DART模块208耦接至SeRF模块220。RDI 224为公共接口，其被配置来使SeRF模块220和不同种类的DART模块208之间进行通信。在该实施例中，RDI 204是无源主机背板，SeRF模块220也连接至该背板。在另一实施例中，RDI 224不是主机背板，而是与SeRF模块220集成在一起。
尽管图2示出了单个耦接至SeRF模块的DART模块，但单个远程单元的外壳可通过处理多个DART模块在多个频带上运行。在一个此类实施例中，RDI 224提供单独的连接接口，以使每个DART模块均可通过SeRF模块220来传送RF数据样本。在此，SeRF模块220可使多个DART模块并行操作，以通过主机单元经由通信链路来传送高速串行光数据流。在一个此类实施例中，SeRF模块积极地多路传输多个DART模块（每个DART模块处理不同的RF频带）的信号，以便通过单个传输通信链路同时发送所述信号。在一个实施例中，SeRF模块向耦接有时钟信号的每个DART模块提供该时钟信号，以确保同步化。
此外，尽管图2示出了连接至单个RDI的单个SeRF模块，但本发明的实施例并不因此受到限制。在替代实施例中，SeRF模块可连接至多个RDI，其中每个RDI可连接至多个DART。例如，在一个实施例中，SeRF模块最多可连接至3个RDI，其中每个RDI最多可连接至2个DART。SeRF模块220提供在RF、IF或基带数据样本的串行数据流（SeRF数据流）和高速串行光数据流之间的双向转换。在上行链路方向上，SeRF模块220从DART模块208接收进入的SeRF数据流，并经由通信链路130将串行光数据流发送至主机单元102。在下行链路方向上，SeRF模块220从主机单元102接收串行光数据流，并向DART模块208提供SeRF数据流。尽管为了简单起见，本实例着重于单个DART模块的操作，但本讨论也适用于此类多个频带远程单元。
图3为示出主机单元（通常示为102）的一个实施例的框图。如图1所述，主机单元102经由通信链路130通信地耦接至多个远程单元106，以形成数字DAS。主机单元102包括主机单元数模射频收发器(DART)模块308和主机单元串行射频(SeRF)模块320。SeRF模块320提供至远程单元106的数字RF数据样本和多个高速串行光数据流之间以及自远程单元106的数字RF数据样本和多个高速串行光数据流之间的双向转换。在上行链路方向上，SeRF模块320从多个远程单元接收进入的串行光数据流，并将每个串行光数据流转换成数字化基带RF数据样本流，所述数字化基带RF数据样本流汇入RF数据样本宽带流。DART模块308在SeRF模块320和一个或多个基站（诸如，BTS 110）之间提供双向接口。如同远程单元106一样，当主机单元320通过多个基站在多个频带上运行时，将为每个频带提供单独的DART模块308。
图4为用于主机单元102（DART模块308）或远程单元106（DART模块208）的DART模块400的一个实施例的框图。DART模块400具有两个主信号路径：发送路径404和接收路径406。对于从SeRF模块接收的信号，如果需要，DART模块400在FPGA 403处由进入的数据流形成并行的数字RF数据。在该实施例中，FPGA 403为逻辑装置，其被编程来将串行数字数据转换成RF采样数据，并被编程来将RF采样数据转换成串行数字数据。DART模块400再使用数模转换器(DAC) 408将数字RF数据转换成模拟信号。随着DART模块400用一套滤波器410、放大器412、振荡器414和衰减器416来过滤、放大和向上转换模拟信号以进行RF传输，发送路径404继续运行。发送路径在超小型RF同轴连接器(SMA)连接器420处离开DART模块400。信号在相反的方向上沿着接收路径406前行，并在接收路径406上从模拟信号转换成数字信号，并被发送至SeRF模块。首先，在SMA连接器420处接收到信号。DART模块400随后使用多个滤波器410、放大器412、振荡器414和衰减器416来放大、向下转换和过滤进入的RF信号。DART模块400再使用模数转换器422使信号数字化。FPGA 403然后将数据流作为并行的数字RF采样数据提供至SeRF模块。共同待决的美国专利申请No. 11/627,251提供了关于DAS 100、主机单元102、远程单元106或DART模块400的更多详情，该申请据此以引用的方式并入本文。
随着串行数字数据和RF采样数据之间的转换，FPGA 403也通过使用滤波器来发送信号和接收信号来对经由DART模块400传送的信号进行数字均衡。在一个实施例中，采用了有限脉冲响应(FIR)滤波器，并将FIR滤波器响应设置为与DART模块400的倒频率响应高度相似。因此，FIR滤波器对DART模块400引起的信号失真进行补偿。在一个实施例中，FPGA 403使用滤波器来发送和接收DART模块400内的信号。通过使用滤波器来对DAC 408、带通滤波器(BPF) 410、放大器412和上变频器411引起的失真进行补偿来对发送信号进行预补偿。通过使用滤波器来对BPF 410、放大器412和下变频器413引起的失真进行补偿来对接收信号进行后补偿。在一个实施例中，滤波器试图将发送信号和接收信号设置为由DART模块400覆盖的整个频带上的单位增益。在一个实施例中，滤波器对整个35MHz频带上的信号进行均衡。
如上文中图1所述，DAS 100包括多个可插式和可拆式DART模块400。分别均衡每个DART模块400，以对由该特定的DART模块400引起的失真进行补偿。这可在对信号路径提供充分均衡的同时，使用其它任何DART模块400将任何DART模块400设置在信号路径中。因为通过DAS 100的给定信号路径穿过两个DART模块400（一个位于远程单元106内和一个位于主机单元102内）前行，且由于在DAS 100安装前，在给定信号路径上一个运行的特定DART模块400为未知，所以难以在安装前对特定信号路径中的特定失真进行补偿。因此，分别均衡DART模块400可使DART模块在安装之前均衡。此外，这可在对信号路径进行充分均衡的同时，使DART模块400插入在任何位置或由其它任何DART模块400代替。另外，分别均衡DART模块400可在DAS 100中进行多播/同播。因此，在给定的DAS信号路径中，均衡的一部分在主机单元DART模块208处完成，而另一部分在远程单元DART模块308处完成。这也适用于上行链路信号和下行链路信号。
图5A示出穿过DAS 100的RF信号路径500的一个实施例。将模拟RF信号502输入信号路径500。该模拟RF信号采用表面声波(SAW)滤波器（图4的BPF 410）过滤，向下转换（图4的下变频器413）并在转换成数字RF样本前再次过滤。这发生在DART模块400的接收路径406中。然而，这些步骤中的每一个均可引起RF信号失真（本文中称为G1(ω)）。然后，经由通信链路130传输该信号，该信号在通信链路130处转换成模拟信号，并经SAW过滤、向上转换（图4的上变频器411）和再次SAW过滤。这些步骤发生在另一个DART模块400的发送路径404中，并可引起RF信号失真（本文中称为G2(ω)失真）。
将每个DART模块400中的失真通过每个DART模块400中的FPGA 403进行均衡。每个DART模块400中的每个FPGA 403将滤波器（本文中称为H(ω)）用于信号。因此，G1(ω)失真由H1(ω)滤波器补偿，而G2(ω)失真由H2(ω)滤波器补偿。
图5B示出一种用于确定接收路径滤波器(H1(ω))的滤波器系数的方法。同样地，图5C示出一种用于确定发送路径滤波器(H2(ω))的滤波器系数的方法。为了确定滤波器的系数，将测试信号输入DART模块，并测量输出信号，以确定DART模块引起的失真。根据测量的输出信号，确定滤波器系数。然后设置滤波器系数，以便滤波器对DART模块引起的失真进行逆操作。
例如，为了确定DART模块400的H1(ω)滤波器系数，将信号发生器502的扫频测试信号施加至DART模块400的接收路径404。测试信号可采用任何适当的信号发生器来生成。对于初始测试顺序，FPGA 403采用滤波器的平坦响应。然后，采用频谱分析仪504来测量DART模块400的边缘连接器402处的输出信号，该输出信号由测试信号生成。为了确定H1(ω)，将模拟RF测试信号施加至接收路径404，并采用谱估计算法来分析边缘连接器402处的数字化信号输出，以确定系统的幅度响应。输入测试信号均以等幅输入，因而输出信号的幅度变化是DART模块400的接收路径404内的失真所致。然后设置滤波器系数，以便滤波器消除由DART模块400中的接收路径404所引起的失真。因此，后来输入接收路径404的信号会因接收路径404而失真，并经FPGA 403进行均衡，以便输出信号会具有（理论上）与相对于其它输入信号的输入信号的幅度具有相同的相对幅度（相对于其它输出信号的幅度）。除了将测试信号输入DART模块400的边缘连接器402并采用SMA连接器420处的频谱分析仪504进行测量所产生的输出信号外，以类似的方式确定DART模块400的H2(ω)滤波器系数。为了确定H2(ω)，将数字化信号施加至边缘连接器402处的发送路径，并采用RF频谱分析仪或RF检波器来测量SMA连接器420处的所产生的模拟RF输出信号，以确定信号幅度。在其它实施例中，采用RF检波器来测量输出信号。在一个实施例中，数字化信号生成于FPGA 403中，而非通过外部装置施加。用于确定H1(ω)和H2(ω)的输入测试信号称为扫频信号。
表1提供了分布式天线系统的部件（诸如，DART模块）的测量幅度响应的参数配置。
表1
通过对测量数据进行线性内插得到的总响应的近似值由以下等式来表示：
假定系统相位响应大致恒定，则由一系列等幅正弦信号（其均匀地间隔在整个数字频谱上）组成的频梳测试信号便可确定反向FIR滤波器，以均衡系统的幅度响应。表2描述了频梳信号与系统响应输出的近似值
之间的关系。通过逼近总系统响应Ge(ω)将频梳信号
施加至所描述的系统模型，其中总系统响应Ge(ω)基于采用扫频信号得到的该幅度的K个测量值的内插。频梳的目的仅用于计算，并由C个音调组成，其中C个音调通常会大于数量K。在一个实施例中，在计算机中生成频梳信号
，并存于其中，以计算H(ω)（其可能为H1(ω)或H2(ω)）的估值。
表2：输入和输出频梳测试信号。
图6示出用于确定FIR滤波器H(ω)的信号模型（通常示为600），其中FIR滤波器H(ω)可估算线性信道响应的倒数。根据最小二乘拟合来确定FIR滤波器H(ω)，从而可得到FIR滤波器的参数，该FIR滤波器会均衡具有线性失真的信道G(ω)。图6中，d(n)表示所需的系统响应。在一个实施例中，d(n)为延迟型输入。为由信道失真G(ω)和近似系统反向滤波器H(ω)的级联导致所得的均衡的系统响应。
H(ω)的最小二乘计算将所需响应和均衡响应之间的误差e(n)平方减至最小。Monson H. Hayes在Statistical Digital Signal Processing and Modeling (New York, Chichester, Brisbane, Toronto, Singapore: John Wiley & Sons, 1996)的第166页提供了图6中描述的最小二乘拟合法的其它信息。
假定为
设置N个抽头的FIR滤波器，则误差项
可采用信道输出
和所需信道输出
表示为：
(2)
其中
为卷积运算。取
和
的M个连续样本，并设置
；在确定的线性等式中，等式(2)可以矩阵形式表示为一组 M+N-1：
或简写为：
(4)
其中
为信道输出样本的卷积矩阵，
为FIR滤波器参数的矢量（FIR滤波器的单位脉冲响应），并且
为所需的信道输出样本的矢量（延迟型输入）。可采用最小二乘法得到等式的最优解，最小二乘法可将误差项的平方和降至最小。最小二乘解可通过求解该组线性方程得到。
或者
图7提供了可用于进行反向滤波器的最小二乘估计的MATLAB代码（通常示为700）。下面的表3汇总了其中用于导出反向FIR滤波器的计算结果。
表3
因此，对于导出的FIR滤波器
（其系数由
表示），系统（即，DART模块）的逆信道误差响应将为
。
在一个实施例中，将滤波器系数储存于DART模块400的存储器424中。一旦确定了上面所述的系数，则将所述系数储存于存储器424中，并在FPGA 403将滤波器施加至信号时经FPGA 403存取。因为每个DART模块400均具有失真度不同的两个信号路径（发送和接收），所以每个信号路径均具有其自己的系数集（存于存储器424中）。因此，当FPGA 403处理发送路径的信号时，FPGA 403会存取发送路径的滤波器系数，并将具有这些系数的滤波器施加至发送路径信号。同样地，当FPGA 403处理接收路径信号时，FPGA 403会存取接收路径的滤波器系数，并将具有所述系数的滤波器施加至接收路径信号。
在一个实施例中，在DART模块400制造后，在工厂中对DART模块400进行均衡。在此，在工厂中信号发生器将信号输入DART模块400，且频谱分析仪分析输出信号。为了进一步分析输出信号，采用缓冲器来收集输出信号。然后，采用快速傅里叶变换(FFT)将输出信号转换成频域。一旦每个频率的输出信号功率处于该频域中，则易于确定该功率。
一旦在工厂中确定了滤波器的系数，则将所述系数储存于存储器424中。将存储器424与FPGA 403隔开，使得所述系数在无需将其集成于FPGA 403的情况下便可储存于存储器424中。因此，可单独对FPGA 403进行编程或随后按要求编程为具有更为通用的功能。这样，在无需分别进行FPGA编程的情况下，可分别处理每个DART模块400的滤波器响应。
在另一实施例中，DART模块400包括自校准模块426。自校准模块426进行上述所列的步骤，以生成测试信号，并分析输出信号，来确定DART模块400的适当的滤波器系数。可对自校准模块426进行编程，以定期校准DART模块400，或者在（例如）将DART模块400调至不同的频带时，可手动启动自校准模块426。
图8为示出用于校准信号处理板（诸如，DART模块）的本发明的一个实施例的方法的流程图。该方法始于810：将补偿器设置在信号处理板的第一信号路径中，以使信号处理板的整个第一通带具有平坦响应。第一信号路径可包括部件，诸如，但不限于，数模转换器(DAC)、模数转换器(ADC)、SAW滤波器以及频率上变频器和频率下变频器。该方法进行至820：将多个测试信号施加至信号处理板的输入上，所述多个测试信号按频率间隔在整个第一通带上。在一个实施例中，多个测试信号包括多个扫频信号，所述多个扫频信号由一系列等幅正弦信号（其均匀地间隔在整个第一通带的数字频谱上）组成。该方法进行至830：根据信号处理板的输出来确定多个测试信号中每一个的增益值。该方法进行至840：根据多个测试信号中每一个的增益值来估算信号处理板的系统响应函数y(n)。在一个实施例中，如先前表1中所定义，通过将扫频信号施加至物理系统中来测量幅度增益值Gm(n)。因为存在K个此类测量值和两个终点，所以n指范围为0至K+1的下标变量。因此，此扫频实际上可在整个信道带中进行全程扫频步骤。上述等式(1)中所定义的Ge(ω)表示系统幅度响应的估值，其为样本单位中标准频率的函数。即，Ge(ω)为Gm(n)和测量Gm(n)的相应频率Fm(n)的内插值。表2中所定义的G(m)表示在频梳测试信号x(n)中含有的音调的C个频率中的每一个处采样的C个Ge(ω)样本。因为存在C个样本，所以m指范围可为0至C-1的下标。因此函数y(n)为估算的系统输出，其可被生成用于输入频梳测试信号x(n)和系统响应的近似值Ge(ω)。该方法进行至850：根据矢量d(n)和卷积h(n)*y(n)之间的差值来求解矢量h(n)的系数，其中d(n)表示系统响应函数y(n)的延迟输入。换言之，其为延迟型频梳测试信号x(n)。在一个实施例中，确定矢量h(n)，以便将d(n)和h(n)*y(n)之间的均方误差相对于h(n)减至最小。
该方法进行至850：根据矢量d(n)和卷积h(n)*y(n)之间的差值来求解矢量h(n)的系数，其中d(n)表示系统响应函数y(n)的延迟输入。在一个实施例中，矢量d(n)和卷积h(n)*y(n)之间的差值为零。该方法进行至860：根据矢量h(n)系数将有限脉冲响应(FIR)滤波器的系数设置在补偿器中。
虽然本文已经示出并描述了具体实施例，但是本领域的普通技术人员应认识到，旨在用于实现相同目的的任何布置可代替所示的具体实施例。本公开旨在涵盖对本发明所做的任何修改或变更。因此，显然其意图是本发明仅受权利要求及其等效形式所限制。
Claims (20)
1. 一种位于分布式天线系统中的信号处理装置，所述信号处理装置包括：
信号处理板内的信号路径，所述信号路径具有无补偿失真函数G(ω)，其中系统响应由y(n)表示；以及
耦接至所述信号路径的补偿器，所述补偿器具有有限脉冲响应(FIR)滤波器，所述滤波器具有由H(ω)表示的脉冲响应函数，所述补偿器具有通过所述信号路径对梳状输入信号x(n)的估算系统响应y(n)来确定的FIR滤波器参数矢量 ，其中y(n)通过所述信号路径对多个扫频信号测试输入的内插式测量输出响应来估算。
2. 根据权利要求1所述的信号处理装置，其中所述FIR滤波器参数矢量由以下等式经计算来确定：
其中，
为表示信道的卷积矩阵。
3. 根据权利要求1所述的信号处理装置，进一步包括存储器，其中所述矢量
的系数储存在所述存储器中。
4. 根据权利要求1所述的信号处理装置，其中所述补偿器采用现场可编程门阵列(FPGA)来实现。
5. 根据权利要求1所述的信号处理装置，其中所述信号处理板的信号路径包括数模转换器(DAC)和至少一个频率上变频器。
6. 根据权利要求1所述的信号处理装置，其中所述信号处理板的信号路径包括模数转换器(ADC)和至少一个频率下变频器。
7. 根据权利要求1所述的信号处理装置，其进一步包括自校准模块，其用于根据所述自校准模块生成的测试信号来计算所述FIR滤波器参数矢量
的系数。
8. 根据权利要求7所述的信号处理装置，其中所述自校准模块根据所述多个扫频信号测试输入通过根据矢量d(n)和卷积h(n)*y(n)之间的差值来求解矢量h(n)的系数来估算所述信号处理板的系统响应函数y(n)，其中d(n)表示所述系统响应函数y(n)的延迟输入；并且
其中，所述自校准模块根据所述矢量h(n)的系数来调节所述有限脉冲响应(FIR)滤波器。
9. 一种用于校准信号处理板的方法，所述方法包括：
将补偿器设置在信号处理板的第一信号路径中，以使所述信号处理板的整个第一通带具有平坦响应；
将多个测试信号施加至所述信号处理板的输入上，所述多个测试信号按频率间隔在整个所述第一通带上；
根据所述信号处理板的输出来确定所述多个测试信号中每一个的增益值；
根据所述多个测试信号中每一个的增益值来估算所述信号处理板的系统响应函数y(n)；
根据矢量d(n)和卷积h(n)*y(n)之间的差值来求解矢量h(n)的系数，其中d(n)表示系统响应函数y(n)的延迟输入；以及
根据所述矢量h(n)的系数将有限脉冲响应(FIR)滤波器的系数设置在所述补偿器中。
10. 根据权利要求9所述的方法，其中确定所述矢量h(n)，以便将所述d(n)和卷积h(n)*y(n)之间的均方误差相对于h(n)减至最小。
11. 根据权利要求9所述的方法，其中所述信号处理板的第一信号路径包括数模转换器(DAC)和至少一个频率上变频器。
12. 根据权利要求9所述的方法，其中所述信号处理板的第一信号路径包括模数转换器(ADC)和至少一个频率下变频器。
13. 根据权利要求9所述的方法，其中根据所述矢量h(n)的系数将所述有限脉冲响应(FIR)滤波器的系数设置在所述补偿器中的步骤进一步包括将所述有限脉冲响应(FIR)滤波器的所述系数储存在存储器中。
14. 根据权利要求13所述的方法，其中所述存储器位于所述补偿器外部。
15. 根据权利要求9所述的方法，其中施加所述多个测试信号的步骤进一步包括：
通过位于所述信号处理板上的自校准模块生成所述测试信号。
16. 根据权利要求9所述的方法，其中求解矢量h(n)的系数的步骤进一步包括：
通过位于所述信号处理板上的自校准模块来确定所述矢量h(n)的系数。
17. 一种位于分布式天线系统中的信号处理装置，所述信号处理装置包括：
信号处理板内的信号路径，所述信号路径具有无补偿失真函数G(ω)；以及
耦接至所述信号路径的补偿器，所述补偿器具有有限脉冲响应(FIR)滤波器，所述滤波器具有由矢量
表示的脉冲响应函数并具有基于关系的矢量
的滤波器系数h(n)，其中
为表示所述信号路径的延迟输入的矢量，且为所述信号路径对梳状信号的估算响应的卷积矩阵，所述估算响应基于所述信号路径对多个扫频信号测试输入的内插式测量输出响应。
18. 根据权利要求17所述的信号处理装置，进一步包括存储器，其中将所述矢量
的滤波器系数h(n)储存在所述存储器中。
19. 根据权利要求17所述的信号处理装置，进一步包括自校准模块，其用于根据由所述自校准模块生成的扫频信号来计算所述矢量
的滤波器系数h(n)。
20. 根据权利要求17所述的信号处理装置，其中所述信号处理板的信号路径包括数模转换器(DAC)、频率上变频器、模数转换器(ADC)或频率下变频器中的至少一个。
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| JP2012516635A (ja) | 2012-07-19 |
| AU2009338702A1 (en) | 2011-08-18 |
| KR20110107820A (ko) | 2011-10-04 |
| US20100189170A1 (en) | 2010-07-29 |
| KR101355501B1 (ko) | 2014-01-28 |
| US20120163431A1 (en) | 2012-06-28 |
| US8437383B2 (en) | 2013-05-07 |
| WO2010087919A3 (en) | 2010-09-16 |
| WO2010087919A2 (en) | 2010-08-05 |
| CN102301606B (zh) | 2014-08-27 |
| EP2392075A4 (en) | 2013-08-07 |
| US8135102B2 (en) | 2012-03-13 |
| AU2009338702B2 (en) | 2013-07-18 |
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