CN102288896A - Method for testing port characteristics of high-speed communication bus chip - Google Patents
Method for testing port characteristics of high-speed communication bus chip Download PDFInfo
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- CN102288896A CN102288896A CN2011101271026A CN201110127102A CN102288896A CN 102288896 A CN102288896 A CN 102288896A CN 2011101271026 A CN2011101271026 A CN 2011101271026A CN 201110127102 A CN201110127102 A CN 201110127102A CN 102288896 A CN102288896 A CN 102288896A
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- speed communication
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Abstract
The invention discloses a method for testing port characteristics of a high-speed communication bus chip. The method comprises the following steps of: controlling a high-speed switch connected with a source line to be conducted to ensure that the source line is connected with a test machine; transmitting a differential signal to the high-speed communication bus chip by the test machine, and starting the high-speed communication bus chip to run; controlling the high-speed switch connected with the source line to be disconnected before a feedback signal generated by the high-speed communication bus chip is transmitted to the test machine along the source line so that the source line is disconnected with the test machine; controlling a high-speed switch connected with a capture line to be conducted to ensure that the capture line is connected with the test machine; transmitting a differential signal to the test machine by the high-speed communication bus chip; and controlling the high-speed switch connected with the capture line to be disconnected before a feedback signal generated by the high-speed communication bus chip is transmitted to the test machine along the capture line so that the capture line is disconnected with the test machine.
Description
Technical field
The present invention relates to the chip testing field, relate in particular to a kind of high-speed communication bus chip port identity method of testing.
Background technology
When whether the test bus chip performance adheres to specification, all to test each passage of bus chip.For the high-speed communication bus chip, each channel transfer all be differential signal, promptly each passage of high-speed communication bus chip all comprises two access ports.For the high-speed communication bus chip that has reception and emission function simultaneously, each access port of each passage both can receive the signal that external transmission is come, can transmit to the outside again, test has the performance of the high-speed communication bus chip of reception and emission function, need test the performance of received signal and the performance that transmits respectively.
When testing the performance of high-speed communication bus chip with reception and emission function, each access port of each passage is all drawn a root line and is caught line and be connected with test machine with one, described source line is used to receive the signal that external transmission is come, and the described line of catching is used for transmitting to the outside.Figure 1 shows that the synoptic diagram of test high-speed communication bus chip performance in the prior art, only demonstrate a passage of high-speed communication bus chip 100 to be measured among Fig. 1, two access ports of this passage are respectively first passage port A+ and second channel port A-, draw the first source line 110 and first from described first passage port A+ and catch line 120, draw the second source line 130 and second from described second channel port A-and catch line 140, the described first source line 110, first is caught line 120, the second source line 130 and second is caught line 140 and is connected with test machine 200 respectively.When testing the performance of described high-speed communication bus chip 100 received signals to be measured, described test machine 200 by the described first source line 110 and the second source line 130 to described high-speed communication bus chip 100 differential signal transmissions to be measured, start the logic function of described high-speed communication bus chip to be measured 100 inside, described test machine 200 judges by detecting the logic function operational factor whether the performance of described high-speed communication bus chip 100 to be measured adheres to specification; When testing the performance that described high-speed communication bus chip 100 to be measured transmits, described high-speed communication bus chip 100 to be measured is caught line 120 and second by described first and is caught line 140 to described test machine 200 emission differential signals, and described test machine 200 judges by the differential signal that detects described high-speed communication bus chip to be measured 100 emissions whether the performance of described high-speed communication bus chip 100 to be measured adheres to specification.
No matter be that described test machine 200 is to described high-speed communication bus chip 100 differential signal transmissions to be measured, still described high-speed communication bus chip 100 to be measured is to described test machine 200 emission differential signals, described high-speed communication bus chip 100 to be measured all can produce feedback signal, this feedback signal transfers to described test machine 200, test is produced interference, cause described test machine 200 to test, even damage described test machine 200.
Summary of the invention
The object of the present invention is to provide a kind of high-speed communication bus chip port identity method of testing, can avoid the interference of feedback signal, accurately the high-speed communication bus chip is tested test.
To achieve the above object, the invention provides a kind of high-speed communication bus chip port identity method of testing, the source line that each access port of high-speed communication bus chip is drawn with catch line and all be connected with test machine by speed-sensitive switch, this method may further comprise the steps: the speed-sensitive switch conducting that control is connected with described source line makes described source line be connected with described test machine; Described test machine starts described high-speed communication bus chip operation by the described high-speed communication bus chip of described source alignment differential signal transmission; Before the feedback signal that described high-speed communication bus chip produces transferred to described test machine along described source line, the speed-sensitive switch that control is connected with described source line disconnected, and described source line is disconnected with described test machine be connected; Control is caught the speed-sensitive switch conducting that line is connected with described, and the described line of catching is connected with described test machine; Described high-speed communication bus chip is by the described described test machine emission of the alignment differential signal of catching; Catch before line transfers to described test machine along described in feedback signal that described high-speed communication bus chip produces, control is caught the speed-sensitive switch disconnection that line is connected with described, and the described line of catching is connected with described test machine disconnection.
Above-mentioned high-speed communication bus chip port identity method of testing, wherein, described access port is the simulating signal port.
Above-mentioned high-speed communication bus chip port identity method of testing, wherein, described test machine is an analog difference signal by the described high-speed communication bus chip of described source alignment differential signal transmission, and to catch the described test machine of alignment emission differential signal be analog difference signal to described high-speed communication bus chip by described.
Above-mentioned high-speed communication bus chip port identity method of testing, wherein, the control cycle of described speed-sensitive switch is a nanosecond.
Above-mentioned high-speed communication bus chip port identity method of testing, wherein, described speed-sensitive switch was obtained by test adjustment from the time interval that conducting state switches between the off-state.
High-speed communication bus chip port identity method of testing of the present invention is by speed-sensitive switch Controlling Source line and catch line and the break-make of test machine, when the needs differential signal transmission, conducting source line or catch being connected between line and the test machine, before the feedback signal transmission, cut-out source line or catch being connected between line and the test machine, avoided the interference of feedback signal, can accurately test the high-speed communication bus chip to test.
Description of drawings
High-speed communication bus chip port identity method of testing of the present invention is provided by following embodiment and accompanying drawing.
Fig. 1 is the synoptic diagram of test high-speed communication bus chip performance in the prior art.
Fig. 2 is the synoptic diagram of test high-speed communication bus chip performance among the present invention.
Embodiment
Below with reference to Fig. 2 high-speed communication bus chip port identity method of testing of the present invention is described in further detail.
High-speed communication bus chip port identity method of testing of the present invention, the source line that each access port of high-speed communication bus chip is drawn with catch line and all be connected with test machine by speed-sensitive switch, this method may further comprise the steps:
The speed-sensitive switch conducting that control is connected with described source line makes described source line be connected with described test machine; Described test machine starts described high-speed communication bus chip operation by the described high-speed communication bus chip of described source alignment differential signal transmission; Before the feedback signal that described high-speed communication bus chip produces transferred to described test machine along described source line, the speed-sensitive switch that control is connected with described source line disconnected, and described source line is disconnected with described test machine be connected;
Control is caught the speed-sensitive switch conducting that line is connected with described, and the described line of catching is connected with described test machine; Described high-speed communication bus chip is by the described described test machine emission of the alignment differential signal of catching; Catch before line transfers to described test machine along described in feedback signal that described high-speed communication bus chip produces, control is caught the speed-sensitive switch disconnection that line is connected with described, and the described line of catching is connected with described test machine disconnection.
High-speed communication bus chip port identity method of testing of the present invention is by speed-sensitive switch Controlling Source line and catch line and the break-make of test machine, when the needs differential signal transmission, conducting source line or catch being connected between line and the test machine, before the feedback signal transmission, cut-out source line or catch being connected between line and the test machine, avoided the interference of feedback signal, can accurately test the high-speed communication bus chip to test.
Now describe high-speed communication bus chip port identity method of testing of the present invention in detail with a specific embodiment:
In the present embodiment, the differential signal that transmits between each passage of high-speed communication bus chip to be measured and the outside is a simulating signal, and mainly handle digital signal the inside of high-speed communication bus chip to be measured, therefore, after high-speed communication bus chip to be measured receives the next analog difference signal of external transmission, earlier convert analog difference signal to digital signal, handle again, when high-speed communication bus chip to be measured need outwards transmit, high-speed communication bus chip to be measured converts digital signal to simulating signal earlier, again to external emission;
In the present embodiment, only a passage to high-speed communication bus chip to be measured describes, and other passages of high-speed communication bus chip to be measured adopt identical method.
Referring to Fig. 2, a passage of high-speed communication bus chip 300 to be measured comprises the first analog signal channel port B+ and the second analog signal channel port B-, draw the first simulation signal generator line 310 and first simulating signal is caught line 320 from the described first analog signal channel port B+, draw the second simulation signal generator line 330 and second simulating signal is caught line 340 from the described second analog signal channel port B-, the described first simulation signal generator line 310 and the second simulation signal generator line 330 are used to receive the analog difference signal that external transmission is come, and described first simulating signal is caught line 320 and second simulating signal and caught line 340 and be used for to outside launching simulation differential signal;
The described first simulation signal generator line 310 all is connected with first speed-sensitive switch 410 with the second simulation signal generator line 330, described first speed-sensitive switch 410 is connected with test machine 500, and the promptly described first simulation signal generator line 310 is connected with described test machine 500 by described first speed-sensitive switch 410 with the second simulation signal generator line 330; Described first simulating signal is caught line 320 and is caught line 340 with second simulating signal and all be connected with second speed-sensitive switch 420, described second speed-sensitive switch 420 is connected with described test machine 500, and promptly described first simulating signal is caught line 320 and caught line 340 with second simulating signal and be connected with described test machine 500 by described second speed-sensitive switch 420;
In the present embodiment, adopt the break-make of described first speed-sensitive switch, the 410 described first simulation signal generator lines 310 of control and the second simulation signal generator line 330 and described test machine 500, adopt described first simulating signal of described second speed-sensitive switch 420 control to catch the break-make that line 320 and second simulating signal are caught line 340 and described test machine 500, but, adopt speed-sensitive switch Controlling Source line and the method for catching line and test machine break-make to be not limited thereto, for example, use four speed-sensitive switches, the described first simulation signal generator line 310, the second simulation signal generator line 330, first simulating signal is caught line 320 and is caught line 340 with second simulating signal and be connected a speed-sensitive switch respectively, it is the described first simulation signal generator line 310, the second simulation signal generator line 330, first simulating signal is caught line 320 and is caught line 340 with second simulating signal and be connected with described test machine 500 by a speed-sensitive switch respectively, satisfy being connected and controlling break-make by speed-sensitive switch between every root line and the test machine, catch being connected between line and the test machine for every and can all can adopt by the method that speed-sensitive switch is controlled break-make;
The control end 411 of described first speed-sensitive switch 410 and the control end 421 of second speed-sensitive switch 420 are connected with control device (not showing among Fig. 2), are controlled the break-make of described first speed-sensitive switch 410 and second speed-sensitive switch 420 by described control device;
During test, described test machine 500 both can send analog difference signals to described high-speed communication bus chip 300 to be measured as external unit, also can receive the analog difference signal of described high-speed communication bus chip to be measured 300 emissions;
When testing the performance of described high-speed communication bus chip 300 received signals to be measured, described control device is controlled 410 conductings of described first speed-sensitive switch, make the described first simulation signal generator line 310 all be connected (being conducting) with described test machine 500 with the second simulation signal generator line 330, described test machine 500 sends analog difference signal by the described first simulation signal generator line 310 and the second simulation signal generator line 330 to described high-speed communication bus chip 300 to be measured, thereby start described high-speed communication bus chip to be measured 300 operations, after getting up, described high-speed communication bus chip to be measured 300 operations can produce feedback signal, this feedback signal can transfer to described test machine 500 along the described first simulation signal generator line 310 and the second simulation signal generator line 330, test is produced interference, the present invention is before this feedback signal transfers to described test machine 500, cut off being connected between the described first simulation signal generator line 310 and the second simulation signal generator line 330 and the described test machine 500 (be described control device control described first speed-sensitive switch 410 disconnect), make this feedback signal can't transfer to described test machine 500, therefore, the interference of feedback signal to testing that the present invention has avoided described high-speed communication bus chip to be measured 300 to produce normally carried out test; Described first speed-sensitive switch 410 can be obtained by test adjustment from the time interval that conducting state switches between the off-state;
When testing the performance that described high-speed communication bus chip 300 to be measured transmits, described high-speed communication bus chip 300 to be measured is in running status, described control device is controlled 420 conductings of described second speed-sensitive switch, making described first simulating signal catch line 320 catches line 340 with second simulating signal and all is connected (being conducting) with described test machine 500, described high-speed communication bus chip 300 to be measured catches line 320 by described first simulating signal and second simulating signal is caught line 340 to described test machine 500 launching simulation differential signals, because the characteristics on described high-speed communication bus chip 300 functions to be measured, described high-speed communication bus chip 300 to be measured can produce feedback signal behind described test machine 500 launching simulation differential signals, this feedback signal also can be caught line 320 and second simulating signal along described first simulating signal and be caught line 340 and transfer to described test machine 500, test is produced interference, the present invention is before this feedback signal transfers to described test machine 500, cutting off described first simulating signal catches line 320 and second simulating signal and catches being connected between line 340 and the described test machine 500 (be described control device control described second speed-sensitive switch 420 disconnect), make this feedback signal can't transfer to described test machine 500, therefore, the interference of feedback signal to testing that the present invention has avoided described high-speed communication bus chip to be measured 300 to produce normally carried out test; Described second speed-sensitive switch 420 can be obtained by test adjustment from the time interval that conducting state switches between the off-state.
In the present embodiment, the control cycle of described first speed-sensitive switch 410 and described second speed-sensitive switch 420 can reach nanosecond.
Claims (5)
1. high-speed communication bus chip port identity method of testing, the source line that each access port of high-speed communication bus chip is drawn with catch line and all be connected with test machine by speed-sensitive switch, it is characterized in that this method may further comprise the steps:
The speed-sensitive switch conducting that control is connected with described source line makes described source line be connected with described test machine; Described test machine starts described high-speed communication bus chip operation by the described high-speed communication bus chip of described source alignment differential signal transmission; Before the feedback signal that described high-speed communication bus chip produces transferred to described test machine along described source line, the speed-sensitive switch that control is connected with described source line disconnected, and described source line is disconnected with described test machine be connected;
Control is caught the speed-sensitive switch conducting that line is connected with described, and the described line of catching is connected with described test machine; Described high-speed communication bus chip is by the described described test machine emission of the alignment differential signal of catching; Catch before line transfers to described test machine along described in feedback signal that described high-speed communication bus chip produces, control is caught the speed-sensitive switch disconnection that line is connected with described, and the described line of catching is connected with described test machine disconnection.
2. high-speed communication bus chip port identity method of testing as claimed in claim 1 is characterized in that described access port is the simulating signal port.
3. high-speed communication bus chip port identity method of testing as claimed in claim 2, it is characterized in that, described test machine is an analog difference signal by the described high-speed communication bus chip of described source alignment differential signal transmission, and to catch the described test machine of alignment emission differential signal be analog difference signal to described high-speed communication bus chip by described.
4. high-speed communication bus chip port identity method of testing as claimed in claim 1 is characterized in that the control cycle of described speed-sensitive switch is a nanosecond.
5. high-speed communication bus chip port identity method of testing as claimed in claim 1 is characterized in that, described speed-sensitive switch was obtained by test adjustment from the time interval that conducting state switches between the off-state.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011101271026A CN102288896A (en) | 2011-05-17 | 2011-05-17 | Method for testing port characteristics of high-speed communication bus chip |
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| CN2011101271026A CN102288896A (en) | 2011-05-17 | 2011-05-17 | Method for testing port characteristics of high-speed communication bus chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106546833A (en) * | 2015-09-16 | 2017-03-29 | 中国电力科学研究院 | A kind of electric energy meter RS-485 communication chip networking test systems |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3787810A (en) * | 1972-11-02 | 1974-01-22 | Burroughs Corp | Test method for a programmable data communication terminal |
| CN1211737A (en) * | 1997-08-26 | 1999-03-24 | 三星电子株式会社 | Integrated circuit chip tester and testing method thereof |
| CN1682203A (en) * | 2002-08-01 | 2005-10-12 | 泰瑞达公司 | Flexible Interface for Universal Bus Testers |
| CN1888990A (en) * | 2006-07-12 | 2007-01-03 | 北京和利时系统工程股份有限公司 | Programmable controller back plate communicating method |
| CN101047404A (en) * | 2006-03-31 | 2007-10-03 | 鸿富锦精密工业（深圳）有限公司 | High speed signal transmission structure |
| CN101136003A (en) * | 2006-09-01 | 2008-03-05 | 鸿富锦精密工业（深圳）有限公司 | High-speed differential signaling architecture |
| CN101789778A (en) * | 2009-12-29 | 2010-07-28 | 北京大学 | Low power consumption and high anti-interference radio frequency switch |
-
2011
- 2011-05-17 CN CN2011101271026A patent/CN102288896A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3787810A (en) * | 1972-11-02 | 1974-01-22 | Burroughs Corp | Test method for a programmable data communication terminal |
| CN1211737A (en) * | 1997-08-26 | 1999-03-24 | 三星电子株式会社 | Integrated circuit chip tester and testing method thereof |
| CN1682203A (en) * | 2002-08-01 | 2005-10-12 | 泰瑞达公司 | Flexible Interface for Universal Bus Testers |
| CN101047404A (en) * | 2006-03-31 | 2007-10-03 | 鸿富锦精密工业（深圳）有限公司 | High speed signal transmission structure |
| CN1888990A (en) * | 2006-07-12 | 2007-01-03 | 北京和利时系统工程股份有限公司 | Programmable controller back plate communicating method |
| CN101136003A (en) * | 2006-09-01 | 2008-03-05 | 鸿富锦精密工业（深圳）有限公司 | High-speed differential signaling architecture |
| CN101789778A (en) * | 2009-12-29 | 2010-07-28 | 北京大学 | Low power consumption and high anti-interference radio frequency switch |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106546833A (en) * | 2015-09-16 | 2017-03-29 | 中国电力科学研究院 | A kind of electric energy meter RS-485 communication chip networking test systems |
| CN106546833B (en) * | 2015-09-16 | 2018-10-09 | 中国电力科学研究院 | A kind of electric energy meter RS-485 communication chip networkings test system |
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Application publication date: 20111221 |