[go: up one dir, main page]

CN102099911A - 使用预模制载体的嵌入式裸片封装及工艺流程 - Google Patents

使用预模制载体的嵌入式裸片封装及工艺流程 Download PDF

Info

Publication number
CN102099911A
CN102099911A CN2009801277269A CN200980127726A CN102099911A CN 102099911 A CN102099911 A CN 102099911A CN 2009801277269 A CN2009801277269 A CN 2009801277269A CN 200980127726 A CN200980127726 A CN 200980127726A CN 102099911 A CN102099911 A CN 102099911A
Authority
CN
China
Prior art keywords
forming
electrical device
metal conductors
solder bumps
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2009801277269A
Other languages
English (en)
Inventor
卢克·英格兰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Publication of CN102099911A publication Critical patent/CN102099911A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/211—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明提供一种嵌入式裸片封装，其包括：载体，其具有在所述载体的腔中的电装置；第一电介质层，其覆盖所述电装置的侧及顶部，除所述电装置的选定接合垫上方的导通孔外；多个金属导体，其中的每一者与所述导通孔中的至少一者接触；一个或一个以上额外电介质层，其位于所述金属导体及所述第一电介质层上方，其中所述一个或一个以上电介质层的顶部层具有开口，其中下方的金属化物耦合到所述金属导体中的至少一者；及焊料凸块，其从所述开口中的每一者突出。

Description

使用预模制载体的嵌入式裸片封装及工艺流程
相关申请案交叉参考
本申请案请求对2008年7月17日提出申请的第12/175,171号美国专利申请案的优先权。
技术领域
本发明涉及用于所模制电装置或多个电装置的封装。
背景技术
在过去的电装置中，通常通过首先将装置安装于引线框上且然后制作到外部引线的连接且然后囊封来封装(例如)半导体裸片。然而，随着电装置的小型化已发展，已开发且仍正在开发新封装技术，用于通过例如将多个裸片放到一封装中且使用具有薄模制覆盖物的焊料凸块互连的方法来缩小经封装半导体装置。
尽管焊料凸块及薄模制提供小封装，但半导体裸片脆弱且通常必须以充足刚性来封装以保护裸片并密封裸片。另一限制为封装方法，为对于商业市场在经济上可行，其需要具有通用性，以使得其可与不同装置大小及几何形状一同使用且仍提供具有匹配行业中的实际标准的占地面积的封装。
发明内容
在其一个形式上，本发明包含一种形成嵌入式封装的方法。所述方法包含以下步骤：形成具有第一多个腔的载体；将电装置置于所述第一多个腔中的每一者中；在所述电装置中的每一者周围及上方且在所述载体的上部表面上方形成第一电介质层；形成穿过所述电介质层到达所述电装置中的每一者上的选定接合垫的导通孔；及形成第二多个金属导体，其中的每一者与所述导通孔中的一者接触且远离那些导通孔延伸一距离。所述方法还包括：在所述第二多个金属导体中的每一者及所述第一电介质层的暴露部分上方形成一个或一个以上额外电介质层；在金属导体上方于所述一个或一个以上额外电介质层中的一者中形成开口；形成第三多个焊料凸块，其中的每一者耦合到所述第二多个金属导体中的一者；及将所述第一多个腔单个化。
在另一形式上，本发明包含一种嵌入式裸片封装，其包括：预模制载体，其具有在所述载体的第一腔中的第一电装置；第一电介质层，其覆盖所述第一电装置的侧及顶部，除所述电装置的选定接合垫上方的导通孔外；第一多个金属导体，其中的每一者与所述导通孔中的至少一者接触；一个或一个以上额外电介质层，其位于所述金属导体及所述第一电介质层上方，其中所述一个或一个以上电介质层的顶部层在所述金属导体中的每一者的一部分上方具有开口；及第二多个焊料凸块，其从所述开口中的每一者突出。
在又一形式上，本发明包含一种除所述预模制载体为扁平水平表面而非具有腔的预模制载体外的以以上形式描述的嵌入式裸片封装。
附图说明
通过结合附图阅读以下更详细说明，将更好地理解前述及其它特征、特性、优点及本发明大体内容，附图中：
图1A是根据本发明的实施例的预模制载体的图表式横截面图；
图1B是图1A中所示的预模制载体在两个半导体裸片已被裸片附接于所述预模制载体的两个腔中之后的图表式横截面图；
图1C是图1B中所示的预模制载体在第一电介质层已形成之后的图表式横截面图；
图1D是图1C中所示的预模制载体在金属互连件已形成之后的图表式横截面图；
图1E是图1D中所示的预模制载体在第二电介质层已形成之后的图表式横截面图；
图1F是图1E中所示的预模制载体在焊料凸块已形成之后的图表式横截面图；
图2A及2B显示根据本发明的实施例的经封装半导体裸片的相应俯视透视图及仰视透视图；
图3A、3B、3C、3D、3E及3F显示根据本发明的实施例的在形成嵌入式裸片封装时的各个阶段；及
图4、5及6是显示可实践本发明的实施例中的一些实施例的图表式横截面图。
应了解，出于清晰的目的且在认为适当时，已在图中重复参考编号以指示对应的特征。此外，在某些情况下，已使图式中各种物体的相对大小偏离现实以更清楚地显示本发明。
具体实施方式
图1A是从囊封材料(例如，环氧树脂模制化合物)形成的预模制载体20的图表式横截面图。图1中所示的载体20具有两个腔22及24，腔22、24具有用于腔22的外部侧壁26及用于腔24的外部侧壁28。较厚中心壁30将两个腔22、24分离，腔22、24表示预模制载体上的两个邻近封装地点。腔22、24具有基底32。
图1B显示在两个半导体裸片34及36已分别裸片附接于腔22及24中之后的预模制载体20。在图1B中，半导体裸片34及36在预模制载体20的侧壁26、28及中心壁30上面延伸。半导体裸片34及36中的每一者具有接合垫38。可用标准裸片附接方法(例如但不限于环氧树脂或裸片附接膜40)来进行裸片附接。在图1C中，电介质材料42填充半导体裸片34及36、侧壁26、28及中心壁30之间的空隙，且在上面及半导体裸片34及36的顶部延伸。已穿过电介质材料42制作到接合垫38的导通孔44。
电介质材料42可以若干已知方法中的任一种形成，所述方法包括：使用用例如味之素累积膜(ABF)等材料的真空膜层压工艺后接对导通孔44的激光钻孔。还可通过旋涂或喷涂聚酰亚胺或光致抗蚀剂随后进行光刻来形成导通孔44。
沉积、图案化并蚀刻金属化物以形成从接合垫38到不直接在半导体裸片22及24上方的位置的金属互连件48，如图1D中所示。在本发明的一个实施例中，通过首先经由无电极Cu镀敷或Cu喷溅沉积用薄金属种子层涂覆电介质层42的表面及暴露的接合垫38、放下经图案化光致抗蚀剂层且在所述薄金属层的暴露区域中电镀额外金属来形成金属化物。然后移除所述光致抗蚀剂且使用酸性蚀刻移除所述金属种子层。在本发明的另一实施例中，通过A1喷溅沉积来将所述金属互连件形成为所需最终互连件厚度。然后沉积光致抗蚀剂层且将其图案化以匹配互连布线。蚀刻掉所述Al金属，随后进行光致抗蚀剂移除，此留下最终的互连图案。
参照图1E，在形成金属互连件48之后，接着在第一层级电介质材料42及金属互连件48上方施加并图案化第二电介质层52。此电介质层52施加工艺可匹配第一电介质层42施加工艺。
在图1F中，已使用若干已知工艺中的一种形成了焊料凸块56，所述工艺例如但不限于模板印刷或球滴(ball drop)后接回流循环。依据互连金属成分，可需要可软焊的凸块下金属化物(UBM)层。此可通过无电极镀敷方法实现。通过两个封装的单个化来完成嵌入式裸片封装58的形成。
图2A及2B显示根据本发明的实施例的经封装半导体裸片64的相应俯视透视图60及仰视透视图62。这些图中所示的封装具有预模制载体66，第二电介质层68具有突出穿过的焊料凸块56。
图3A到3F显示根据本发明的实施例的形成嵌入式裸片封装70中的各个阶段。图3A显示预模制载体72，其具有九个腔74的矩阵。半导体裸片76被置于六个腔74中的每一者中，如图3B中所示。
图3C显示在第一电介质层80已形成于裸片76上方、导通孔已形成于第一电介质层80中且金属导体82已形成于接合垫78及将放置焊料凸块56的地点84中的每一者之间之后的嵌入式裸片封装。然后，在第一电介质层80及金属导体82上方形成第二电介质层86，且在第二电介质层86中制作开口88以暴露用于焊料凸块56的地点84，如图3D中所示。
图3E显示焊料凸块56位于地点84上，且图3F显示在单个化工艺之后的个别裸片封装70。
图4、5及6显示可实践本发明的实施例中的一些实施例。在图4中，半导体裸片34在腔22中，腔22邻近含有无源电元件92(例如，电感器、电阻器或电容器)的深得多的腔90。半导体裸片34可具有约20μm的高度且电元件92可具有1mm的高度，但每一者的高度可随应用要求而变换。另外，半导体裸片34与电元件92的宽度可不同，如图4中所示。因此，预模制载体94经形成以适应半导体裸片34及电元件92的高度及宽度。
图5是根据本发明的另一实施例的预模制载体的图表式横截面图，其中在两个半导体裸片34与36之间制作有互连金属化物。可使用一般PC板或重分布层技术在不同垂直层级处制作互连件。在图5中，金属互连件96位于第一电介质层42与可比图1E中所示的第二电介质层52厚的第二电介质层94之间。金属互连件96将作为嵌入式裸片封装98(其为多芯片封装)的部分的半导体裸片34及36的接合垫38连接在一起。金属互连件100形成从接合垫102到位于第二电介质层94上的金属互连件104的连接，金属互连件104延伸到金属互连件96。另一金属互连件106形成从接合垫108到位于第二电介质层94上的第二金属互连件110的连接。第三电介质层112覆盖金属互连件104及110以及第二电介质层94的暴露区。图5中还显示，焊料凸块56延伸穿过第三电介质层112中的开口，到达金属互连件104及110。
在图6中，预模制载体114不具有侧壁26、28或中心壁30，而是具有扁平水平表面。上文关于图1A到1F所描述的工艺仍适用于形成图6中所示的实施例。在不使用接合垫38的应用中，嵌入式裸片封装中可不存在到接合垫的金属互连件，其实例显示于图6中。
尽管已参考特定实施例描述了本发明，但所属领域的技术人员应理解，可在不背离本发明范围的情况下做出各种改变且可用等效物代替元件。另外，为适应特定情况或材料可在不背离本发明的范围的情况下对本发明的教示做出许多修改。
因此，本文并非打算将本发明限于所揭示的作为实施本发明的最好设想模式的特定实施例，而是本发明将包括属于所附权利要求书的范围及精神内的所有实施例。

Claims (20)

1.一种形成嵌入式封装的方法，其包含以下步骤：
a)形成具有第一多个腔的载体；
b)将电装置置于所述第一多个腔中的每一者中；
c)在所述电装置中的每一者周围及上方且在所述载体的上部表面上方形成第一电介质层；
d)形成穿过所述电介质层到达所述电装置中的每一者上的选定接合垫的导通孔；
e)形成第二多个金属导体，其中的每一者与所述导通孔中的一者接触且远离所述导通孔中的所述一者延伸一距离；
f)在所述第二多个金属导体中的每一者及所述第一电介质层的暴露部分上方形成一个或一个以上额外电介质层；
g)在金属导体上方于所述一个或一个以上额外电介质层中的一者中形成开口；
h)形成第三多个焊料凸块，其中的每一者耦合到所述第二多个金属导体中的一者；及
i)将所述第一多个腔单个化。
2.根据权利要求1所述的方法，其中通过模制工艺形成所述载体。
3.根据权利要求1所述的方法，其包括将所述电装置附接到所述载体的额外步骤。
4.根据权利要求1所述的方法，其中将所述焊料凸块中的至少一者置于在所述电装置的横向周界外部的位置中。
5.根据权利要求1所述的方法，其中将所述焊料凸块中的至少一者置于在所述电装置的所述横向周界内部的位置中。
6.根据权利要求1所述的方法，其中所述单个化步骤产生含有两个或两个以上腔的嵌入式封装，所述两个或两个以上腔中的每一者含有电装置。
7.根据权利要求1所述的方法，其中穿过所述开口中的至少一者形成所述焊料凸块中的至少一者，从而形成到所述第二多个金属导体中的一者的电连接。
8.一种形成嵌入式封装的方法，其包含以下步骤：
a)形成具有第一多个腔的预模制载体；
b)将电装置置于所述第一多个腔中的每一者中；
c)在所述电装置中的每一者周围及上方且在所述载体的上部表面上方形成第一电介质层；
d)形成穿过所述电介质层到达所述电装置中的每一者上的选定接合垫的导通孔；
e)形成第二多个金属导体，其中的每一者与所述导通孔中的一者接触且远离所述导通孔中的所述一者延伸一距离；
f)在所述第二多个金属导体中的每一者及所述第一电介质层的暴露部分上方形成一个或一个以上额外电介质层；
g)在金属导体上方于所述一个或一个以上额外电介质层中的一者中形成开口；
h)形成第三多个焊料凸块，其中的每一者耦合到所述第二多个金属导体中的一者；及
i)将所述第一多个腔单个化；
j)其中将所述焊料凸块中的至少一者置于在所述电装置的横向周界内部的位置中，且穿过所述开口中的至少一者形成所述焊料凸块中的至少一者，从而形成到所述第二多个金属导体中的一者的电连接。
9.根据权利要求1或权利要求8所述的方法，其中所述电装置为无源装置。
10.根据权利要求1或权利要求8所述的方法，其中通过层压工艺形成所述第一电介质层。
11.根据权利要求1或权利要求10所述的方法，其中通过激光钻孔形成所述导通孔。
12.根据权利要求1或权利要求10所述的方法，其中通过光刻形成所述导通孔。
13.一种嵌入式裸片封装，其包含：
a)预模制载体，其具有在所述载体的第一腔中的第一电装置；
b)第一电介质层，其覆盖所述第一电装置的侧及顶部，除所述电装置的选定接合垫上方的导通孔外；
c)第一多个金属导体，其中的每一者与所述导通孔中的至少一者接触；
d)一个或一个以上额外电介质层，其位于所述金属导体及所述第一电介质层上方，其中所述一个或一个以上电介质层的顶部层具有开口，其中下方的金属化物耦合到所述第一多个金属导体中的至少一者；及
e)第二多个焊料凸块，其从所述开口中的每一者突出。
14.根据权利要求13所述的封装，其中所述焊料凸块中的至少一者置于在所述电装置的横向周界外部的位置中。
15.根据权利要求13所述的封装，其中所述焊料凸块中的至少一者置于在所述电装置的所述横向周界内部的位置中。
16.根据权利要求13所述的封装，其中单个化步骤产生含有两个或两个以上腔的嵌入式封装，所述两个或两个以上腔中的每一者含有电装置。
17.根据权利要求13所述的封装，其进一步包括形成第四多个金属导体的步骤，所述第四多个金属导体中的每一者耦合到所述第二多个金属导体中的至少一者。
18.根据权利要求13所述的封装，其中所述焊料凸块中的至少一者经形成而穿过所述开口中的至少一者，从而形成到所述第一多个金属导体中的一者的电连接。
19.一种嵌入式裸片封装，其包含：
a)预模制载体，其具有在所述载体的第一腔中的第一电装置；
b)第一电介质层，其覆盖所述第一电装置的侧及顶部，除所述电装置的选定接合垫上方的导通孔外；
c)第一多个金属导体，其中的每一者与所述导通孔中的至少一者接触；
d)一个或一个以上额外电介质层，其位于所述第一多个金属导体及所述第一电介质层上方，其中所述一个或一个以上电介质层的顶部层具有开口，其中下方的金属化物耦合到所述第一多个金属导体中的至少一者；及
e)第二多个焊料凸块，其从所述开口中的每一者突出；
f)其中所述焊料凸块中的至少一者位于所述电装置的横向周界的内部，且所述焊料凸块中的至少一者形成到所述第二多个金属导体中的一者的直接电连接。
20.根据权利要求13或权利要求19所述的封装，其中所述电装置为无源装置。
CN2009801277269A 2008-07-17 2009-05-29 使用预模制载体的嵌入式裸片封装及工艺流程 Pending CN102099911A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/175,171 US7863096B2 (en) 2008-07-17 2008-07-17 Embedded die package and process flow using a pre-molded carrier
US12/175,171 2008-07-17
PCT/US2009/045582 WO2010008689A2 (en) 2008-07-17 2009-05-29 Embedded die package and process flow using a pre-molded carrier

Publications (1)

Publication Number Publication Date
CN102099911A true CN102099911A (zh) 2011-06-15

Family

ID=41529573

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009801277269A Pending CN102099911A (zh) 2008-07-17 2009-05-29 使用预模制载体的嵌入式裸片封装及工艺流程

Country Status (6)

Country Link
US (2) US7863096B2 (zh)
KR (2) KR101056245B1 (zh)
CN (1) CN102099911A (zh)
DE (1) DE112009001746T5 (zh)
TW (1) TWI413194B (zh)
WO (1) WO2010008689A2 (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106024738A (zh) * 2015-03-30 2016-10-12 意法半导体公司 具有倾斜侧壁的半导体器件及相关方法
CN106158773A (zh) * 2014-11-07 2016-11-23 日月光半导体制造股份有限公司 具有嵌入组件的半导体封装及其制造方法
CN106876356A (zh) * 2017-03-09 2017-06-20 华天科技（昆山）电子有限公司 芯片嵌入硅基式扇出型封装结构及其制作方法
CN107078133A (zh) * 2015-04-29 2017-08-18 德卡技术股份有限公司 用于全模制封装的3d互连部件
CN107731787A (zh) * 2016-08-11 2018-02-23 日月光半导体制造股份有限公司 包含高密度互连的半导体装置封装和堆叠封装组合件
US10079156B2 (en) 2014-11-07 2018-09-18 Advanced Semiconductor Engineering, Inc. Semiconductor package including dielectric layers defining via holes extending to component pads
CN112204719A (zh) * 2018-03-29 2021-01-08 维斯普瑞公司 晶圆级制造具有平面网格阵列接口的设备的系统和方法
US12205881B2 (en) 2022-12-23 2025-01-21 Deca Technologies Usa, Inc. Semiconductor assembly comprising a 3D block and method of making the same

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9875911B2 (en) 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
US8143097B2 (en) * 2009-09-23 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
US8294276B1 (en) * 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8598695B2 (en) 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
US8247269B1 (en) 2011-06-29 2012-08-21 Fairchild Semiconductor Corporation Wafer level embedded and stacked die power system-in-package packages
KR101264735B1 (ko) * 2011-08-03 2013-05-15 하나 마이크론(주) 반도체 패키지 및 이의 제조 방법
US8586408B2 (en) * 2011-11-08 2013-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Contact and method of formation
US9111949B2 (en) * 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US8741691B2 (en) 2012-04-20 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating three dimensional integrated circuit
TWI469294B (zh) * 2012-07-11 2015-01-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US9209081B2 (en) * 2013-02-21 2015-12-08 Freescale Semiconductor, Inc. Semiconductor grid array package
US9642259B2 (en) 2013-10-30 2017-05-02 Qualcomm Incorporated Embedded bridge structure in a substrate
US9379041B2 (en) * 2013-12-11 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fan out package structure
US9824989B2 (en) 2014-01-17 2017-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package and methods of forming thereof
US9034694B1 (en) 2014-02-27 2015-05-19 Freescale Semiconductor, Inc. Embedded die ball grid array package
US9355997B2 (en) * 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9165793B1 (en) 2014-05-02 2015-10-20 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US9252127B1 (en) 2014-07-10 2016-02-02 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
JP6314731B2 (ja) * 2014-08-01 2018-04-25 株式会社ソシオネクスト 半導体装置及び半導体装置の製造方法
US9653438B2 (en) 2014-08-21 2017-05-16 General Electric Company Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof
TWI557853B (zh) * 2014-11-12 2016-11-11 矽品精密工業股份有限公司 半導體封裝件及其製法
KR101631406B1 (ko) 2015-02-09 2016-06-17 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
TWI606555B (zh) 2015-05-15 2017-11-21 尼克森微電子股份有限公司 晶片封裝結構及其製造方法
US10373922B2 (en) 2015-06-04 2019-08-06 Micron Technology, Inc. Methods of manufacturing a multi-device package
US9478504B1 (en) 2015-06-19 2016-10-25 Invensas Corporation Microelectronic assemblies with cavities, and methods of fabrication
US20170053832A1 (en) * 2015-08-20 2017-02-23 Beijing Acuti Microsystems Co., Ltd. Wafer structure and processing method thereof
US10147645B2 (en) * 2015-09-22 2018-12-04 Nxp Usa, Inc. Wafer level chip scale package with encapsulant
US10083888B2 (en) * 2015-11-19 2018-09-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package
JP6716363B2 (ja) 2016-06-28 2020-07-01 株式会社アムコー・テクノロジー・ジャパン 半導体パッケージ及びその製造方法
KR102566996B1 (ko) 2016-09-09 2023-08-14 삼성전자주식회사 FOWLP 형태의 반도체 패키지 및 이를 가지는 PoP 형태의 반도체 패키지
US9966361B1 (en) * 2016-11-04 2018-05-08 General Electric Company Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
US10700035B2 (en) 2016-11-04 2020-06-30 General Electric Company Stacked electronics package and method of manufacturing thereof
US10312194B2 (en) 2016-11-04 2019-06-04 General Electric Company Stacked electronics package and method of manufacturing thereof
US9966371B1 (en) 2016-11-04 2018-05-08 General Electric Company Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
KR20180112463A (ko) 2017-04-04 2018-10-12 에스케이하이닉스 주식회사 팬 아웃 웨이퍼 레벨 패키지 제조 방법
TWI658520B (zh) * 2017-07-07 2019-05-01 恆勁科技股份有限公司 以大板面製程製作晶粒凸塊結構之方法
US10497648B2 (en) 2018-04-03 2019-12-03 General Electric Company Embedded electronics package with multi-thickness interconnect structure and method of making same
US10741534B2 (en) * 2018-09-28 2020-08-11 Intel Corporation Multi-die microelectronic device with integral heat spreader
JP6621951B1 (ja) * 2018-12-28 2019-12-18 長瀬産業株式会社 半導体装置の製造方法
US10985101B2 (en) * 2019-03-14 2021-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
KR102741560B1 (ko) 2019-10-22 2024-12-12 삼성전자주식회사 반도체 패키지
US11532563B2 (en) * 2020-09-21 2022-12-20 Apple Inc. Package integration using fanout cavity substrate
US11810895B2 (en) * 2021-10-14 2023-11-07 Honeywell Federal Manufacturing & Technologies, Llc Electrical interconnect structure using metal bridges to interconnect die
TWI859729B (zh) * 2023-02-14 2024-10-21 矽品精密工業股份有限公司 電子封裝件及其製法
US20250096164A1 (en) * 2023-09-15 2025-03-20 Qualcomm Technologies, Inc. Die package with guard structure to reduce or prevent material seepage into air cavity, and related fabrication methods

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040214373A1 (en) * 2003-04-22 2004-10-28 Tongbi Jiang Packaged microelectronic devices and methods for packaging microelectronic devices
CN1624888A (zh) * 2003-12-03 2005-06-08 育霈科技股份有限公司 扩散式晶圆型态封装的结构与其形成方法
US6919508B2 (en) * 2002-11-08 2005-07-19 Flipchip International, Llc Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing
US7208344B2 (en) * 2004-03-31 2007-04-24 Aptos Corporation Wafer level mounting frame for ball grid array packaging, and method of making and using the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1350296A (en) * 1919-08-20 1920-08-24 Willard J Cook Manure-spreader
JP3521758B2 (ja) * 1997-10-28 2004-04-19 セイコーエプソン株式会社 半導体装置の製造方法
KR100266637B1 (ko) 1997-11-15 2000-09-15 김영환 적층형볼그리드어레이반도체패키지및그의제조방법
US6979594B1 (en) 2002-07-19 2005-12-27 Asat Ltd. Process for manufacturing ball grid array package
TWI246761B (en) 2003-05-14 2006-01-01 Siliconware Precision Industries Co Ltd Semiconductor package with build-up layers formed on chip and fabrication method of the semiconductor package
US7235431B2 (en) 2004-09-02 2007-06-26 Micron Technology, Inc. Methods for packaging a plurality of semiconductor dice using a flowable dielectric material
KR100598275B1 (ko) 2004-09-15 2006-07-10 삼성전기주식회사 수동소자 내장형 인쇄회로기판 및 그 제조 방법
KR20080048311A (ko) * 2006-11-28 2008-06-02 삼성전자주식회사 반도체 패키지 및 그 제조방법
US7759777B2 (en) 2007-04-16 2010-07-20 Infineon Technologies Ag Semiconductor module

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6919508B2 (en) * 2002-11-08 2005-07-19 Flipchip International, Llc Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing
US20040214373A1 (en) * 2003-04-22 2004-10-28 Tongbi Jiang Packaged microelectronic devices and methods for packaging microelectronic devices
CN1624888A (zh) * 2003-12-03 2005-06-08 育霈科技股份有限公司 扩散式晶圆型态封装的结构与其形成方法
US7208344B2 (en) * 2004-03-31 2007-04-24 Aptos Corporation Wafer level mounting frame for ball grid array packaging, and method of making and using the same

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106158773A (zh) * 2014-11-07 2016-11-23 日月光半导体制造股份有限公司 具有嵌入组件的半导体封装及其制造方法
US10079156B2 (en) 2014-11-07 2018-09-18 Advanced Semiconductor Engineering, Inc. Semiconductor package including dielectric layers defining via holes extending to component pads
CN106158773B (zh) * 2014-11-07 2018-12-14 日月光半导体制造股份有限公司 具有嵌入组件的半导体封装及其制造方法
CN106024738A (zh) * 2015-03-30 2016-10-12 意法半导体公司 具有倾斜侧壁的半导体器件及相关方法
CN107078133A (zh) * 2015-04-29 2017-08-18 德卡技术股份有限公司 用于全模制封装的3d互连部件
CN107078133B (zh) * 2015-04-29 2021-10-15 美国德卡科技公司 制备用于全模制封装的3d互连部件的方法
CN107731787A (zh) * 2016-08-11 2018-02-23 日月光半导体制造股份有限公司 包含高密度互连的半导体装置封装和堆叠封装组合件
CN106876356A (zh) * 2017-03-09 2017-06-20 华天科技（昆山）电子有限公司 芯片嵌入硅基式扇出型封装结构及其制作方法
CN106876356B (zh) * 2017-03-09 2020-04-17 华天科技（昆山）电子有限公司 芯片嵌入硅基式扇出型封装结构及其制作方法
CN112204719A (zh) * 2018-03-29 2021-01-08 维斯普瑞公司 晶圆级制造具有平面网格阵列接口的设备的系统和方法
US12205881B2 (en) 2022-12-23 2025-01-21 Deca Technologies Usa, Inc. Semiconductor assembly comprising a 3D block and method of making the same
US12469776B2 (en) 2022-12-23 2025-11-11 Deca Technologies Usa, Inc. Semiconductor assembly comprising a 3D block and method of making the same

Also Published As

Publication number Publication date
TW201005838A (en) 2010-02-01
US8304896B2 (en) 2012-11-06
WO2010008689A3 (en) 2010-03-04
KR101159016B1 (ko) 2012-06-21
KR20110017011A (ko) 2011-02-18
KR20110020951A (ko) 2011-03-03
WO2010008689A2 (en) 2010-01-21
US20110068461A1 (en) 2011-03-24
TWI413194B (zh) 2013-10-21
US20100013087A1 (en) 2010-01-21
US7863096B2 (en) 2011-01-04
DE112009001746T5 (de) 2011-06-16
KR101056245B1 (ko) 2011-08-11

Similar Documents

Publication Publication Date Title
US7863096B2 (en) Embedded die package and process flow using a pre-molded carrier
KR101496085B1 (ko) 인터포저 프레임을 이용한 패키징
US10079200B2 (en) Packaging devices and methods
US7242081B1 (en) Stacked package structure
US10068853B2 (en) Integrated fan-out package and method of fabricating the same
CN109560061B (zh) 集成扇出型封装体及其制造方法
US20130037929A1 (en) Stackable wafer level packages and related methods
US20160189983A1 (en) Method and structure for fan-out wafer level packaging
US20120286408A1 (en) Wafer level package with thermal pad for higher power dissipation
US20140353836A1 (en) Chip arrangements and a method for manufacturing a chip arrangement
US10297552B2 (en) Semiconductor device with embedded semiconductor die and substrate-to-substrate interconnects
TWI471991B (zh) 半導體封裝
CN106328624B (zh) 制造具有多层囊封的传导基板的半导体封装的方法及结构
US9871011B2 (en) Semiconductor package using a contact in a pleated sidewall encapsulant opening
CN113725198B (zh) 半导体封装
US20180204816A1 (en) Packaging through Pre-Formed Metal Pins
CN104409369A (zh) 封装组件制造方法
CN107658273A (zh) 半导体装置及制造方法
US20240371825A1 (en) Semiconductor package and method for making the same
KR102727515B1 (ko) 반도체 패키지 기판 및 그 제조방법, 반도체 패키지
KR101579434B1 (ko) 반도체 패키지 제조 방법
CN119812169A (zh) 半导体封装件及其制造方法
KR20240178189A (ko) 반도체 패키지 및 그 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20110615