CN102037371A - Enhancement of detection of defects on display panels using front lighting - Google Patents

Abstract

Front-side illumination apparatus and methods are provided to enable, in general, detection of a-Si residue defects at the array test step well before the cell step. A-Si has high resistivity without exposure to light making it difficult to detect in conventional TFT-array test procedures. On the other hand, when the a-Si residue is illuminated with a light, its resistivity decreases, which, in turn, changes the electrical properties of the TFT array cell, which may be detected using the voltage imaging optical system (VIOS). In one implementation, the TFT array cell is exposed to illuminating light pulses, impacting the top side of the TFT panel during the testing performed using the VIOS. In one implementation, the front side illumination is traveling along the same path as the illumination used for voltage imaging in the VIOS. In another implementation, light source(s) for front side illumination are located in the close proximity to the VIOS modulator.

Description

Enhanced Defect Detection of Display Panels Using Front Side Illumination

Cross References to Related Applications

This application is based on and claims the benefit of priority under 35 U.S.C. 119 of U.S. Provisional Patent Application No. 61/055,031 filed May 21, 2008, the entire disclosure of which is hereby incorporated by reference.

technical field

The present invention relates to detecting defects in flat panel displays, and more particularly, to detecting defects in flat panel displays using front side illumination.

Background technique

In the manufacture of flat-panel liquid crystal (LC) displays, large clear and thin glass plates are used as substrates for depositing arrays of thin-film transistors (TFTs). Typically, several independent TFT arrays are contained within one glass substrate plate, and are often referred to as TFT panels. Alternatively, Active Matrix LCD (or AMLCD) encompasses such displays that utilize transistors or diodes at each pixel or sub-pixel, so such glass substrate panels may also be referred to as AMLCD panels. Flat panel displays can also be fabricated using organic LED (OLED) technology and, although typically fabricated on glass, can also be fabricated on plastic substrates.

TFT pattern deposition is performed in multiple stages, where in each stage a specific material (e.g. metal, indium tin oxide (ITO) is deposited on top of the previous layer (or glass) in a predetermined pattern. ), crystalline silicon, amorphous silicon, etc.). Each stage typically includes multiple steps such as deposition, masking, etching, lift-off, and the like.

During each of these stages and in the various steps within each stage, a number of production defects can occur which will affect the electrical and/or optical properties of the final LCD product. These defects include, but are not limited to, metal protrusions 110 in ITO 112, ITO protrusions 114 in metal 116, so-called mouse bites 118, opens 120, shorts 122 in transistors 124, foreign particles 126, and pixels The lower residue 128 is shown in FIG. 1 . Amorphous silicon (a-Si) residue 128 under the pixel may be caused by under-etching or lithography problems. Other defects include masking issues, over etching, etc.

Although the TFT deposition process is strictly controlled, the occurrence of defects cannot be avoided. This limits throughput and adversely affects production costs. Typically, after the critical deposition process steps, one or more automated optical inspection (AOI) systems are used to inspect the TFT array, and an electro-optical inspection machine (such as Photon by 5970 Optical Court, San Jose, California 95138, USA) is used to inspect the TFT array. Dynamics company (Orbotech company), also known as array tester or array checker (array checker; AC)) to test the completed TFT array.

The a-Si defect is a particularly troublesome defect because it is sensitive to light; that is, a-Si behaves as an insulator in the dark state, but behaves as a conductor when it is exposed to light. In fact, its sheet resistance R _Si decreases as a function of light intensity. Figure 4 illustrates this dependency. The dependence of the sheet resistance on light intensity thus means that with varying exposure to light, changes in pixel voltage due to defects can also be varied. Therefore, if a defect is not detected before final FPD assembly is complete, it will be easily noticed by the end user since it is exposed to the backlight of the display during normal FPD operation. Therefore, there is a strong incentive to detect such defects.

Unfortunately, conventional techniques have failed to provide a suitable method for effectively detecting defect-forming a-Si residues on LCD panels during various stages of panel fabrication.

Contents of the invention

The methods of the present invention are directed to methods and systems that substantially eliminate one or more of the above-mentioned and other problems associated with the detection of defect-forming a-Si residues in LCD panel displays.

According to one aspect of the present invention, a system for detecting defects in a panel under test is provided. The system incorporates a front illumination subsystem configured to deliver a front illumination beam onto the panel under test. The frontside illuminating beam has the ability to alter the electrical properties of the defects to facilitate detection of the defects. The system also incorporates a detection subsystem configured to detect defects based on the changed electrical characteristics of the defects. The frontside illumination beam used in the system is pulsed and its duration and intensity optimized to maximize detection of defects and minimize detection of spurious defects. In addition, the frontside illuminating beam has a wavelength that matches the maximum absorption optical property of the defect.

According to another aspect of the invention, a system for detecting defects in a panel under test is provided. The system incorporates a front illumination subsystem configured to deliver a front illumination beam onto the panel under test. The frontside illuminating beam has the ability to alter the electrical properties of the defect to facilitate detection of the defect. The system also incorporates a detection subsystem configured to detect defects based on the changed electrical characteristics of the defects. The aforementioned detection subsystem includes voltage imaging optics configured to create an image indicative of a spatial voltage distribution of the panel under test. Defects in the tested panel are detected based on the created image. In this system, the front side illumination subsystem is integrated within the optical path of the voltage imaging optics. In addition, the frontside illuminating beam has a wavelength that matches the maximum absorption optical property of the defect.

According to another aspect of the invention, a system for detecting defects in a panel under test is provided. The system incorporates a front illumination subsystem configured to deliver a front illumination beam onto the panel under test. The front side illuminating beam has the ability to change the electrical properties of the defect to facilitate detection of the defect. The system also incorporates a detection subsystem configured to detect defects based on the changed electrical characteristics of the defects. The aforementioned detection subsystem includes voltage imaging optics configured to create an image indicative of the spatial voltage distribution of the tested panel. Defects in the tested panel are detected based on the created image. The aforementioned front side illumination subsystem is arranged outside the optical path of the voltage imaging optics. In addition, the frontside illuminating beam has a wavelength that matches the maximum absorption optical property of the defect.

Additional aspects related to the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention. Aspects of the invention may be realized and obtained by means of the elements and combinations of various elements and aspects particularly pointed out in the hereinafter detailed description and claims.

It should be understood that the foregoing and following descriptions are illustrative and explanatory only, and are not intended to limit the claimed invention or its application in any way.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain and explain the principles of the inventive technology. in particular:

Figure 1 shows various aperiodic defects in a top view of a portion of a large flat patterned medium with a periodic transistor array.

FIG. 2 shows an exemplary cross-sectional view of an amorphous silicon residue.

FIG. 3 illustrates an exemplary equivalent circuit diagram of a-Si residues relative to a TFT pixel.

Fig. 4 is a sample graph of the dependence of sheet resistance on the wavelength of incident light.

FIG. 5 is an exemplary schematic diagram of a dual wavelength illuminator (DWI) according to an embodiment of the inventive concept.

FIG. 6 is an exemplary schematic diagram of a modulator mount illuminator (MMI) according to another embodiment of the inventive concept.

Figure 7 illustrates an exemplary schematic block diagram of a system of the present invention for detecting defects in a flat panel display.

FIG. 8 is an exemplary graph showing a typical absorption curve of amorphous silicon.

Figure 9 is an example of a possible frontside light and pixel pattern driver timing diagram.

Figure 10 is another example of a possible front side light pattern where the pulses are different for each frame for a given drive pattern.

11A and 11B are graphs of defect detection sensitivity (DDS) and signal-to-noise ratio (SNR) as a function of front side light pulse end time for varying pulse start time and pulse intensity.

Detailed ways

In the following detailed description, reference will be made to the drawing(s) in which elements of the same function will be assigned the same reference numerals. The foregoing drawings show, by way of illustration and not limitation, specific embodiments and implementations consistent with the principles of the invention. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and structural changes and/or substitutions may be made in various elements without departing from scope and spirit of the invention. Accordingly, the following detailed description should not be interpreted in a limiting sense. Furthermore, the various embodiments of the invention described can be implemented in the form of dedicated hardware or a combination of software and hardware.

Those skilled in the art will also understand that array testers can identify defects in LC displays by utilizing voltage imaging test apparatus and methods as described in, for example, U.S. Patents 4,983,911, 5,097,201, and 5,124,635, which are incorporated by reference at It is hereby incorporated in its entirety. Pixels within an LC display are electrically driven using specific patterns, for example, as described in US Pat. Nos. 5,235,272 and 5,459,410, the entire contents of which are hereby incorporated by reference. Because LC displays are constructed of arrays of pixels, when an LC display is electrically driven, some pixels associated with a defect may behave electrically differently than normal pixels and thus can be detected using a voltage imaging sensor and associated image processing software such a difference. By utilizing combinations of different drive patterns, the type and location of many of the defects illustrated in FIG. 1 can be deduced.

However, it is very difficult to detect defective pixels with a-Si residues 128 under ITO in array testing using standard array testing methods. A cross-sectional view of an example of a TFT pixel 200 with a-Si defects is shown in FIG. 2 . TFT pixel structures 200 are formed on a glass plate 202 . A gate insulator 204 is placed on the glass, then data metal lines 206 may be coated, and then the pixel features in the form of a transparent conductive material such as indium tin oxide (ITO) 210 are deposited. Finally, a passivation layer such as silicon nitride (SiNx) 208 is deposited. Amorphous silicon or data metal residues 212 may remain and are graphically represented as extensions of line features that subsequently fall under the ITO layer. The overlap region 214 between the residue 212 and the pixel (ITO) 210 forms a capacitor 216 with a parasitic capacitance Cp.

Figure 3 is an equivalent diagram of a-Si residues under a pixel. In this case:

C _p ＝k _SiN *ε ₀ *Area _residue /d _{gate SiN} equation 1

C _st ＝k _SiN *ε ₀ *W _pixel W _st /d _passSiN Equation 2

where C _p is the parasitic capacitance, K _SiN is the dielectric constant of SiN, ε ₀ is the permittivity constant in air, W _pixel is the width of the pixel, and W _st is the width of the storage capacitor (the capacitance is C _st ), d _passSiN and d _{gate SiN} are the thicknesses from the passivation layer and the gate electrode to the SiN layer respectively, and the Area _residue is the area of the residue defect in question.

In the array test, a driving voltage is applied to the LC panel, and the pixel response is observed through the voltage imaging sensor. For defects such as data metal residues and a-Si, a positive-negative (PN) drive pattern can be used, where the data voltage drops to a negative value before image acquisition. In this pattern, the drop in data voltage causes a voltage drop across pixels with ITO-data line overlap. If the data voltage drop is ΔV _d , the pixel voltage drop ΔV _p can be expressed as the following formula:

$\mathrm{\Δ}{V}_p=\mathrm{\Δ}{V}_d\left[\frac{C_p}{C_{\mathrm{st}}+C_p}\right][1-\exp \left(\frac{-\mathrm{\τ}}{R_{\mathrm{Si}}(C_{\mathrm{st}}+C_p)}\right)]$ [Formula 3]

where _Cp is the parasitic capacitance of the ITO-data line residue overlap, _Cst is the capacitance of the storage capacitor, and _RSi is the sheet resistance of amorphous silicon.

Equations 1 and 3 reveal two key points about a-Si defects. First, the parasitic capacitance is a function of the size of the defect (Area _residue ). Second, is the exponential dependence on the sheet resistance _RSi . In the insulator state (in the absence of light), R _Si can be very high (on the order of hundreds of gigaohms/square), so according to Equation 3, in the absence of exposure to light, ΔV _p is approximately equal to ΔV _d * (C _p /C _st ), and it has a maximum value. Since C _p < C _st , the maximum ΔV _p may be very small without exposure to light, and therefore these defects may not be easily detected in the absence of light. Depending on the overlapping area, this variation may result in a shift of a few gray levels under a conventional 64 gray level driving scheme. The voltage step size between two consecutive gray levels is approximately 50mV. This is too small to distinguish a defect from a normal pixel.

Furthermore, however, very small a-Si defects may not be detectable even with exposure to light due to the size dependence (Equation 1).

Although some a-Si defects can be found using AOI, and some defects can be detected using AC using conventional defect detection techniques, a large proportion of these defects cannot be identified at an early stage and can only be identified in the TFT-LCD unit After the assembly has been completed, it cannot be detected until after the LC board has been separated into panels and assembled into modules. In the unit test, the backlight module provides a light source for the TFT-LCD panel displaying images when electrically driven. The light-sensitive properties of a-Si make it possible to detect this defect under these conditions. However, it is desirable to actually capture these defects prior to the cell assembly step, and more preferably during the array inspection step, since the residue can be relatively easily removed using a laser repair system. Furthermore, detecting these defects early in the manufacturing process and prior to unit assembly saves costs associated with the assembly process and with the required color filter glass.

LCD array inspection equipment generally does not have an external light source, so detection of a-Si residues can be difficult. Array testers of the AC47xx product family manufactured by Photon Dynamics (acquired by Orbotech Ltd.) incorporate a short-wavelength backlight that is a transparent chuck with a split axis-type system Used in conjunction where the inspection area, and thus the chuck, is limited to a single modulator row. However, in gantry type systems where the chuck covers the entire glass dimension, an associated backlight will also be required to cover the entire glass either moving (e.g. single line) or statically (e.g. full coverage). size, and thus may be neither practical nor cost-effective.

For some cases where the a-Si residue covers the gate metal in the TFT, the backlight will not be able to pass through this gate feature, making it difficult to detect the a-Si residue on the gate. This is a frequent defect in certain pixel designs with redundant TFTs, particularly in those cases where the redundant TFTs are electrically isolated and not connected to the pixel. When the a-Si residue bridges the pixel TFT and the redundant TFT, it affects performance and thus is considered a defect. a-Si residues increase C _gd (gate-drain parasitic capacitance). Due to the gate-drain capacitor coupling effect, when the gate is turned off, the pixel voltage decreases (voltage swing: ΔV _g ). This is called the kick-back effect. The pixel voltage drop ΔV _p can be expressed as:

ΔV _p =ΔV _g *C _gd /(C _gd +C _st +C _lc ). [Formula 4]

Among them, C _lc is the electric capacity of the cell (exists only in the situation of driving the cell). The a-Si residue on the gate connecting the pixel TFT to the redundant TFT increases the gate-drain capacitance, which in turn increases the pixel voltage drop.

Other non-voltage imaging array testers, such as those using electron beams, can detect a-Si residues by spraying the defect with electrons and then accumulating the electrons in the defect area. This accumulation of electrons increases the a-Si conductivity, making defects detectable by associated imaging methods.

According to an embodiment of the present invention, a frontside illumination apparatus and method are provided to enable the detection of a-Si residue defects in the array test step, typically prior to the cell step, in particular, the detection of gates of TFT array cells. a-Si residues on polar insulators. Those skilled in the art will appreciate that a-Si has high resistivity in the absence of exposure to light in TFT array testing. On the other hand, when the a-Si residue is illuminated by light, its resistivity will decrease, which in turn changes the electrical properties of the TFT array cells, which can be detected using a voltage imaging optical system (VIOS) such as Voltage imaging optics manufactured by Photon Dynamics, Inc. (Orbotech, Inc.), 5970 Optical Court, San Jose, CA 95138, USA. Example embodiments of such systems are described in detail in the aforementioned US Patents 4,983,911, 5,097,201, and 5,124,635, which are hereby incorporated by reference in their entirety. Accordingly, in one embodiment of the present invention, the TFT array elements are exposed to light pulses that impact the top side of the TFT panel during testing with the VIOS.

According to an embodiment, the front side illumination follows the same path as the illumination used for voltage imaging in the VIOS. In an embodiment, VIOS illumination is performed in the red portion of the visible wavelength range. In a specific embodiment, an exemplary wavelength of light is 630 nm. According to another embodiment, the front side illumination contains one or two wavelengths and is delivered at the periphery of the voltage image modulator of the VIOS.

In one embodiment of the present invention, according to the VIOS test device and its functions, the implementation of irradiating to the top side or the front side of the flat panel array tester is realized. This results in cost savings and increased efficiency of the overall test system since several components of the VOIS column are being used for both frontside illumination and VIOS imaging. Specifically, since the ability to detect the defect of interest (a-Si) is a function of light intensity, the front side illumination of the TFT cell must be suitably uniform and repeatable in the detection region of interest. In addition, the illumination and optics used to inspect a-Si must not interfere with the ability of the VIOS tester to find other types of defects that may occur in the TFT cell, some of which are described above.

In one embodiment of the present invention, a system configured to generate front side illumination of LCD structures on a panel under test during LCD array testing is provided to facilitate detection of photosensitive manufacturing defects, such as the structure of LCD pixels ( For example, a-Si residues remaining on gate structures or attached to data lines). In an embodiment of the inventive system, the front side of the panel is illuminated with light having a wavelength different from that used for voltage imaging in the VIOS. This is done for at least several reasons. First, the light used in VIOS illumination may have wavelengths that do not allow effective detection of a-Si residues and/or other photosensitive defects. Second, the design of the VIOS modulator is such that the light used for voltage imaging in the VIOS is almost completely reflected by the pellicle of the aforementioned modulator and thus does not reach the panel. Accordingly, the light for front side illumination is chosen such that it activates (changes) the electrical properties of the a-Si residue and is transmitted by the film.

Finally, the overall system includes (using the aforementioned differences in the individual light wavelengths) components to separate the two beams and prevent the light used for front side illumination from interfering with the VIOS imaging (low pass filter 510 shown in Figure 5).

A diagram of an exemplary embodiment of a dual wavelength optical illumination system 500 of the present invention is shown in FIG. 5 . This illustration is for illustrative purposes only and should not be construed as limiting the scope of the invention in any way. As shown in FIG. 5, for use in conjunction with a voltage imaging optical system (VIOS) based array inspection and testing system, a dual wavelength illumination device (DWI) 512 is placed in the optical column of the VIOS illumination device. The construction of the VIOS irradiation device is described, for example, in US Patent 5,124,635, which is hereby incorporated in its entirety.

As shown in FIG. 5, a dual-wavelength illumination device 512 couples blue light 504 (e.g., having a wavelength of 455 nm, to which a-Si defects are particularly sensitive) generated by blue light illumination device 502 to red light used for defect imaging. The visible light 505 (for example, the wavelength is 630 nm) generated by the irradiation device 501 is in the same optical path. Specifically, FIG. 8 shows a typical light absorption curve 801 of a-Si, which indicates that light (802) having a wavelength of 455 nm has the highest absorption coefficient for a-Si.

The coupling of the aforementioned two light beams of different wavelengths is realized in the dual-wavelength irradiation device 512 by using a dichroic mirror (beam splitter) 503. The dichroic mirror 503 substantially transmits the blue light beam 504 and substantially reflects the red light beam 505 to generate A combined beam with two wavelengths. As will be understood by those skilled in the art, the coupling of beams of different wavelengths can be accomplished in many other ways, some of which will be described below with reference to other embodiments of the invention. Accordingly, the specific design of the dual-wavelength illumination device 512 shown in FIG. 5 should not be considered limiting in any way.

Turning to the system shown in Figure 5, after passing through the dichroic mirror (beam splitter) 503, the collinear blue and red light beams are reflected by the beam splitter 506 and pass through the lens assembly 507, providing the lens assembly 507 for optical modulation The desired illumination distribution pattern on the device 508 and the panel 509 under test.

As noted above, in various additional or alternative embodiments of the invention, dual wavelength collinear illumination of the modulator 508 and the panel under test 509 can be accomplished in a number of different ways. For example, in one embodiment, multi-wavelength light emitting diodes (LEDs) may be employed, wherein the wavelength selection of these multi-wavelength diodes may be limited. In this configuration, it is only necessary to use an illumination device using the aforementioned multi-wavelength LEDs instead of, for example, the light source 502, while the second light source 501 and the dichroic mirror 503 can be eliminated from the illumination system.

In another alternative embodiment, a single wavelength red LED and a single wavelength blue LED may be spatially interspersed together in a single light source that may also be used in place of light source 502 . Also, in this configuration, the second light source 501 and the dichroic mirror 503 need to be removed from the illumination system. It should be noted, however, that in such a configuration utilizing two interspersed LEDs of different wavelengths, the uniformity of the illumination may be compromised.

In one embodiment, the VIOS modulator 508 is provided with a thin film 515 located on the surface of the modulator 508 of the LCD structure under test spatially adjacent to the panel under test. The film 515 has optical properties specifically chosen such that the red light generated by the illuminating device 501 is being reflected by it and the blue light generated by the illuminating device 502 is being transmitted by the film 515 . Modulator 508 modulates the intensity of the red light reflected by film 515 based on the distribution of potentials on the top surface ( FIG. 5 ) of test panel 509 placed spatially adjacent to the film of modulator 508 . After being reflected by the film, the modulated red light passes through lens assembly 507 , beam splitter 506 and low pass filter 510 . After passing through the filter 510, the reflected red light impinges on the photosensitive element of the CCD device 511, which is used to create an image of the panel under test. To prevent any blue light used to illuminate the a-Si residue from interfering with the CCD image sensor 511 of the VIOS, the CCD device 511 is equipped with a low-pass filter 510 . The filter has optical transmission properties designed to greatly attenuate blue light and allow the red light to pass through without attenuation. This prevents the front side illuminated blue light from reaching the CCD device 511 and interfering with the created image of the potential on the top surface of the panel 509 under test. It should be noted that in one embodiment of the present invention, the blue light is only used to alter the electrical properties of the a-Si residue to make it easier to detect eg by VIOS, without producing an image of the defect itself.

The LCD structure under test on the surface of the panel under test 509 is biased by voltage source 513 , while the top surface 516 ( FIG. 5 ) of modulator 508 is biased by voltage source 514 . In one embodiment of the invention, all optical components of the system are equipped with suitable optical coatings for optimal light transmission and reflection. It should be noted that the uniformity of illumination for the two wavelengths of light (blue and red) will be similar, and typically no worse than approximately 25% in one embodiment of the invention. Typical illumination uniformity ranges between 10% and 15%. Thus, the inventive dual wavelength illumination concept and configuration shown in FIG. 5 allows a-Si defects to be illuminated at the wavelength to which a-Si defects are most sensitive, without degrading or interfering with the functionality of voltage imaging test (VIOS) hardware.

It should be noted that the invention is not limited to illuminating the modulator and the tested panel with only red and blue light. As will be appreciated by those skilled in the art, another wavelength of illumination light can be selected to achieve proper absorption by the a-Si residues in order to alter its electrical properties sufficiently to enable detection and reduce the impact of front side illumination on VIOS operation ( It is used to recreate the disturbance of the voltage distribution pattern) on the panel under test.

According to a second alternative embodiment of the inventive dual wavelength illumination concept illustrated in FIG. 6 , and also for use in conjunction with VIOS based array inspection and testing systems, a ring illumination device 601 is incorporated into the modulator seat 600 . A ring illuminator 601 is mounted above the modulator 508 and a single wavelength (blue or approximately 455nm wavelength) light source 603 (eg multiple LEDs) is located out of the optical path of the VIOS illuminator to prevent image clipping. As in the first embodiment previously described, the thin film (not shown) of the modulator 508 transmits blue light and reflects light of visible wavelengths generated by the red illumination device 501 , which is required for the function of the voltage imaging modulator 508 . Light source 603 creates illumination pattern 604 . In an exemplary embodiment of the invention, each side of the mounting ring 601 carries four LEDs 603. However, those skilled in the art will understand that any other suitable number of LEDs spaced on the mounting ring 601 in any suitable manner may be utilized to achieve the desired intensity and uniformity of illumination. Accordingly, the invention is not limited to the illustrated arrangement of illuminator ring 601 , modulator mount 600 and light source 603 . In various embodiments of the invention, the illuminating device ring 601 has a square, rectangular, octagonal, circular, oval, or other suitable shape. Light generated by light source 603 passes through modulator 602 and illuminates the front side of the panel under test in order to affect the electrical properties of the a-Si residues on the panel under test.

As will be appreciated by those skilled in the art, depending on the size of the modulator 508, in some cases, especially when the number of LEDs 603 is relatively small, compared to the dual wavelength illumination device (DWI) described with reference to FIG. , it may be more difficult to achieve good uniformity in this embodiment. However, increasing the number of LEDs 603 to more than 10 per side (more than 40 in total) facilitates greater Irradiation uniformity and uniformity characteristics. For optimum uniformity across the modulator area, the emission angle of the LED must be controlled. As is well known in the art, certain LEDs have a Lambertian emission profile and thus emit at very large solid angles, which is detrimental to achieving the desired goal of high illumination uniformity because more light is sent unbalanced to the center of the modulator. Several alternative solutions exist to overcome this deficiency. In one embodiment, a dedicated plurality of directional LEDs is utilized as the light source 603 and directed to illuminate the innermost portion of the modulator 508 .

In an alternative embodiment, a collimating lens is added or preferably optically coupled to each generic LED to encompass the extension of the Lambertian profile. Various methods for optically coupling a collimating lens to an LED are well known in the art. In one embodiment, each LED is equipped with its own collimating lens. These collimating lenses help to enhance the uniformity of the front side illumination. In yet another embodiment, directional attenuation is applied by adding a neutral density filter on the LED side. In addition, diffusers can be used to: (1) eliminate the spatial non-uniformity of each LED; and (2) improve the overall illumination uniformity of the combined LED distribution. For example, in one embodiment, diffusers manufactured and sold by Luminit (Physical Optics Corporation) of Torrance, California, USA may be utilized.

In one embodiment, a beam shaping diffuser that produces an elliptical radiation distribution may be used to improve front side illumination uniformity. In the same or different embodiments, front side illumination uniformity can also be improved by utilizing light bending or turning films.

The main advantage of the multi-light source configuration shown in Figure 6 is that it will be easier and less expensive to retrofit existing gantry-type systems where a-Si residue on the tested panel 509 surface The light source 603 providing front side illumination is mounted on a separate mounting ring arranged near the modulator 508 on the dual wavelength illumination system of FIG. 5 with the second light source integrated in the VIOS column itself. Furthermore, the inventive concept illustrated in FIG. 6 can be applied to defect inspection techniques that require uniform peripheral illumination (such as e-beam based detectors, and possibly also full contact probe testers). It should be noted, however, that e-beam detectors are not compatible with blue light radiation, as previously stated.

Those skilled in the art will understand that the system configuration for providing front side illumination, including arranging the light source near the modulator, can be implemented in many ways other than the embodiment shown in FIG. 6 . Accordingly, the particular design of the illumination system shown in Figure 6 should not be considered limiting in any way.

FIG. 7 illustrates an exemplary schematic block diagram of a system 700 for detecting defects in a flat panel display employing one of the embodiments of the inventive concept. The system of the present invention incorporates VIOS 702, which includes a dual-wavelength illumination device 703, an exemplary embodiment of which was described above with reference to FIG. 5 (element 512). The light beam of the first wavelength (eg, blue light) generated by the illuminating device 703 is directed to the LCD panel 701 mounted on the glass support. The light beam of the second wavelength (e.g. red visible light) generated by the illumination device 703 is directed onto the modulator 705, which is operatively used on the LCD panel to be subjected to the test bias voltage via the electro-optic sensor (modulator) The electric field of is transformed into a spatially modulated optical signal, which is reflected by a thin film (not shown) of the modulator 705 . The reflected light is focused by the lens system 704 onto the CCD device 711, which creates an image of the area of the LCD panel under test in reflected red light by the CCD device 711, which is indicative of the distribution of potentials on the panel under test 701. Exemplary system 700 may further include image acquisition/image processing PC 709 configured to receive image data from CCD device 711, generate an image of the panel under test using the received image data, and process the generated image to identify defective LCDs unit, including the location of such defective unit on the panel tested. Location information of these defects can be recorded for further processing, eg to correct detected defects.

In one embodiment of the present invention, the VIOS 702 is installed on a movable X/Y/Z platform assembly 706, and the X/Y/Z platform assembly 706 can move under the control of the platform/IO control module 707. In an embodiment of the invention, more than one VIOS 702 is installed on the same X/Y/Z platform 706, so that different regions of the panel for the test are being simultaneously inspected with different VIOS 702.

Finally, a test signal pattern generator 710 is arranged to provide a driving voltage pattern to the LCD panel under test to control the triggering of the illumination device and provide the required bias voltage to the modulator.

It should be noted that in embodiments of the present invention, the front side illumination system can be fully integrated in the VIOS subsystem, without being limited in any way by the detection techniques described above, which provides optimal absorption efficiency and radiation uniformity. The frontside light illumination technique illustrated in FIG. 6 is also applicable to electron beam based inspection systems. However, irradiance uniformity should be especially good for the dual-wavelength illumination setup design described above and illustrated in Figure 5, where the blue light for a-Si activation follows the same optical path as the primary VIOS illumination light reaches the modulator .

In one embodiment of the invention, the front side illumination is pulsed and its duration and intensity are optimized to maximize photosensitive defect detection relative to the TFT pixels. Specifically, the frontside illumination light has a wavelength that matches the maximum absorption optical property of the photosensitive defect. In a specific embodiment, blue light with a wavelength less than 470 nm is used for the front side illumination of the a-Si residue.

In an embodiment of the invention, the wavelength used to increase the conductivity of the amorphous silicon residue is chosen to match the absorption properties of the material for optimal front side light efficiency. Typically, a-Si has an absorption edge in the low wavelength (blue) range, see curve 801 in FIG. 8 . For larger wavelengths (lower energy) the absorptivity drops sharply, while for shorter wavelengths the absorptivity remains more or less unchanged. It should be noted that e-beam based defect detection is not compatible with the use of blue light due to the significant amount of noise introduced in the secondary electron detector it uses to measure the pixel voltage. There are two reasons for this. First, short-wavelength photons, such as blue light, have more energy than photons with red wavelengths, so when they hit the scintillator-photomultiplier detectors needed to detect electrons, they produce more unwanted noise signal. Second, since the energy of secondary electrons entering the detector may be affected by electron and photon collisions, there may be greater signal variation, which contributes to the overall noise.

Amorphous silicon is sensitive to short-wavelength light, thus generating mobile photoelectrons after irradiation, leading to an increase in the conductivity of a-Si defects. In some embodiments, blue light with a wavelength of 470 nm (or shorter) is chosen, in part because it has relatively higher power that is more efficiently absorbed in a-Si, and has lower sheet resistance . Figure 4 illustrates a graph of sheet resistance as a function of light intensity for two different wavelengths, 470 nm (curve 401 ) and 530 nm (curve 402 )). It can be seen from these graphs that the shorter of the two wavelengths (401) decreases the resistance faster as the intensity increases. The use of shorter wavelength light may also enable the detection of smaller sized defects since the signal corresponding to light having a shorter wavelength may be stronger (Equations 1 and 3).

A disadvantage of illuminating the front panel surface with light of a wavelength to which a-Si is sensitive is that the TFT channels are also exposed to the same light illumination. Since the TFT structure is also made of a-Si material, impinging on the front side irradiation will also increase the conductivity of the a-Si material in the TFT in the same way as residues forming defects. When exposed to light, the off-state conductivity of the TFT will increase, and thus the leakage current of the TFT will be higher than the corresponding value in the dark state. This results in an increased attenuation of the pixel voltage, which can be detected using the voltage response of the TFT to defect detection, by a voltage imaging tester, or other similar testing methods. Therefore, even if the TFT channel is not actually defective, a decay tester that depends on the pixel voltage can erroneously consider it to be defective. That is, illuminating a good TFT pixel or channel with frontside illumination may result in the observation of spurious defects.

One way to minimize pixel voltage decay due to TFT leakage current, but at the same time maximize the detection response of a-Si residues, is to pulse the front-side illumination light and vary the duration and intensity of the light pulses. FIG. 9 is an exemplary graphical user interface 900 showing a graph of front side light timing versus LCD drive pattern signal timing. Signals 901 (odd data), 902 (even data), 903 (odd strobe), 904 (even strobe) constitute an LCD test drive pattern. The front side illumination pulse 905 is characterized by its intensity, duration, start time and end time.

Fig. 10 is another example of a possible frontside light pattern 1000, where the parameters of the frontside illumination pulse 905 are different for each frame of a given drive pattern. Specifically, in the first (A) frame, the front illumination pulse 905 has a duration of 3 milliseconds, a start time of 3.5 milliseconds, and an intensity of 50%. In the second (B) frame, the front side illumination pulse 905 is off. In the third (C) frame, the front illumination pulse 905 has a duration of 7 milliseconds, a start time of 0 milliseconds, and an intensity of 25%. Finally, in the fourth (D) frame, the front illumination pulse 905 has a duration of 3 milliseconds, a start time of 3.5 milliseconds, and an intensity of 50%. Modulator bias 906 is the same for each frame.

Maximizing pixel voltage drop caused by a-Si residue while minimizing voltage drop caused by TFT leakage corresponds to maximizing defect detection sensitivity (DDS) while making site standard deviation small or Make the signal-to-noise ratio (SNR) high. Specifically, the value of DDS is a measure of defect contrast and is defined as the comparison between the pixel voltage of a normal pixel and that of a defect, ie DDS=(1-V _defect /v _site-av ), and typically For detection with a 30% threshold (which is a value typically used in defect detection), the DDS should be greater than 0.3. The site standard deviation should be kept less than 0.4V, while the signal-to-noise ratio SNR=(V _site-av /standard deviation) can be greater than 25.

11A and 11B illustrate test results 1100 and 1200 obtained using an exemplary embodiment of the system of the present invention for a particular type of defect (parasitic data-pixel capacitance type defect). These figures show the dependence of DDS (FIG. 11A) and SNR (FIG. 11B) on the front light end time. Specifically, the data curves 1101-1109 of FIG. 11A are shown for nine pairs of intensity and onset time values. Specifically: 10% intensity, 1 millisecond onset time (curve 1101); 10% intensity, 7 millisecond onset time (curve 1102); 10% intensity, 9 millisecond onset time (curve 1103); 50% intensity, 1 Millisecond onset (curve 1104); 50% intensity, 7 msec onset (curve 1105); 50% intensity, 9 msec onset (curve 1106); 90% intensity, 1 msec onset (curve 1107) ; 90% intensity, 7 milliseconds onset (curve 1108 ); and 90% intensity, 9 milliseconds onset (curve 1109 ). Curves 1201-1209 shown in FIG. 11B correspond to the same intensity/onset time pairs as corresponding curves 1101-1109 of FIG. 11A. It should be noted that pulse duration, intensity, and onset time may vary from panel to panel, and may vary from defect type to defect.

First, it can be observed from the provided curves 1101-1109 that DDS increases with pulse end time and duration (due to the effect of front side light on a-Si residues), while SNR decreases with pulse end time and duration (Due to the influence of the front light on the TFT). Second, between 10% and 50% intensities, the value of DDS increases and the value of SNR decreases, but does not change for higher intensities. This indicates the presence of a saturation effect. Third, the values of DDS and SNR appear to be saturated for Tend > 14ms (take T=0 at the beginning of the positive modulator period). Fourth, pulses limited to the negative modulator bias period have no effect when no pixel driving is in progress.

As indicated in FIGS. 11A and 11B , for pulses with an intensity of 50% or higher, and for pulses ending t=8 to 11 milliseconds after the start of the positive half-cycle of the modulator bias cycle (i.e. The case where the hold times at the end of the dip overlap by 1 to 3 milliseconds) satisfies optimal detection, ie DDS > 0.3 and SNR > 25%, in a particular embodiment of the inventive concept. It should be noted that pulses with longer durations result in unacceptably large SNR degradation due to light-induced TFT leakage. For comparison, in FIG. 11B , the SNR value 1210 corresponding to defect detection without frontside light is also shown.

Finally, it should be understood that the processes and techniques described herein are not inherently related to any particular device, but may be implemented by any suitable combination of components. In addition, various types of general purpose devices can be used in accordance with the teachings described herein. It may also prove advantageous to construct dedicated apparatus to perform the method steps described herein. The present invention has been described in connection with specific examples, which are intended in all respects to be illustrative rather than restrictive. Those skilled in the art will appreciate that many different combinations of hardware, software, and firmware will also be suitable for implementing the invention.

In addition, other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. Various aspects and/or components of the described embodiments may be used alone or in any combination in the defect detection system of the present invention. It is intended that the specification and these examples be considered exemplary only, with a true scope and spirit of the invention being indicated by the claims and their equivalents.

Claims (30)

1. A system for detecting defects in tested panels, the system comprising: a. a frontside illumination subsystem configured to deliver a frontside illumination beam onto the panel under test, the frontside illumination beam altering the electrical characteristics of the defect to facilitate detection of the defect; and b. A detection subsystem configured to detect said defect based on said defect's altered electrical properties, wherein the front side illumination beam is pulsed and its duration and intensity optimized to enable detection of said defect The detection of spurious defects is maximized and minimized, and wherein the frontside illuminating beam has a wavelength that matches the maximum absorption optical property of said defects. 2. The system of claim 1 , further comprising a voltage signal source configured to apply a voltage signal to the panel under test, the applied voltage signal causing a spatial voltage distribution on the panel under test, wherein the detection subsystem comprises Voltage imaging optics configured to create an image indicative of the spatial voltage distribution on the tested panel, and wherein the defect is detected based on the created image. 3. The system of claim 2, wherein the front side illumination subsystem is integrated within the optical path of the voltage imaging optics. 4. The system of claim 3, wherein the optical path of the voltage imaging optics comprises a dichroic mirror configured to combine the voltage imaging beam and the front illumination beam. 5. The system of claim 3, wherein the voltage imaging optics comprise an imaging device configured to create an image indicative of the spatial voltage distribution on the tested panel, and a low pass filter, the low pass filter A device is configured to prevent the front side illumination beam from reaching the imaging device. 6. The system of claim 3, wherein the voltage imaging optics comprises a modulator configured to modulate a voltage imaging beam according to a spatial voltage distribution on the panel under test, the modulator having a function configured to reflect the voltage imaging beam and transmits the front-side illuminating beam of film. 7. The system of claim 1, wherein the front illuminating beam is in the blue wavelength range, and wherein the voltage imaging beam used by the voltage imaging device to create an image has a different wavelength than the front illuminating beam. 8. A system for detecting defects in a tested panel, the system comprising: a. a frontside illumination subsystem configured to deliver a frontside illumination beam onto the panel under test, the frontside illumination beam altering the electrical characteristics of the defect to facilitate detection of the defect; and b. a detection subsystem configured to detect said defect based on said defect's altered electrical characteristics, said detection subsystem comprising voltage imaging optics configured to create a spatial voltage distribution indicative of the tested panel image, wherein the defect is detected based on the image created, wherein the frontside illumination beam has a wavelength that matches the maximum absorption optical property of the defect, and wherein the frontside illumination subsystem is integrated into the optics of the voltage imaging optics within the path. 9. The system of claim 8, wherein the optical path of the voltage imaging optics comprises a dichroic mirror configured to combine the voltage imaging beam and the front illumination beam. 10. The system of claim 8, wherein the voltage imaging optics comprises an imaging device configured to create an image indicative of the spatial voltage distribution on the tested panel, and a low pass filter, the low pass filter A device is configured to prevent the front side illumination beam from reaching the imaging device. 11. The system of claim 8, wherein the voltage imaging optics comprises a modulator configured to modulate the voltage imaging beam according to a spatial voltage distribution on the panel under test, the modulator having a modulator configured to reflect the voltage The film that images the beam and transmits the front-side illuminating beam. 12. The system of claim 8, wherein the front illuminating beam is in the blue wavelength range, and wherein the voltage imaging beam used by the voltage imaging device to create an image has a different wavelength than the front illuminating beam. 13. A system for detecting defects in a tested panel, the system comprising: a. a frontside illumination subsystem configured to deliver a frontside illumination beam onto the panel under test, the frontside illumination beam altering the electrical characteristics of the defect to facilitate detection of the defect; and b. a detection subsystem configured to detect said defect based on said defect's altered electrical characteristics, said detection subsystem comprising voltage imaging optics configured to create a spatial voltage distribution indicative of the tested panel image, wherein the defect is detected based on the image created, wherein the frontside illumination beam has a wavelength that matches the maximum absorption optical property of the defect, and wherein the frontside illumination subsystem is arranged in the voltage imaging optics outside the optical path. 14. The system of claim 13, wherein the front illumination subsystem includes specially oriented LEDs mounted on a mounting ring to optimize uniformity of the front illumination beam. 15. The system of claim 13 , wherein the front side illumination subsystem comprises a plurality of light emitting diodes, and wherein at least one light emitting diode in the plurality of light emitting diodes is optically coupled to a collimating lens, the collimating lens being Mounted on the mounting ring to optimize the uniformity of the front side illumination beam. 16. The system of claim 13, wherein the front illumination subsystem comprises a plurality of LEDs optically coupled to a directional attenuation module to optimize uniformity of the front illumination beam. 17. The system of claim 13, wherein the directional attenuation module comprises a neutral density filter. 18. The system of claim 13, wherein the voltage imaging optics comprise an imaging device configured to create an image indicative of a spatial voltage distribution on the tested panel, and a low pass filter, the low pass filter A device is configured to prevent the front side illumination beam from reaching the imaging device. 19. The system of claim 13, wherein the voltage imaging optics comprises a modulator configured to modulate the voltage imaging beam according to a spatial voltage distribution on the panel under test, the modulator having a modulator configured to reflect the A voltage images the beam and transmits the film of the front illumination beam, and wherein the front illumination subsystem is disposed in close spatial proximity to the modulator. 20. The system of claim 13, wherein the voltage imaging optics and the front side illumination subsystem are mounted on a movable platform assembly configured to scan the Test panel. 21. The system of claim 20, further comprising at least one second voltage imaging optics and at least one second front side illumination subsystem mounted on the movable platform assembly. 22. The system of claim 13, wherein the front illuminating beam is in the blue wavelength range, and wherein the voltage imaging beam used by the voltage imaging device to create an image has a different wavelength than the front illuminating beam. 23. The system of claim 13, wherein the front side illumination subsystem comprises a plurality of LEDs, and wherein each of the plurality of LEDs is equipped with a A diffuser for each of the light emitting diodes, the diffuser is configured to eliminate the spatial non-uniformity of the front illuminating beam and improve the overall illumination uniformity of the front illuminating beam. 24. A method for detecting defects in a tested panel, the method comprising: a. utilizing a front illumination subsystem to deliver a front illumination beam onto the panel under test, the front illumination beam altering the electrical characteristics of the defect to facilitate detection of the defect; and b. Detecting the defect based on its altered electrical properties using a detection subsystem wherein the front side illumination beam is pulsed and its duration and intensity optimized to maximize detection of the defect and to minimize the detection of spurious defects, and wherein the front side illumination beam has a wavelength matched to the maximum absorption optical property of said defects. 25. The method of claim 24, further comprising applying a voltage signal to the panel under test, the applied voltage signal causing a spatial voltage distribution on the panel under test and creating a signal indicative of the spatial voltage distribution on the panel under test An image, wherein the defect is detected based on the created image. 26. The method of claim 25, wherein an image indicative of the spatial voltage distribution on the tested panel is created using a voltage imaging beam, and wherein the front illumination beam is within the optical path of the voltage imaging beam. 27. The method of claim 25, wherein the image indicative of the spatial voltage distribution on the tested panel is created using voltage imaging optics comprising an imaging device and a low pass filter, the low pass A filter is configured to prevent the front illumination beam from reaching the imaging device. 28. The method of claim 25, wherein the front side illuminating beam is in the blue wavelength range, and wherein the voltage imaging beam used to create an image indicative of the spatial voltage distribution on the tested panel has a different voltage than the front side illuminating beam. The wavelength of the side illuminating beam. 29. A method for detecting defects in a tested panel, the method comprising: a. utilizing a front illumination subsystem to deliver a front illumination beam onto the panel under test, the front illumination beam altering the electrical characteristics of the defect to facilitate detection of the defect; and b. Detecting said defect based on an altered electrical characteristic of said defect with a detection subsystem comprising voltage imaging optics configured to create an image indicative of a spatial voltage distribution on the tested panel, wherein Detecting the defect based on the image created, wherein the frontside illumination beam has a wavelength that matches the maximum absorption optical property of the defect, and wherein the frontside illumination subsystem is integrated within the optical path of the voltage imaging optics . 30. A method for detecting defects in a tested panel, the method comprising: a. Utilizing the front-side illumination subsystem to deliver a front-side illumination beam to the panel under test, the front-side illumination beam changes the electrical characteristics of the defect to facilitate detection of the defect; b. Detecting said defect based on an altered electrical characteristic of said defect with a detection subsystem comprising voltage imaging optics configured to create an image indicative of a spatial voltage distribution on the tested panel, wherein Detecting the defect based on the image created, wherein the frontside illumination beam has a wavelength that matches the maximum absorption optical property of the defect, and wherein the frontside illumination subsystem is arranged outside the optical path of the voltage imaging optics .

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