CN101984668A - Real-time image scaling engine suitable for various 4*4 interpolation filters - Google Patents
Real-time image scaling engine suitable for various 4*4 interpolation filters Download PDFInfo
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Abstract
The invention discloses a real-time image scaling engine suitable for various 4*4 interpolation filters. A line memory adopted in the invention is an SRAM with a bit width of 24 bits, and each line can store 2560 pixels at most. In the invention, only five lines of image data need to be stored to support image scaling with a maximum resolution of 2560*1960, so that the requirement of real-time scaling can be met and more hardware resources can be saved compared with hardwares of the same type. A source clock control module operates at the source clock frequency, a target clock control module operates at the target clock frequency and the source clock control module and the target clock control module realize trans-clock domain operation by controlling reading and writing of line memory data. In the invention, when image amplification operation and image reduction operation are carried out, in response to different realization of the hardware, multiple multi-path selectors are adopted to control data paths, maximally multiplex all modules and realize relatively independent image amplification and reduction operations in the line direction and in the field direction.
Description
Technical field
The present invention relates to the post processing of image technology, relate in particular to a kind of realtime graphic zooming engine that is applicable to various 4 * 4 interpolation filters.
Background technology
In recent years, the flat-panel display device that dot matrix drives is popularized rapidly, becomes the main flow display device gradually.The common feature of flat-panel display device is a corresponding pixel correspondence on the brightness of each pixel and chrominance information and the screen, so the form of its output (fabric width than, resolution) is fixed.The operation principle of panel display screen has determined it only to support so-called true resolution, and flat panel display equipment only just can present best image effect under true resolution.But, in actual environment, input signal as display device can not only be a kind of sample rate form, and may be from Phase Alternation Line system (720 * 576i), NTSC (standard definition video (SDTV) signals of 720 * 480i) systems to high definition video (HDTV) signal (720p, 1080i, 1080p), also or from VGA (640 * 480) to QXGA (2048 * 1536) form.For correct display image, the sample rate of input signal source need be redeveloped into various display device can compatible form.This just need dwindle or amplify signal, and picture signal is become the resolution that panel display screen is supported, will guarantee the display quality of signal simultaneously.
Image zoom is one of key technology in the Digital Video Processing.Interpolation method at present relatively more commonly used has: neighbor interpolation, bilinear interpolation, bicubic convolution, bicubic spline, multinomial parabola etc.Preceding two kinds is that four point (2 * 2) interpolation algorithm hardware are realized in the comparatively simple image zoom hardware in early days comparatively common, the back then needs the individual point in 16 (4 * 4) to carry out interpolation arithmetic for three kinds at least, and wherein bicubic convolution and multinomial parabola algorithm are the Graph Scaler interpolation algorithms commonly used in the current main-stream reprocessing chip.
Present Graph Scaler adopts the fifo structure of first-in first-out more on metadata cache.This structural order write sequence writes out, and need not extra control module.But, because there is greatest differences in the process that image amplifies and image dwindles for the read-write of metadata cache: during the image amplification, may need repeatedly read for same group of data; When image dwindles, may skip some data and not read.Therefore, dwindle the situation of amplifying with image for image, most zooming engines need adopt different circuit structures and bigger data buffer to handle, and can't realize the independent convergent-divergent of line direction and field direction.But, on storage, adopt dual-port SRAM structure, and, just can control data cached read-write flexibly, thereby address the above problem the control module that SRAM reads and writes pointer.To increase limited control module and MUX is cost, uses same set of circuit structure to handle image and dwindles and the image amplification process, effectively economize on hardware resource and manufacturing cost.
Summary of the invention
The objective of the invention is at the deficiencies in the prior art, a kind of realtime graphic zooming engine that is applicable to various 4 * 4 interpolation filters is provided.
The objective of the invention is to be achieved through the following technical solutions: a kind of realtime graphic zooming engine that is applicable to various 4 * 4 interpolation filters, it comprises: first line storage, second line storage, row interpolation filter, an interpolation filter, input pattern detector, clock module, source clock control module, target clock control module, four capable convergent-divergent selectors and three field convergent-divergent selectors.Wherein, the described first row convergent-divergent selector links to each other with first line storage; First line storage links to each other with the target clock control module with the source clock control module respectively; The first row convergent-divergent selector, first convergent-divergent selector link to each other successively with second line storage; Second line storage links to each other with second convergent-divergent selector with the target clock control module respectively; The second row convergent-divergent selector links to each other with the target clock control module with the source clock control module respectively; The input pattern detector links to each other with clock module with source clock control module, target clock control module respectively; Clock module links to each other with the target clock control module; The source clock control module links to each other with the 3rd convergent-divergent selector with the third line convergent-divergent selector respectively; The target clock control module links to each other with the 3rd convergent-divergent selector with the third line convergent-divergent selector respectively; The third line convergent-divergent selector links to each other with the row interpolation filter; The row interpolation filter links to each other with the second row convergent-divergent selector with fourth line convergent-divergent selector respectively; The 3rd convergent-divergent selector links to each other with the field interpolation filter; The field interpolation filter links to each other with first convergent-divergent selector with second convergent-divergent selector respectively; Second convergent-divergent selector links to each other with the first row convergent-divergent selector with fourth line convergent-divergent selector respectively.
The invention has the beneficial effects as follows: adopt dual-port SRAM structure as line storage, by source clock control module and target clock control module data write on the line storage is controlled, thus satisfy image on line direction and the field direction separately independently convergent-divergent for required data the read-write on requirement.Simultaneously, the present invention adopts the difference of a plurality of MUX (MUX) at the situation of dwindling on line direction, the field direction or amplifying, the control data path, thus the functional module in the multiplexing to greatest extent framework is effectively saved hardware resource and manufacturing cost.
Description of drawings
Fig. 1 is 4 the general interpolation models of 4 * 4 interpolation algorithms in the one dimension direction;
Fig. 2 is the general frame that is applicable to the realtime graphic zooming engine of various 4 * 4 interpolation filters;
Fig. 3 is the internal structure of source clock control module;
Fig. 4 is the internal structure of target clock control module;
Fig. 5 is a row interpolation data parallel output module internal structure;
Fig. 6 (a) is for line direction amplifies, data flow diagram when field direction amplifies;
Fig. 6 (b) is for line direction amplifies, data flow diagram when field direction dwindles;
Fig. 6 (c) is for line direction dwindles, data flow diagram when field direction amplifies;
Fig. 6 (d) is for line direction dwindles, data flow diagram when field direction dwindles;
Embodiment
The invention provides a kind of line direction and field direction and all can independently dwindle or amplify, support that the ultimate resolution of convergent-divergent is 2560 * 1920, and be applicable to the method for designing of Graph Scaler of the interpolation filter of various 16 (4 * 4) points.
As shown in Figure 1 be 4 the general interpolation models of the interpolation algorithm of 16 (4 * 4) point in the one dimension direction.The thinking of the interpolation algorithm of 16 (4 * 4) point generally is that the row to original image, the convergent-divergent of field direction separate, reduce algorithm complex and hard-wired complexity by the method that reduces dimension, promptly carry out four point interpolation algorithms of an one dimension respectively at line direction and field direction.For the interpolation point S (x) that needs obtain, main with four adjacent pixel S (x of original image
1), S (x
2), S (x
3), S (x
4) and interpolation side-play amount d as 5 independents variable, obtain the value of interpolation point S (x) by corresponding concrete interpolation kernel function.That is:
S(x)＝f(S(x
1)，S(x
2)，S(x
3)，S(x
4)，d)
As shown in Figure 2 be that the framework of whole zooming engine connects situation, comprising: first line storage, second line storage, row interpolation filter, an interpolation filter, input pattern detector, clock module, source clock control module, target clock control module, four capable convergent-divergent selectors and three field convergent-divergent selectors.The connection situation is as follows: the first row convergent-divergent selector links to each other with first line storage; First line storage links to each other with the target clock control module with the source clock control module respectively; The first row convergent-divergent selector, first convergent-divergent selector link to each other successively with second line storage; Second line storage links to each other with second convergent-divergent selector with the target clock control module respectively; The second row convergent-divergent selector links to each other with the target clock control module with the source clock control module respectively; The input pattern detector links to each other with clock module with source clock control module, target clock control module respectively; Clock module links to each other with the target clock control module; The source clock control module links to each other with the 3rd convergent-divergent selector with the third line convergent-divergent selector respectively; The target clock control module links to each other with the 3rd convergent-divergent selector with the third line convergent-divergent selector respectively; The third line convergent-divergent selector links to each other with the row interpolation filter; The row interpolation filter links to each other with the second row convergent-divergent selector with fourth line convergent-divergent selector respectively; The 3rd convergent-divergent selector links to each other with the field interpolation filter; The field interpolation filter links to each other with first convergent-divergent selector with second convergent-divergent selector respectively; Second convergent-divergent selector links to each other with the first row convergent-divergent selector with fourth line convergent-divergent selector respectively.
First line storage, be that a bit wide is 24 SRAM, be used to store 24 YUV or RGB digital video image data, writing, read respectively of data by writing pointer and reading pointer control, coexistence storage four lines DID, each row of data is supported the view data of 2560 points of maximum storage, and each line data can independently be controlled read-write.Second line storage, be that a bit wide is 24 SRAM, be used to store 24 YUV or RGB digital video image data, the writing, read respectively of data by writing pointer and reading pointer control, storage single file DID is stored 2560 dot image datas at most.Two interpolation filters are used to carry out the interpolation calculation of image zoom, are applicable to various 4 * 4 interpolation algorithms, and the row interpolation filter is used for calculating at the enterprising row interpolation of line direction, and an interpolation filter is used for calculating at the enterprising row interpolation of field direction.The input pattern detector by line synchronizing signal, field sync signal, source clock frequency, obtains resolution, row datum offset amount, a datum offset amount, line synchronizing signal, the field sync signal of input picture.Clock module is used to produce the target clock frequency.The source clock control module, be used under source clock frequency first line storage and second line storage are sent read-write control signal, and the interpolation filter that will send to correspondence from required four the adjacent original image points of the current interpolation point that line storage is read and interpolation side-play amount.The target clock control module, be used under the target clock frequency, first line storage being sent write control signal, first line storage and second line storage sent read control signal, and the interpolation filter that will send to correspondence from required four the adjacent original image points of the current interpolation point that line storage is read and interpolation side-play amount.Four capable convergent-divergent selectors are MUX (MUX), are used for according to the dwindling or the amplification situation of line direction epigraph, and the break-make of control data is judged in input to two-way.Three field convergent-divergent selectors are MUX (MUX), are used for according to the dwindling or the amplification situation of field direction epigraph, and the break-make of control data is judged in input to two-way.Image zoom is according to row, a situation difference of dwindling amplification, and being divided into is four kinds of situations: line direction amplifies, field direction amplifies; Line direction amplifies, field direction dwindles; Line direction dwindles, field direction amplifies; Line direction dwindles, field direction dwindles.Whole framework makes framework be operated in one of corresponding four kinds of situations by a row convergent-divergent selector and a convergent-divergent selector control data path, and detailed data flow diagram is seen Fig. 6.
As shown in Figure 3 be the internal structure of source clock control module.The each several part of source clock control module all is operated under the source clock frequency.He comprises: row interpolation data parallel output module, row interpolation side-play amount accumulator, pixel counter, line storage are write control module, line number counter, interpolation field side-play amount accumulator, line storage and are read control module, the parallel output module of an interpolated data.Its annexation is as follows: row interpolation side-play amount accumulator is write control module with line storage respectively with pixel counter and is linked to each other; Interpolation field side-play amount accumulator is read control module with line storage respectively and is linked to each other with the parallel output module of an interpolated data; The line number counter is read control module with line storage and is linked to each other.
Row interpolation data parallel output module, structure is seen Fig. 5, this module is used for the view data of serial input synchronous by register, produces the parallel row interpolation filter that exports to of four circuit-switched data.Row interpolation side-play amount accumulator, it is an adder, control by clock signal, the capable datum offset amount that the input pattern detector is sent adds up, and export its result's decimal place to the row interpolation filter as row interpolation side-play amount, export its result's integer-bit to line storage and write control module.Pixel counter is a counter by clock signal control, is used for the pixel counts to input picture.Interpolation field side-play amount accumulator, it is an adder, control by clock signal, the field datum offset amount that the input pattern detector is sent adds up, and export its result's decimal place to interpolation filter as the interpolation field side-play amount, export its result's integer-bit to line storage respectively and read control module and the parallel output module of an interpolated data.The line number counter is a counter by clock signal and line synchronizing signal control, is used for the line number counting to input picture.Line storage is write control module, according to the output signal of row interpolation side-play amount accumulator and pixel counter first line storage, second line storage is carried out data and writes.Line storage is read control module, according to the output signal of interpolation field side-play amount accumulator and line number counter first line storage is carried out data read.The parallel output module of field interpolated data, output according to interpolation field side-play amount accumulator, parallel four adjacent original digital image datas that read on first line storage are sorted, according to of the requirement of interpolation filter input, obtain four channel parallel datas and export an interpolation filter to for the input data.
As shown in Figure 4 be the internal structure of target clock control module.The each several part of target clock control module all is operated under the target clock frequency that is produced by clock module.It comprises: row interpolation data parallel output module, row interpolation side-play amount accumulator, interpolation field side-play amount accumulator, line storage are read control module, the parallel output module of an interpolated data.Its annexation is as follows: row interpolation side-play amount accumulator is read control module with line storage and is linked to each other; Interpolation field side-play amount accumulator links to each other with the parallel output module of field interpolated data.
Line storage is read control module, according to the output signal of row interpolation side-play amount accumulator first line storage is carried out data read.Other functions of modules, purposes are similar to the respective modules in the clock control module of source.
As shown in Figure 5 be row interpolation data parallel output module, comprise four d type flip flops.Four d type flip flops link to each other successively.D type flip flop in the module uses as register, connects an output after each d type flip flop.Data on the line direction of serial input just can be passed through and be postponed like this, and line output four adjacent original image points as shown in Figure 1.
As shown in Figure 6 be to dwindle or the different and concrete data flow diagram that produces of amplification situation at line direction, field direction.Line direction shown in Fig. 6 (a) amplifies, the data flow diagram when field direction amplifies.Data are successively by source clock control module, first line storage and second line storage, target clock control module, an interpolation filter, target clock control module, row interpolation filter.And the end that writes of first line storage and second line storage is operated in the source clock zone, reads end and is operated in the target clock territory.Thereby make that in this case engine is realized the cross clock domain operation at first line storage and the second line storage place.Fig. 6 (b) is for line direction amplifies, data flow diagram when field direction dwindles.Under the situation that line direction amplifies, field direction dwindles, data are successively by source clock control module, first line storage, source clock control module, an interpolation filter, second line storage, target clock control module, row interpolation filter.And the end that writes of second line storage is operated in the source clock zone, reads end and is operated in the target clock territory.Thereby make that in this case engine is realized the cross clock domain operation at the second line storage place.Fig. 6 (c) is for line direction dwindles, data flow diagram when field direction amplifies.Under the situation of dwindle at line direction, field direction amplifying, data are successively by source clock control module, row interpolation filter, source clock control module, first line storage and second line storage, target clock control module, an interpolation filter.And the end that writes of first line storage and second line storage is operated in the source clock zone, reads end and is operated in the target clock territory.Thereby make that in this case engine is realized the cross clock domain operation at first line storage and the second line storage place.Fig. 6 (d) is for line direction dwindles, data flow diagram when field direction dwindles.Under the situation of be expert at, field direction all dwindling, data are successively by source clock control module, row interpolation filter, source clock control module, first line storage, source clock control module, an interpolation filter, second line storage.And the end that writes of second line storage is operated in the source clock zone, reads end and is operated in the target clock territory.Thereby make that in this case engine is realized the cross clock domain operation at the second line storage place.In this case, two interpolation filters are all in the work of source clock zone, and the target clock control module is only in the end controlled the output of the second line storage sense data as whole engine.
Claims (4)
1. realtime graphic zooming engine that is applicable to various 4 * 4 interpolation filters, it is characterized in that it comprises: first line storage, second line storage, row interpolation filter, an interpolation filter, input pattern detector, clock module, source clock control module, target clock control module, four capable convergent-divergent selectors and three field convergent-divergent selectors.Wherein, the described first row convergent-divergent selector links to each other with first line storage; First line storage links to each other with the target clock control module with the source clock control module respectively; The first row convergent-divergent selector, first convergent-divergent selector link to each other successively with second line storage; Second line storage links to each other with second convergent-divergent selector with the target clock control module respectively; The second row convergent-divergent selector links to each other with the target clock control module with the source clock control module respectively; The input pattern detector links to each other with clock module with source clock control module, target clock control module respectively; Clock module links to each other with the target clock control module; The source clock control module links to each other with the 3rd convergent-divergent selector with the third line convergent-divergent selector respectively; The target clock control module links to each other with the 3rd convergent-divergent selector with the third line convergent-divergent selector respectively; The third line convergent-divergent selector links to each other with the row interpolation filter; The row interpolation filter links to each other with the second row convergent-divergent selector with fourth line convergent-divergent selector respectively; The 3rd convergent-divergent selector links to each other with the field interpolation filter; The field interpolation filter links to each other with first convergent-divergent selector with second convergent-divergent selector respectively; Second convergent-divergent selector links to each other with the first row convergent-divergent selector with fourth line convergent-divergent selector respectively.
2. according to the described realtime graphic zooming engine of claim 1, it is characterized in that described source clock control module comprises: row interpolation data parallel output module, row interpolation side-play amount accumulator, pixel counter, line storage are write control module, line number counter, interpolation field side-play amount accumulator, line storage and are read control module, the parallel output module of a difference data.Wherein, described capable interpolation side-play amount accumulator is write control module with line storage respectively with pixel counter and is linked to each other; Interpolation field side-play amount accumulator is read control module with line storage respectively and is linked to each other with the parallel output module of an interpolated data; The line number counter is read control module with line storage and is linked to each other.
3. according to the described realtime graphic zooming engine of claim 1, it is characterized in that described target clock control module comprises: row interpolation data parallel output module, row interpolation side-play amount accumulator, interpolation field side-play amount accumulator, line storage are read control module, the parallel output module of an interpolated data.Its annexation is as follows: row interpolation side-play amount accumulator is read control module with line storage and is linked to each other; Interpolation field side-play amount accumulator links to each other with the parallel output module of field interpolated data.
4. according to claim 2 and 3 described realtime graphic zooming engines, it is characterized in that described row interpolation data parallel output module is connected to form successively by four d type flip flops.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016000093A1 (en) * | 2014-06-05 | 2016-01-07 | Empire Technology Development Llc | Data interpolation |
| CN111199515A (en) * | 2018-11-16 | 2020-05-26 | 西安诺瓦星云科技股份有限公司 | Scaler, image scaling method and device |
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| US7321400B1 (en) * | 2005-02-22 | 2008-01-22 | Kolorific, Inc. | Method and apparatus for adaptive image data interpolation |
| CN101350925A (en) * | 2008-07-11 | 2009-01-21 | 清华大学 | A method of interpolation filtering |
| CN101783900A (en) * | 2010-03-10 | 2010-07-21 | 华为终端有限公司 | Method and device thereof for zooming image in partitions |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7321400B1 (en) * | 2005-02-22 | 2008-01-22 | Kolorific, Inc. | Method and apparatus for adaptive image data interpolation |
| CN101350925A (en) * | 2008-07-11 | 2009-01-21 | 清华大学 | A method of interpolation filtering |
| CN101783900A (en) * | 2010-03-10 | 2010-07-21 | 华为终端有限公司 | Method and device thereof for zooming image in partitions |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016000093A1 (en) * | 2014-06-05 | 2016-01-07 | Empire Technology Development Llc | Data interpolation |
| US9736426B2 (en) | 2014-06-05 | 2017-08-15 | Empire Technology Development Llc | Data interpolation |
| CN111199515A (en) * | 2018-11-16 | 2020-05-26 | 西安诺瓦星云科技股份有限公司 | Scaler, image scaling method and device |
| CN111199515B (en) * | 2018-11-16 | 2024-03-19 | 西安诺瓦星云科技股份有限公司 | Scaler, image scaling method and device |
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