CN101674473A - An image real-time histogram statistical device and its implementation method - Google Patents

Abstract

The present invention relates to a real-time histogram statistics device for images and its implementation method. The device comprises a video decoding unit, which receives an original image signal for filtering, amplifying and digital processing to generate video data; a programmable logic gate array, which receives the video data output by the video decoding unit and performs histogram statistics on the video data; a program memory, which is used to store application programs of the programmable logic gate array; a clock management unit, which provides the required clock for the programmable logic gate array and the video decoding unit; a reset management unit, which provides a reset signal for the programmable logic gate array; a power management unit, which provides the required power for the programmable logic gate array and each unit; the method comprises the following steps: the video decoding unit receives the original image signal for filtering, amplifying and digital processing to generate video data; and the programmable logic gate array performs histogram statistics on the video data to obtain the result. The present invention has the characteristics of rapidity, high integration, low cost, etc.

Description

An image real-time histogram statistical device and its implementation method

technical field

The invention relates to an image processing technology, in particular to an image real-time histogram statistics device and its realization method.

Background technique

In real-time image processing, histogram statistics is an important part of image preprocessing, how to quickly and effectively perform histogram statistics is often the premise of subsequent image processing. The histogram statistics of images is based on the processing method of pixel points. At present, there are roughly two methods of implementation:

(1) Realized by software: traverse the entire image data, count the number of pixels belonging to each gray level and store them in the array C[i], where the range of i is [0, 2 ^N -1], and C[i] is gray The degree level is the number of pixels of i, and N is the number of digits of the original video signal after digitization. This method needs to occupy a certain amount of on-chip register resources, and it takes time to make statistics, which is not conducive to real-time image processing.

(2) Realized by hardware: The hardware circuit is generally composed of RAM, adder, address register and clock controller. This method is usually realized by small-scale integrated circuits. Due to the delay of signal transmission between each chip, the processing time is increased, the reliability is reduced, and it also brings difficulties for debugging and subsequent circuit improvement and upgrading.

Contents of the invention

Aiming at the deficiencies of the existing image processing technology, such as long time-consuming, reduced reliability, difficulty in debugging and subsequent circuit improvement and upgrading, the technical problem to be solved by the present invention is to provide a low-cost A low-cost, high-flexibility image real-time histogram statistical device and a realization method thereof.

In order to solve the problems of the technologies described above, the technical solution adopted in the present invention is:

The image real-time histogram statistical device of the present invention includes: a video decoding unit, which receives the original image signal and performs filtering, amplification and digital processing to generate video data;

The programmable logic gate array is the control core, receives the video data output by the video decoding unit, and performs histogram statistics on the video data;

program memory for storing the application program of the programmable logic gate array;

The clock management unit provides the required clock for the programmable logic gate array and the video decoding unit;

The reset management unit provides a reset signal for the programmable logic gate array;

The power management unit provides the required power for the programmable logic gate array and each unit.

The programmable logic gate array includes:

The on-chip phase-locked loop module receives the clock signal of the clock management unit and the reset signal of the reset management unit, and generates a pixel clock as the pixel clock of the histogram statistical state control module, image processing area selection module and histogram statistical data clearing control module ; Generate the quadruple frequency clock of the pixel clock as the read and write clock of the three-port RAM and the write clock of the histogram statistical state control module;

The image processing area selection module receives the line and field synchronization signals and image data of the video decoding unit according to different image input formats, selects the image data in the area to be processed and the effective signal of the processing area and outputs them to the histogram statistics state control module, selects the required The image pixel coordinates in the processing area are output to the histogram statistical data zeroing control module;

The histogram statistical state control module receives the line and field synchronization signals of the video decoding unit, the temporary statistical data output by the A port of the three-port RAM, the image data selected by the image processing area selection module and the effective signal of the processing area, and selects according to the image processing area The effective signal of the processing area selected by the module performs cumulative processing on the image data and temporary statistical data, and sends the processing result to the write data terminal of the three-port RAM through the first histogram statistical data multiplexing control module; generates read address data and read use The enable signal is sent to the read address terminal and the read enable terminal of the A port of the three-port RAM; the write address data and write enable signal for statistics are generated and sent to the 2nd and 3rd histogram statistical data multiplex control modules respectively. The write address terminal and write enable terminal of the A port of the three-port RAM;

The histogram statistical data clearing control module receives the line and field synchronous signals of the video decoding unit, and generates write address data and write enabling signals for clearing according to the image pixel coordinates output by the image processing area selection module through the 2nd, 2nd, and 2nd, respectively. 3 The histogram statistical data multiplex selection control module is sent to the write address end and the write enable end of the A port of the three-port RAM;

The first to third histogram statistical data multiplexing control modules, the control terminal signal comes from the field synchronization signal of the video decoding unit.

The device of the present invention also includes:

The digital signal processing unit reads the histogram statistical data processed by the programmable logic gate array and the application program of the program memory, and further processes the histogram statistical data;

The data memory is used to store the temporary data generated by the digital signal processing unit during processing.

The digital signal processing unit generates the read address data and the read enable signal, and reads the histogram statistical data through the B port of the three-port RAM; generates a data read end signal and sends it to the histogram statistical data clearing control module.

The device of the present invention also has a video encoding unit, which converts the digital video data processed by the programmable logic gate array into an analog video signal and outputs it for display.

The realization method of image real-time histogram statistical device of the present invention comprises the following steps:

The video decoding unit receives the original image signal for filtering, amplification and digital processing to generate video data;

The video data is subjected to histogram statistics by the programmable logic gate array to obtain statistical results.

Carrying out histogram statistics on video data comprises the following steps:

The image processing area selection module receives video data according to different image input formats output by the video decoding unit, generates video data and pixel coordinate positions in the area to be processed, and generates an effective signal in the processing area;

The histogram statistical state control module generates the read/write address data and read/write enable signal of the three-port RAM according to the video data, the pixel coordinate position and the effective signal of the processing area;

The histogram statistical state control module utilizes the above-mentioned read/write address data and the read/write enable signal to read in temporary histogram statistical data from the three-port RAM within one pixel clock cycle;

In the histogram statistical state control module, the above-mentioned temporary histogram statistical data is added to the operation;

The histogram statistical state control module writes the data added by 1 back to the three-port RAM.

The inventive method also comprises the following steps:

The digital signal processing unit reads the statistical results from the three-port RAM, performs subsequent processing, and generates a read end signal at the same time;

The histogram statistical data clearing control module clears the three-port RAM according to the above read end signal.

The present invention has the following beneficial effects and advantages:

1. Rapidity. The invention uses the on-chip clock phase-locked loop in the programmable logic gate array to use the quadruple frequency clock of the pixel clock as the processing clock of the synchronous finite state machine and the three-port RAM, completes the statistical process of the pixels within one pixel clock, and realizes the histogram in real time. Graph statistics provide a good foundation for other subsequent image processing algorithms.

2. High integration. Considering the real-time performance of image processing, the present invention adopts a high-speed field programmable logic gate array as the hardware platform. The input and output interface reduces the complexity of the connection of peripheral devices and has the characteristics of high integration.

3. Reduce costs. The method of the invention occupies few logic units and memories inside the programmable logic gate array, and lays a foundation for realizing more complex image processing algorithms on the single-chip programmable logic gate array.

Description of drawings

Fig. 1 is the schematic diagram of the circuit structure of the image real-time histogram statistical device;

Fig. 2 is a schematic diagram of the hardware structure for realizing histogram statistical calculation inside the programmable logic gate array.

Detailed ways

As shown in Figure 1, the image real-time histogram statistical device of the present invention includes a video decoding unit U4, which receives the original image signal for filtering, amplification and digital processing, generates video data and sends it to the programmable logic gate array U6, the programmable logic gate array U6 (the present embodiment adopts EP1C12) is the control core of the device of the present invention, and it receives the video data that video decoding unit U4 outputs and carries out histogram statistics; Program memory U7 (FLASH) is used for storing the application program of programmable logic gate array U6, After the programmable logic gate array U6 is powered on, its application program is configured in the programmable logic gate array U6; the clock management unit U2 provides the required working clock for the programmable logic gate array U6 and the video decoding unit U4; reset management The unit U3 provides reset signals for the programmable logic gate array U6; the power management unit U1 provides the required working power for the programmable logic gate array U6 and each unit.

The device of the present invention also has a digital signal processing unit U9 (the present embodiment adopts TMS320LF2407) and a data memory U8 (SRAM), wherein the digital signal processing unit U9 reads the histogram statistical data processed by the programmable logic gate array U6 through the data bus and the application program of the program memory U7 to perform further subsequent processing on the histogram statistical data; the data memory U8 is used to store the temporary data generated by the digital signal processing unit U9 during the processing.

The programmable logic gate array U6 includes an on-chip phase-locked loop module U10, an image processing area selection module U12, a histogram statistical state control module U11, a histogram statistical data clearing control module U13, a three-port RAM U14 and the first to 3 Histogram statistical data multiplex selection control modules U15-U17, wherein:

The on-chip phase-locked loop module U10 is used to receive the clock signal of the clock management unit U2 and the reset signal of the reset management unit U3, and generate a pixel clock as the histogram statistical state control module U11, the image processing area selection module U12 and the histogram statistical data clearing module U11. The pixel clock of the zero control module U13; the quadruple-frequency clock that generates the pixel clock is used as the read and write clock of the three-port RAM U14 and the write clock of the histogram statistical state control module U11;

The image processing area selection module U12 receives the line and field synchronization signals and image data of the video decoding unit U4 according to different image input formats, selects the image data in the area to be processed and the effective signal of the processing area and outputs them to the histogram statistics state control module U11, Select the image pixel coordinates in the area to be processed and output to the histogram statistical data clearing control module U13;

The histogram statistical state control module U11 is used to receive the line of video decoding unit U4, the field synchronous signal, the temporary statistical data of the A port output of three-port RAM U14, the image data and the effective signal of the processing area selected by the image processing area selection module U12, According to the effective signal of the processing area selected by the image processing area selection module U12, the temporary statistical data is processed by adding 1, and the processing result is sent to the write data end of the three-port RAMU 14 through the first histogram statistical data multiplex selection control module U15; The read address data and the read enable signal are sent to the read address end and the read enable end of the A port of the three-port RAMU14; the write address data and write enable signal used for statistics are generated through the second and third histogram statistics data respectively. Road selection control modules U16, U17 are sent to the write address end and the write enable end of the A port of the three-port RAMU14;

The histogram statistical data clearing control module U13 is used to receive the line and field synchronous signals of the video decoding unit U4, and generates write address data and write enable signals for clearing according to the image pixel coordinates output by the image processing area selection module U12 The 2nd, 3rd histogram statistical data multiplex selection control modules U16, U17 are sent to the write address end and the write enable end of the A port of the three-port RAMU14;

The three-port RAM (U14) has a write port and two read ports (A, B ports), wherein the write port is used for writing temporary histogram data during the histogram statistics process and writing 0 values during the clearing process, The A port is used for reading out the temporary histogram data during the histogram statistics process, and the B port is used for reading out the final histogram data by the digital signal processing unit U9. The device of the present invention configures the RAM as a three-port RAM, which reduces the complexity of the bus connection compared with a dual-port RAM, and can adapt to the size of images to be processed in practical applications by adjusting the data bit width of the three-port RAM.

The control terminal signals of the first to third histogram statistical data multiplexing control modules U15 to U17 all come from the field synchronization signal of the video decoding unit U4.

The digital signal processing unit U9 is set for the follow-up processing of the histogram statistical results, which generates read address data and read enabling signals, and reads the histogram statistical data through the B port of the three-port RAMU 14; generates data read end signals and sends them to To the histogram statistical data clearing control module U13.

The device of the present invention is also provided with a video encoding unit U5, which converts the digital video data processed by the programmable logic gate array U6 into an analog video signal and outputs it for display, so as to facilitate observation.

The realization method of image real-time histogram statistical device of the present invention comprises the following steps:

The video decoding unit U4 receives the original image signal for filtering, amplification and digital processing to generate video data;

The histogram statistics of the video data is performed by the programmable logic gate array U6 to obtain statistical results.

Carrying out histogram statistics on video data comprises the following steps:

The image processing area selection module U12 receives video data according to the different image input formats output by the video decoding unit U4, generates video data and pixel coordinate positions in the area to be processed, and generates an effective signal for the processing area;

The histogram statistical state control module U11 generates the read/write address data and the read/write enable signal of the three-port RAM U14 according to the video data, the pixel coordinate position and the effective signal of the processing area;

The histogram statistical state control module U11 uses the above-mentioned read/write address data and read/write enable signal to read in temporary histogram statistical data from the three-port RAMU14 within one pixel clock cycle;

In the histogram statistical state control module U11, the above-mentioned temporary histogram statistical data is added to the operation;

The histogram statistical state control module U11 writes the data added by 1 back to the three-port RAMU 14.

The whole process of the realization method of the present invention is completed by a synchronous finite state machine of "one hot" (one_hot) encoding, which is implemented in the histogram statistical state control module U11, and the following four steps are required for each statistical operation of one pixel: state:

Idle state IDLE: When the effective signal of the processing area arrives, the write address and write enable signal are established, the read address and read enable signal are cleared, and the state is transferred to the read state at the same time; if the effective signal of the processing area does not arrive, the original state is maintained ;

Read state READ: read operation, and the state transfers to the accumulative state at the same time;

Accumulation state SUM: perform data plus 1 operation, establish read address, read enable signal, clear write address, write enable signal, and state transfer to write state at the same time;

Write state WRITE: perform a data write-back operation (that is, write temporary statistical data back into the three-port RAMU14), and at the same time, the state shifts to an idle state to wait for the next data to arrive.

The realization method of the present invention also comprises the following steps:

The digital signal processing unit U9 reads the statistical results obtained by the three-port RAM U14, and performs subsequent processing (such as image grayscale stretching, image contrast enhancement, and image filtering, etc.), and simultaneously generates a read end signal;

The histogram statistical data clearing control module U13 clears the three-port RAMU 14 according to the above-mentioned read end signal.

The above steps are also set for the subsequent processing of the image.

Claims (8)

1. A kind of image real-time histogram statistics device, it is characterized in that comprising: The video decoding unit (U4) receives the original image signal for filtering, amplification and digital processing to generate video data; Programmable logic gate array (U6), is control core, receives the video data that video decoding unit (U4) outputs, carries out histogram statistics to video data; Program memory (U7) for storing the application program of the programmable logic gate array (U6); The clock management unit (U2) provides the required clock for the programmable logic gate array (U6) and the video decoding unit (U4); The reset management unit (U3) provides a reset signal for the programmable logic gate array (U6); The power management unit (U1) provides the required power for the programmable logic gate array (U6) and each unit. 2. by the described image real-time histogram statistics device of claim 1, it is characterized in that: described programmable logic gate array (U6) inside comprises: The on-chip PLL module (U10) receives the clock signal from the clock management unit (U2) and the reset signal from the reset management unit (U3), and generates a pixel clock as the histogram statistical state control module (U11), image processing area selection module (U12) and the pixel clock of the histogram statistical data clearing control module (U13); the quadruple frequency clock that produces the pixel clock is used as the read-write clock of the three-port RAM (U14) and the histogram statistical state control module (U11) write clock; The image processing area selection module (U12) receives the line and field synchronization signals and image data of the video decoding unit (U4) according to different image input formats, selects the image data in the area to be processed and the effective signal of the processing area to output to the histogram statistics The state control module (U11), selects the image pixel coordinates in the area to be processed and outputs to the histogram statistical data clearing control module (U13); Histogram statistical state control module (U11), receives the line of video decoding unit (U4), the temporary statistics data that the A port output of three-port RAM (U14), the image that image processing region selection module (U12) selects Data and effective signals in the processing area, according to the effective signals in the processing area selected by the image processing area selection module (U12), the image data and temporary statistical data are accumulated and processed, and the processing results are passed through the first histogram statistical data multiplex selection control module (U15 ) is sent to the write data end of the three-port RAM (U14); the read address data and the read enable signal are sent to the read address end and the read enable end of the A port of the three-port RAM (U14); the write data for statistics is generated Address data and write enable signal are sent to the write address end and the write enable end of the A port of the three-port RAM (U14) through the second and third histogram statistical data multiplexing control modules (U16, U17) respectively; Histogram statistical data clearing control module (U13), receives the line of video decoding unit (U4), the synchronous signal of field, produces the write address data for clearing according to the image pixel coordinates of image processing area selection module (U12) output, The write enable signal is sent to the write address end and the write enable end of the A port of the three-port RAM (U14) through the second and third histogram statistical data multiplexing control modules (U16, U17) respectively; The first to third histogram statistical data multiplexing control modules (U15 to U17), the control terminal signal comes from the field synchronization signal of the video decoding unit (U4). 3. by the image real-time histogram statistical device described in claim 1 or 2, it is characterized in that also comprising: The digital signal processing unit (U9) reads the histogram statistical data processed by the programmable logic gate array (U6) and the application program of the program memory (U7), and further processes the histogram statistical data; A data memory (U8) for storing temporary data generated by the digital signal processing unit (U9) during processing. 4. by the described image real-time histogram statistics device of claim 3, it is characterized in that: digital signal processing unit (U9) produces read address data and read enabling signal, reads in histogram by the B port of three-port RAM (U14) Graph statistical data; generate a data read end signal and send it to the histogram statistical data clearing control module (U13). 5. by the described image real-time histogram statistics device of claim 1, it is characterized in that: also have video coding unit (U5), it will be converted into analog video by the digital video data after programmable logic gate array (U6) process signal and output the display. 6. A method for realizing an image real-time histogram statistics device, characterized in that it comprises the following steps: The video decoding unit (U4) receives the original image signal for filtering, amplification and digital processing to generate video data; The histogram statistics of the video data is performed by the programmable logic gate array (U6), and the statistical results are obtained. 7. The image real-time histogram statistics device according to claim 6, characterized in that: said carrying out histogram statistics to video data comprises the following steps: The image processing area selection module (U12) outputs different image input formats according to the video decoding unit (U4) to receive video data, generates video data and pixel coordinate positions in the area to be processed, and generates an effective signal for the processing area; The histogram statistical state control module (U11) generates the read/write address data and the read/write enable signal of the three-port RAM (U14) according to the video data, the pixel coordinate position and the effective signal of the processing area; The histogram statistical state control module (U11) utilizes the above-mentioned read/write address data and the read/write enable signal to read in temporary histogram statistical data from the three-port RAM (U14) within one pixel clock cycle; In the histogram statistical state control module (U11), the above-mentioned temporary histogram statistical data is added to the operation; The histogram statistical state control module (U11) writes the data added by 1 back to the three-port RAM (U14). 8. by the image real-time histogram statistical device of claim 7, it is characterized in that: also comprise the following steps: The digital signal processing unit (U9) reads the statistical results from the three-port RAM (U14), performs subsequent processing, and generates a read end signal; The histogram statistical data clearing control module (U13) clears the three-port RAM (U14) according to the above-mentioned read end signal.

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