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CN101465301A - 晶片水平的芯片级封装 - Google Patents

晶片水平的芯片级封装 Download PDF

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Publication number
CN101465301A
CN101465301A CNA2008101839329A CN200810183932A CN101465301A CN 101465301 A CN101465301 A CN 101465301A CN A2008101839329 A CNA2008101839329 A CN A2008101839329A CN 200810183932 A CN200810183932 A CN 200810183932A CN 101465301 A CN101465301 A CN 101465301A
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chip
wafer
chips
semiconductor
semiconductor chip
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孙明
冯涛
弗兰茨娃·赫尔伯特
何约瑟
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Alpha and Omega Semiconductor Ltd
Alpha and Omega Semiconductor Inc
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Alpha and Omega Semiconductor Inc
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Abstract

本发明公开了一种在晶片水平芯片级封装工艺中制造背部与前部之间电连接的方法。一包含多个半导体芯片的晶片被安装在封装衬底上。多个半导体芯片中的每一个都包括一个或多个位于暴露背部的电极。去除位于晶片上的两个或多个相邻芯片之间的划线部分，形成相对宽的沟槽。导体材料被应用到半导体芯片背侧及沟槽中。然后切割位于两个或多个芯片之间的沟道中的导体材料，仅将导体材料留在两个或多个芯片的背侧及四壁上。最终，导电材料提供了从芯片背部上的电极到芯片前部的电连接。本发明的优点在于允许真正的晶片层级的半导体器件芯片规模封装工艺，并具有最小附加成本，从而可以批量处理而且减少生产线的设备需求也可以降低成本。

Description

晶片水平的芯片级封装
技术领域
本发明涉及半导体封装领域，更特别的是涉及低成本的晶片水平芯片级封装工艺。
背景技术
低封装电阻Rds-on和好的性能是半导体器件所追求的。尤其是在金属氧化硅场效应晶体管(MOSFET)的情况中，特别的，垂直导通功率MOSFET器件具有位于同一个表面上的栅极和源极以及位于相反表面上的漏极。通常也希望具有简单、快速、高效的半导体器件封装方法。因此，现有技术中已经提出了许多封装的概念和方法。
在过去的十年间硅制程技术取得了显著的进步，而在同样的十年间，封装技术仍然沿用原先的封装方法。环氧树脂或焊料芯片沿铝或金键合线附贴到引线框架上仍然是优选的半导体封装方法。然而，在改进的半导体制程技术中，产生了许多与常见封装相关的寄生物(如电阻、电容和电感)，从而成为性能限制因素。在现有的倒装芯片技术中，众多缺点之中，热耗散受限于芯片尺寸，而且芯片背面的连接(通常需要键合线)是难以达到的。这些限制(散热困难和连接背面的阻力)在例如功率开关器件这样的高电流的应用中变得十分明显。
美国专利6,767,820公开了一种半导体MOS栅极器件的规模封装工艺。MOS栅极器件晶片的源极侧覆盖有一钝化层，优选感光液体环氧树脂，或氮化硅层，或其他类似的材料。材料干燥后，使用标准光刻技术图案化有覆盖层的晶片，在钝化层上形成若干开口，从而在晶片上的每一个芯片上的源极金属的下面产生若干个相互分离暴露表面区域，还形成类似的开口用以暴露每个芯片的栅极下部。钝化层上的开口通常设置为穿过普通的下部可焊顶部金属层，例如钛、钨、镍或银。在开口形成后，晶片被锯开或以别的方式分割为独立芯片。然后将独立芯片的源极侧朝下，U型或杯型的部分电镀的漏极夹片通过导电环氧树脂或焊料连接到芯片的可焊漏极侧，或类似地连接漏极夹片到芯片的底部漏极。漏极夹片引脚的底部与源极侧表面(为连接突出物的顶部)处于同一平面。然而，U型夹片通常使用铜合金制成，并至少带有部分镀银表面，而且实际上非常薄。因此，此类U型夹片相当昂贵。另外，不同的芯片尺寸需要不同的U型夹片，又或者较小的芯片使用了较大的U型夹，这就占据了更多的集成电路板空间。
美国公开号为2003/0052405的美国专利公开了一种垂直功率MOSFET器件，该器件具有通过例如焊料这样的键合材料连接到引线框架的源极和栅极，而位于整个芯片底部表面之下的漏极则直接连接到其所在的衬底。该垂直MOSFET器件其上部朝下设置，从而形成于硅衬底底部表面上的漏极会连接到其上的引线框架，而栅极和源极则开设在器件的底部。MOSFET器件由例如环氧树脂或硅的树脂封口，这样可以覆盖MOSFET器件和引线框架的内部部分。在MOSFET器件的底部表面上，树脂表面大致充满引线框架和漏极表面。在半导体器件的底部表面上暴露出引线框架外部引脚部分的底部表面以及底部表面漏极用以连接所在衬底的导电部分(置于表面)，随后，漏极的周围就被树脂覆盖。
美国专利号为6,133,634的美国专利公开了一种功率MOSFET器件的覆晶封装结构，包括一漏极端，一源极端和一栅极端。漏极端连接导电载体和一系列外部焊球。源极端和栅极端连接一系列内部焊球。导电载体和外部焊球系列提供印刷电路板与漏极端之间的电连接。
专利号为6,469,384的美国专利公开了一种封装例如MOSFET器件这样的半导体器件的方法，其不需要模体(molded body)。MOSFET器件与衬底连接，从而使芯片的源极与栅极区域与衬底连接。MOSFET器件置于一印刷电路板(PCB)上，芯片表面通过焊膏或合适的导电内连接直接连接PCB，这也就可以作为漏极连接。连接到衬底的芯片表面包括芯片的栅极区域和源极区域。从而，在衬垫栅极区域中的焊球将芯片栅极区域耦合到PCB，而剩余的焊球将芯片的源极区域通过衬底耦合到PCB。
现有的垂直MOSFET器件的封装设计每次仅能提供一个独立MOSFET上源极，栅极和漏极的内部电连接，这是昂贵且耗时的。另外，可用的芯片空间也会减少。因此需要提供一种制造的封装设计及方法，其可以批量处理从而减少生产线的设备需求也可以降低成本。
本文中将提供本发明的具体实施方式。
发明内容
本发明的目的在于公开了一种在晶片水平芯片级封装工艺中制造背部与前部之间的电连接的方法，包括：a)在封装衬底上安装包括多个半导体芯片的晶片，其中每一个半导体芯片都包括一个或多个位于暴露的背部的电极；b)去除两个或多个相邻芯片之间的划线部分，以在其间形成相对宽的沟槽；c)在半导体芯片的背侧及沟槽中设置导电材料；d)以及切割位于两个或多个芯片之间的沟槽中的导电材料，只将导电材料留在两个或多个芯片的背部及侧壁上。以此，导电材料就提供了从芯片背部上的电极到芯片前部的电连接。
所述的多个半导体芯片中的每一个都包括图案化为基板栅格阵列(LGA)的前表面。
其中步骤a)包括使用厚刃晶片锯去除两个或多个相邻芯片之间的划线部分。其中所述的厚刃晶片锯的刃的厚度为80μm至100μm。
所述的导体材料包括导电环氧树脂或导电填充材料。
所述的步骤d)包括使用薄刃晶片锯切割两个或多个芯片之间的导体材料；其中薄刃晶片锯的刃的厚度为20μm至30μm。
所述的数个半导体芯片包括一个或多个垂直金属氧化硅场效应晶体管(MOSFET)，所述的一个或多个垂直金属氧化硅场效应晶体管包括一个或多个沟槽MOSFET，其中一个或多个位于暴露背侧的电极包括一个或多个漏极。
所述的一个或多个位于暴露背侧的电极组成一标准背侧金属或晶片衬底上的暴露的背侧部分。
还包括在去除所述划线部分之前，对暴露的背侧部分进行掺杂及退火，以及还包括在应用导体材料之前，清洁晶片表面。
一种芯片级半导体封装结构，包括：一功率半导体芯片，包括一个或多个位于其背部及其前部的电极；一层覆盖于所述半导体芯片背侧和所述半导体芯片侧壁上的导体材料，以形成封装的最外层表面，其中导体材料层的侧面还延伸到所述芯片前侧的边缘。
所述的导体材料层覆盖所述半导体芯片的四个侧壁。
其中所述的前侧面图案化为基板栅格阵列。
所述的半导体芯片包括垂直MOSFET。
所述的半导体芯片包括横向MOSFET芯片，其具有底部栅极和漏极以及开设于顶部的源极。
所述的半导体芯片包括绝缘栅双极型晶体管(IGBT)。
本发明的优点在于提供了一种制造的封装设计及方法，允许真正的晶片层级的半导体器件芯片规模封装工艺，并具有最小附加成本，从而可以批量处理而且减少生产线的设备需求也可以降低成本。
附图说明
本发明的其它内容及优点在阅读了后续的具体实施方式并参考下列相应附图后得以体现：
图1A-1E所示为一种晶片水平芯片级封装工艺，其中，在沟槽MOSFET的漏极侧具有电连接。
图2是图1A-1E中所示的晶片水平芯片级封装工艺的流程图。
图3所示为使用图1A-1E中的工艺制作的具有漏极电连接的沟槽MOSFET的侧视图。
具体实施方式
尽管后续的详细叙述包括许多意在解释本发明的特殊细节，任何本领域的普通技术人员都会认识到许多对于所述细节的变化和代替都属于本发明的范围。相应的，下文中所叙述的本发明的具体实施例对所要求的发明内容概要没有任何的缺失，也没有对其强加任何限制。
依照本发明的一个具体实施例的制作内部电连接的方法如图1A至1E及图2所示。图1A至1E一系列图示，其用于说明图2所示的流程图中描述的方法200。在本例中，内部电连接形成于以晶片水平芯片级封装工艺(CSP)封装的沟槽MOSFET的漏极侧。
参考图2，方法200开始于步骤202，将器件安装在封装衬底上。举例来说，如图1A所示，半导体晶片100包括若干个图案化于其表面的半导体芯片102，例如垂直MOSFET，该芯片由晶片制作过程制备。每一个芯片包括一个暴露于顶部的背面漏极107。背面漏极107可以由标准背面材料构成，例如钛镍银合金、铬金合金、钛金合金等。也可以选择不使用金属，而使用晶片100的衬底的背面暴露部分作为电极107。暴露的背面晶片衬底也可以进行掺杂和退火，以减少与后续制程中加入的导电材料层110之间的连接电阻。划线104部分将半导体晶片100分割为若干个半导体芯片102。晶片100安装在封装衬底101上。例如，当晶片100被安装到载体上时，可以采用带状安装。如果晶片100安装在一真空卡盘上，则可选择通过真空安装。半导体芯片102可以包括一图案化为基板栅格阵列(LGA)的前表面。如图2中所示的步骤204，晶片可以通过在器件之间形成比较宽的沟道来分隔成各个部分。举例来说，在两个半导体芯片102之间的划线104可以通过使用如图1B中所示的厚刀片状晶片锯106去除，以形成位于两个半导体芯片102之间的沟槽108。厚刀片状晶片锯106的刀刃厚度大约为80μm至100μm。
如图2中所述的步骤206，导体材料110可以覆盖在器件上并填充器件间的沟槽。导体材料110覆盖半导体芯片102的四个侧壁。例如，如图1C所示，用形成导体材料110的导体环氧树脂填入沟槽108并覆盖漏极107的顶部和半导体芯片102的侧面。举例来说，导体材料110可以是碳材料，如纳米碳或碳纳米管。导体材料110也可以选择导体粘合剂、导体环氧树脂、焊锡及其它类似的物质。导体材料110设置于半导体芯片102的背面及侧壁，以而提供从芯片102背面上的漏极107到芯片正面的电连接。在本例中，背部电极107由晶片衬底而非金属构成，所以需要在沉积导体金属110之前进行清洁步骤，以此来减少有可能会形成在晶片表面的任何杂质或氧化物，从而确保背部电极107与导体材料110之间具有较好的连接。清洁溶液可以包括稀释氢氟、溶剂、蒸汽氢氟等。
如图2中步骤206所述，通过切割位于器件之间相对较宽的沟槽108中的导体材料110来实现器件的彼此分离。举例来说，半导体芯片的独立可以通过使用薄刃锯112切割位于芯片间的固化的导电材料实现，以此将晶片100分割成如图1E所示的独立半导体器件116。优选的，薄刃锯112的刃的厚度小于沟槽108的宽度，例如，如果沟槽的宽度大约为80至100微米，则薄刃锯112的刃的宽度大约为20至30微米。其结果是，覆盖于背部表面和侧壁表面的导电材料层不仅实现了从背部电极到前表面的电连接，也保护了芯片的侧面在成品电测试、封装、电路板层级设置及运输过程中免受刮伤、破损及其它化学危害。
图3所示为使用图1A-1E中的工艺制作的独立半导体器件116安装到印刷电路板(PCB)113上的电路连接。如图3所示，半导体器件116包括半导体芯片102，所述的半导体芯片102包括源极103，栅极105和漏极107，导电环氧树脂或导电填充材料109沉积到漏极107的顶部及划线槽108中。导电填充材料109可以覆盖半导体芯片102的四壁。源极103和栅极105通过焊料连接物111电连接到位于PCB113上的铜垫115。钝化或绝缘物质填充到电极103和105之间的沟槽中。焊料掩模117沉积到铜垫115之间。
本发明的具体实施方式允许真正的晶片层级的半导体器件芯片规模封装工艺(CSP)，该封装的器件背部与前部连接，并具有最小附加成本。常见的CSP系统也可以经过相对最少的修改后使用，例如，更厚的锯刃可以提供临近芯片与装置之间的沟槽，用于应用覆盖及位于芯片之间的导电材料。在本发明的具体实施方式中，通过设置开口从而在漏极连接处使用纳米碳或碳纳米管。
没有与本发明的具体实施方式相关联的最小CSP尺寸。本发明的具体实施方式中的制作工艺与芯片尺寸完全无关，也没有必要准备任何预制的导电盖或薄膜。另外，也不需要如其它技术中所要求的预刻的金属框架或用于CSP的衬底和焊料突起。
本发明的具体实施方式允许在很简单的晶片层级CSP制程中提供背部与前面的电连接。该制程不需要背部到前面的漏极连接的装配步骤。作为比较，在现有技术的制程中，所使用的装配步骤需要更多的材料消耗及装置。
另外，所述的制程可以相当灵活的应用于任何芯片尺寸，对于不同尺寸的芯片无需作出加工变化。作为比较，现有技术中对不同尺寸的芯片，不是要求加工新的金属框架，就是要改变球栅阵列封装(BGA)掩模，另外设备转换装置也需要变化，所有这些都耗费巨大。此外，在现有技术中许多晶片水平芯片级封装工艺的结构与制程中，由于晶片与晶片背部覆盖材料之间的热涨不吻合而造成的晶片翘曲的难题在这里就不再需要关注了，因为在上述的制程中，将晶片切割为小芯片之后才将其用导电材料进行覆盖。这大大降低了晶片和覆盖材料之间热涨不吻合的可能性。
在此所述的制程可以应用于任何垂直半导体器件。这也应用于任何在顶部及底部开设有导电区域的横向半导体器件，例如绝缘栅双极型晶体管(IGBT)或底部源极横向双扩散MOSFET(BS-LDMOSFET)。BS-LDMOSFET具有位于底部的栅极和漏极以及可设于顶部的源极(衬底)。
由于上述是对于本发明的优选实施方式的完整叙述，其可以做出各种各样的选择，修改和等价替换。因此，本发明的范围不应取决于上述的内容，而应当取决于附后的权利要求及其所有等价的范围。任何优选或非优选的特征都可以与其它优选或非优选的特征组合。在后附的权利要求中，除非有其它明确的说明，定冠词“一”指的是一个或更多的所述对象的数量。权利要求不能被解释为包括方法加功能的限制，除非在所给出的权利要求中以“其方法为”作出明确的叙述。

Claims (21)

1、一种在晶片水平芯片级封装工艺中制造背部与前部之间的电连接的方法，包括：
a)在封装衬底上安装包括多个半导体芯片的晶片，其中每一个半导体芯片都包括一个或多个位于暴露的背部的电极；
b)去除两个或多个相邻芯片之间的划线部分，以在其间形成相对宽的沟槽；
c)在半导体芯片的背侧及沟槽中设置导电材料；以及
d)切割位于两个或多个芯片之间的沟槽中的导电材料，只将导电材料留在两个或多个芯片的背部及侧壁上，
以此，导电材料就提供了从芯片背部上的电极到芯片前部的电连接。
2、如权利要求1所述的方法，其特征在于，其中所述的多个半导体芯片中的每一个都包括图案化为基板栅格阵列的前表面。
3、如权利要求1所述的方法，其特征在于，其中步骤a)包括使用厚刃晶片锯去除两个或多个相邻芯片之间的划线部分。
4、如权利要求3所述的方法，其特征在于，其中厚刃晶片锯的刃的厚度为80μm至100μm。
5、如权利要求1所述的方法，其特征在于，其中导体材料包括导电环氧树脂。
6、如权利要求1所述的方法，其特征在于，其中导体材料包括导电填充材料。
7、如权利要求1所述的方法，其特征在于，其中步骤d)包括使用薄刃晶片锯切割两个或多个芯片之间的导体材料。
8、如权利要求7所述的方法，其特征在于，其中薄刃晶片锯的刃的厚度为20μm至30μm。
9、如权利要求1所述的方法，其特征在于，其中数个半导体芯片包括一个或多个垂直金属氧化硅场效应晶体管。
10、如权利要求9所述的方法，其特征在于，其中所述的一个或多个垂直金属氧化硅场效应晶体管包括一个或多个沟槽金属氧化硅场效应晶体管。
11、如权利要求9所述的方法，其特征在于，其中一个或多个位于暴露背侧的电极包括一个或多个漏极。
12、如权利要求1所述的方法，其特征在于，其中一个或多个位于暴露背侧的电极组成一标准背侧金属。
13、如权利要求1所述的方法，其特征在于，其中一个或多个位于暴露背侧的电极组成晶片衬底上的暴露的背侧部分。
14、如权利要求13所述的方法，其特征在于，还包括在去除所述划线部分之前，对暴露的背侧部分进行掺杂及退火。
15、如权利要求13所述的方法，其特征在于，还包括在应用导体材料之前，清洁晶片表面。
16、一种芯片级半导体封装结构，包括：
一功率半导体芯片，包括一个或多个位于其背部及其前部的电极；
一层覆盖于所述半导体芯片背侧和所述半导体芯片侧壁上的导体材料，以形成封装的最外层表面，
其中导体材料层的侧面还延伸到所述芯片前侧的边缘。
17、如权利要求16所述的封装结构，其特征在于，其中所述的导体材料层覆盖所述半导体芯片的四个侧壁。
18、如权利要求16所述的封装结构，其特征在于，其中所述的前侧面图案化为基板栅格阵列。
19、如权利要求16所述的封装结构，其特征在于，其中所述的半导体芯片包括垂直金属氧化硅场效应晶体管。
20、如权利要求16所述的封装结构，其特征在于，其中所述的半导体芯片包括横向金属氧化硅场效应晶体管芯片，其具有底部栅极和漏极以及开设于顶部的源极。
21、如权利要求16所述的封装结构，其特征在于，其中所述的半导体芯片包括绝缘栅双极型晶体管。
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