CN101373639A - Memory time sequence measuring circuit and testing method thereof - Google Patents

Abstract

A memory timing measurement circuit and a test method thereof. The memory timing measurement circuit performs different delays on a plurality of balanced test signals to generate a plurality of delayed test signals. Each delayed test signal is sent to one of a plurality of input pins of a memory subsystem. By adjusting the delay amount of the delayed test signal source, the AC timing parameters of the memory subsystem are tested and measured. When the timing measurement circuit is in a ring oscillation, its resolution can be measured.

Description

Memory timing measurement circuit and its testing method

technical field

The invention relates to a storage timing measurement circuit, a storage structure and a testing method thereof.

Background technique

In memory testing, how to correctly measure AC timing (AC timing) parameters is of great importance. Generally speaking, the communication timing parameters at least include: a setup time parameter, a hold time parameter and an access time parameter.

In the past, an automatic testing machine (ATE, automatic testing machine) was usually used to test the AC timing parameters. However, this leads to several disadvantages:

(1) Because the resolution of the automatic test machine is very large, it is not suitable for measuring the AC timing parameters of the memory. Generally speaking, the resolution of an automatic test machine may be as high as 350ps (pico-second, picosecond); however, the AC timing parameters of the memory may only be tens of ps. This also tends to reduce the accuracy of the measurement.

(2) The test signal sent by the automatic test machine may have errors. When transmitted to the circuit board carrying the memory to be tested, the test signal will pass through the wiring and signal lines on the circuit board, which will cause greater error (signal variation).

(3) It is not easy to know the real timing measurement value in the timing measurement. This is because the timing measurement value can only be obtained by the automatic test machine, but the signal timing inside the memory can only be inferred from the measurement signal sent by the automatic test machine.

(4) Since the test signal, the control signal and the clock signal are all sent from the outside of the memory, the number of pins of the memory will be very high and the chip area will be increased.

In order to improve the above shortcomings, the present invention proposes a memory timing measurement circuit, a memory structure and a testing method thereof.

Contents of the invention

The invention provides a memory timing measurement circuit, a memory structure and a testing method thereof, which can provide high-precision timing measurement.

The invention provides a memory timing measurement circuit, a memory structure and a testing method thereof, which can reduce the number of input and output pins used for timing measurement.

The invention provides a memory timing measurement circuit, a memory structure and a testing method thereof, which can improve measurement efficiency.

The invention provides a memory timing measurement circuit, a memory structure and a testing method thereof, which can reduce the influence of the signal timing variation outside the chip on the test result.

The invention provides a memory timing measurement circuit, a memory structure and a testing method thereof, which can easily complete timing measurement.

The invention provides a storage timing measurement circuit, a storage structure and a testing method thereof, which can measure the measurement resolution of the storage timing measurement circuit.

The example of the present invention proposes a memory chip, including: a memory subsystem for storing data, which includes a plurality of pins; a clock tree, which sends out a test signal source in a balanced manner; and a timing measurement circuit, which is received by The test signal source sent by the clock tree, the timing measurement circuit respectively delays the test signal source to generate a plurality of delayed test signals, and the delayed test signals are sent to the pins of the memory subsystem and testing the memory communication timing parameter of the memory subsystem by adjusting the timing of the delayed test signal source.

Another example of the present invention provides a timing measurement circuit for a memory chip. The memory chip includes: a memory subsystem and a clock tree that sends out a test signal source in a balanced manner. The timing measurement circuit includes: a plurality of timing measurement units, and each timing measurement unit is coupled to one of the plurality of pins of the memory subsystem to measure memory parameters of the memory subsystem. Each timing measurement unit includes: a switch, having: a control terminal, receiving an external switch control signal, a first terminal, receiving the test signal source sent by the clock tree, a second terminal, receiving an external data, a The third end, and a fourth end; a plurality of series-connected delay circuits, an input end of a first-stage delay circuit of the delay circuit is coupled to the fourth end of the switch, and the last of the delay circuit The first stage will output a ring oscillator output signal, and the ring oscillator output signal represents a resolution of the timing measurement circuit; and a multiplexer has: a control terminal for receiving an external delay control signal; a plurality of The input terminal is respectively coupled to a plurality of output terminals of the delay circuit; and an output terminal is coupled to the corresponding pin of the memory subsystem. The external switch control signal controls the operation mode of the timing measurement unit, and the external delay control signal controls a time difference between the test signal source and the output signal of the multiplexer.

Another example of the present invention provides a method for testing a memory, the method comprising: sending a test signal in a balanced manner; respectively delaying the test signal to generate a plurality of delayed test signals to be input to a plurality of pins of the memory and checking whether an output data output by the memory is correct and adjusting the timing of the delayed test signal input to the pin of the memory, so as to measure an AC timing parameter of the memory.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 shows a block diagram of a memory chip with a memory timing measurement circuit according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a memory timing measurement circuit according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a timing measurement unit according to an embodiment of the present invention.

4a and 4b show signal timing diagrams of internal test signals of the memory chip according to the present invention.

Description of reference symbols

10: memory chip

11a, 11b: Memory Subsystem

12: Control circuit

13a, 13b: timing measurement circuit

14: Frequency divider

15: Multiplexer

16: Clock tree

17: Output data register

19: Automatic test machine

21a-21g: timing measurement unit

31: switch

32: Multiplexer

33a-33d: inverter pair

INV1-INV9: Inverters.

Detailed ways

In this embodiment, in order to reduce the variation of test signals outside the chip, all test signals are generated by a clock tree. The clock tree receives a single clock signal; that is, the single clock signal can be regarded as the root of the clock tree. The clock tree sends test signals to each timing measurement unit in a balanced (synchronous) manner to test AC timing parameters of the memory.

FIG. 1 shows a block diagram of a memory chip with a memory timing measurement circuit according to an embodiment of the invention. As shown in Figure 1, this memory chip 10 comprises: memory subsystem 11a and 11b, control circuit 12, timing measurement circuit 13a and 13b, frequency divider 14, multiplexer 15, clock tree 16 and output data register 17 .

The memory subsystem is used to store data, which is the object under test. Please note that although two memory subsystems 11a and 11b are shown in FIG. 1 , the number of memory subsystems included in the memory chip of the present invention is not limited thereto. Furthermore, the memory capacities of these memory subsystems are not necessarily equal. The quantity relationship between the memory subsystem and the timing measurement circuit is 1:1.

The control circuit 12 is used for controlling the timing measurement circuit and the multiplexer 15 . When the memory chip 10 includes multiple timing measurement circuits, the control circuit 12 can send appropriate control signals (such as switch control signal SW and delay control signal D_SEL) to respective timing measurement circuits.

In order to reduce the control signal pins of the memory chip 10 , the control circuit 12 may include a shift register, and the shift register includes multiple sets of registers. A set of registers is used to temporarily store and output control signals required by a timing measurement circuit. The control signal is sent from the outside to the control circuit 12 in the memory chip 10 through the control signal pin CTL_IN.

The timing measurement circuit is used to measure the AC timing parameters of the memory subsystem. Please refer to Figure 2-Figure 4 below for the detailed structure and operation of the timing measurement circuit.

The frequency divider 14 divides the frequency of the output signal RING_OUT of the timing measurement circuit. When the frequency of the output signal RING_OUT is quite high, the frequency divider 14 can properly reduce the frequency of the output signal RING_OUT. In this way, a high-frequency and high-cost measurement circuit (not shown) is not needed to directly measure the frequency of the output signal RING_OUT. The period of the output signal RING_OUT can be used to count the resolution of this timing measurement circuit.

When the memory chip 10 includes multiple timing measurement circuits, the multiplexer 15 can select which timing measurement circuit's output signal RING_OUT is to be taken out. In Figure 1, the input(s) of the frequency divider are coupled to the output(s) of the timing measurement circuit(s), and the output(s) of the frequency divider are coupled to the input(s) of the multiplexer end. Those skilled in the art should know that the coupling relationship between the multiplexer and the frequency divider is not limited to that shown in FIG. 1 . For example, the coupling relationship between the multiplexer and the frequency divider can be changed into that the multiplexer receives (multiple) output signals RING_OUT of the timing measurement circuit, and outputs one of them to the frequency divider; that is, multiple The input(s) of the multiplexer are coupled to the output(s) of the timing measurement circuit(s), and the output(s) of the multiplexer are coupled to the input(s) of the frequency divider

The clock tree 16 is used to send the test signal source T_CK to the timing measurement circuit in a balanced and synchronous manner. The structure of the clock tree 16 is not particularly limited here. For example, without limitation, clock tree 16 may include multiple buffers.

The output data register 17 is used to store the output data of the memory subsystem. By checking whether the output data is correct, it is possible to check whether the measured AC timing parameters are acceptable.

When the memory subsystem is performing a functional test, the automatic test machine 19 sends an external functional test signal D_EXT required by the memory subsystem to the timing measurement circuit. The external function test signal D_EXT includes, for example, an address signal, a data input signal, a write enable signal (WEB), an output enable signal (OE), a chip select signal (CSB), and a clock signal CK.

FIG. 2 is a schematic diagram of a timing measurement circuit according to an embodiment of the invention. The structures of the timing measurement circuits 13a and 13b are basically similar or identical. Referring now to FIG. 2, the timing measurement circuit 13a includes a plurality of timing measurement units (timing measurement units, TMUs) 21a-21g. For example, the memory subsystem includes: address signal input pin A, data input pin DI, write enable signal input pin WEB, output enable signal input pin OE, chip select signal input pin CSB, clock Signal input pin CK and data output pin DO etc.

Each timing measurement unit is coupled to one of the input pins of the memory subsystem 11a. For example, the timing measurement unit 21a is coupled to the address signal input pin A. As shown in FIG. The timing measurement unit 21b is coupled to the data input pin DI. The timing measurement unit 21c is coupled to the write enable signal input pin WEB. The timing measurement unit 21d is coupled to the output enable signal input pin OE. The timing measurement unit 21e is coupled to the chip select signal input pin CSB. The timing measurement unit 21f is coupled to the clock signal input pin CK. The timing measurement unit 21g is coupled to the data output pin DO.

Each of the timing measurement units 21a-21g can operate in different modes and apply different delays to the test signal T_CK under the control of the control signals SW and D_SEL. As shown in FIG. 2 , the timing measurement unit 21 a delays the test signal T_CK into a signal A_IN to be input to the address signal input pin A. As shown in FIG. The timing measurement unit 21b delays the test signal T_CK into a signal DI_IN to be input to the data input pin DI. The timing measurement unit 21c delays the test signal T_CK into a signal WEB_IN to be input to the write enable signal input pin WEB. The timing measurement unit 21d delays the test signal T_CK into a signal OE_IN to be input to the output enable signal input pin OE. The timing measurement unit 21e delays the test signal T_CK into a signal CSB_IN to be input to the chip select signal input pin CSB. The timing measurement unit 21f delays the test signal T_CK into a signal CK_IN to be input to the clock signal input pin CK. The timing measurement unit 21 g delays the test signal T_CK into a signal DO_IN to be input to the output data register 17 . The timing measurement unit 21g and the output data register 17 can be used to test the access time of the memory subsystem.

The operation mode and delay operation of the timing measurement unit can be understood with reference to FIG. 3 and FIG. 4 .

FIG. 3 is a schematic diagram of a timing measurement unit according to an embodiment of the present invention. The structures of the respective timing measurement units 21a-21g are basically the same or similar to each other. As shown in FIG. 3 , the timing measurement unit 21 a includes: a switch 31 , a plurality of serially connected inverter pairs, a buffer INV9 , and a multiplexer 32 . FIG. 3 takes four series-connected inverter pairs 33a-33d as an example for illustration, but the present invention is not limited thereto. The delay control signal D_SEL determines the delay of the timing measurement unit.

The switch 31 is controlled by the switch control signal SW[1:0]. According to the value of the switch control signal SW[1:0], the switch 31 has four operation modes. These four modes of operation are listed in Table 1.

Table 1

In Table 1, "x" stands for don't care.

Operation mode 1 may also be referred to as normal latency mode. In operation mode 1, the switch control signal SW[1:0] is [0, 0]. In this mode of operation, the switch 31 directs the input signal (ie the test signal T_CK) to the input terminal of the first inverter pair 33a without inversion. The delay control signal D_SEL determines the time difference between the output signal A_IN and the test signal T_CK.

The operation mode 2 may also be referred to as an inverse delay mode. In operation mode 2, the switch control signal SW[1:0] is [0, 1]. In this operation mode, the switch 31 inverts the input signal T_CK before guiding it to the input terminal of the first inverter pair 33a. Likewise, the delay control signal D_SEL determines the time difference between the output signal A_IN and the test signal T_CK.

Operation mode 3 can also be called external mode. In operation mode 3, the switch control signal SW[1:0] is [1,0]. In this operation mode, the switch 31 directs the external input signal D_EXT (provided by the automatic test machine 19 ) to the input terminal of the first inverter pair 33 a. That is to say, in this operation mode, the output signal A_IN can be regarded as a delayed address signal. The delay control signal D_SEL determines the time difference between the output signal A_IN and the external input signal D_EXT.

The operation mode 4 can also be referred to as a ring oscillator (ring oscillator) mode. In operation mode 4, the switch control signal SW[1:0] is [1, 1]. In this mode of operation, switch 31 causes inverter pair 33a ^- 33d and buffer INV9 to act as a ring oscillator. That is, the switch 31 couples the output terminal of the buffer INV9 to the input terminal of the first inverter pair 33a.

Each inverter pair includes a plurality of inverters connected in series. For example, the inverter pair 33a includes inverters INV1 and INV2 connected in series. The inverter pair 33b includes inverters INV3 and INV4 connected in series. The inverter pair 33c includes inverters INV5 and INV6 connected in series. The inverter pair 33d includes inverters INV7 and INV8 connected in series. The output terminal of each inverter pair is coupled to one of the input terminals of the multiplexer 32 and the input terminal of the next stage inverter pair. Each inverter pair can be used as a delay circuit to delay the signal.

The buffer INV9 can be used to improve the driving capability of the output signal of the last stage inverter pair. The signal RING_OUT is output by the buffer INV9.

The multiplexer 32 will determine which inverter pair's output signal is to be selected as the signal A_IN according to the delay control signal D_SEL. For example, when the multiplexer 32 selects the output signal of the inverter pair 33a as the signal A_IN, it means that the time difference between the signal A_IN and the signal T_CK is two basic delay times; one basic delay time is determined by one inverter supply. In addition, in this description, a basic delay time can also be referred to as the resolution of the timing measurement circuit.

Assume that the frequency divider is a frequency divider divided by N (N is a positive integer). When the timing measurement unit is in operating mode 4 (ring oscillation), one period of the signal RING_OUT is equal to twice the resolution. The resolution of the timing measurement circuit can be expressed as: (1/2)*(1/N)*(1/R_OUT). R_OUT represents the frequency of the output signal R_OUT of the frequency divider.

4a and 4b show signal timing diagrams of internal test signals of the memory chip according to the present invention. For simplicity, FIGS. 4a and 4b only show the timing diagrams of the test signals A_IN and CK_IN applied to the address pin A and the clock pin CK of the memory subsystem.

FIG. 4a shows a timing diagram of the test signals A_IN and CK_IN for measuring the setup time T_SETUP. As shown in FIG. 4 a , to ensure correct operation of the memory subsystem, after the test signal A_IN transitions, at least a set time T_SETUP must pass before the test signal CK_IN transitions. That is, signal A_IN leads signal CK_IN. In this embodiment, when the output data DO of the memory subsystem is still correct, the minimum setup time T_SETUP is obtained by adjusting the delay time of the timing measurement unit 21a or 21f.

FIG. 4b shows a timing diagram of the test signals A_IN and CK_IN for measuring the hold time T_HOLD. As shown in FIG. 4 b , in order to ensure correct operation of the memory subsystem, after the test signal CK_IN transitions, at least the hold time T_HOLD must pass before the test signal A_IN transitions. That is, signal A_IN lags signal CK_IN. In this embodiment, when the output data DO of the memory subsystem is still correct, the minimum hold time T_HOLD is obtained by adjusting the delay time of the timing measurement unit 21a or 21f.

In the prior art, the test signal is generated by an external automatic test machine and sent to the memory chip to be tested. Therefore, if the timing variation or error of the external test signal will affect the accuracy of the test. In this embodiment, the test signal is generated inside the memory chip, so the test accuracy and efficiency can be improved.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and changes without departing from the spirit and scope of the present invention. Modification, so the scope of protection of the present invention should be defined by the patent scope of the present invention.

Claims (13)

1. A memory chip, comprising: A memory subsystem for storing data, including a plurality of pins; a clock tree that feeds out a test signal source in balance; and A timing measurement circuit, receiving the test signal source sent by the clock tree, the timing measurement circuit respectively delays the test signal source to generate a plurality of delayed test signals, and the delayed test signals are sent to the memory The pins of the subsystem test the memory communication timing parameters of the memory subsystem by adjusting the timing of the delayed test signal source. 2. The memory chip as claimed in claim 1, further comprising: A control circuit is used for controlling the operation mode of the timing measurement circuit and the delay amount of the delayed test signal. 3. The memory chip as claimed in claim 1, further comprising: A frequency divider receives and divides a ring oscillator output signal output by the timing measurement circuit. 4. The memory chip as claimed in claim 3, wherein when the memory chip comprises a plurality of timing measurement circuits, a plurality of ring oscillator output signals of the timing measurement circuits are coupled to the frequency divider, and the memory chip Also includes: A multiplexer, coupled to the frequency divider, is used to select one of the ring oscillator output signals of the timing measurement circuit. 5. The memory chip of claim 1, further comprising: An output data register receives an output data of the memory subsystem. 6. The memory chip of claim 4, wherein each timing measurement unit is coupled to one of the pins of the memory subsystem. 7. The memory chip as claimed in claim 6, wherein each timing measurement unit comprises: a switch, the operation mode of which is determined according to a switch control signal; A plurality of series-connected delay circuits, an input end of each delay circuit is coupled to an output end of the switch or an output end of the previous stage delay circuit, and the last stage of the delay circuit outputs the ring oscillator output signal ;as well as A multiplexer receives multiple outputs of the delay circuit and generates the delayed test signal to the corresponding pin of the memory subsystem. 8. A timing measurement circuit of a memory chip, the memory chip comprising: a memory subsystem and a clock tree that sends a test signal source in balance; the timing measurement circuit comprises: A plurality of timing measurement units, each timing measurement unit is coupled to one of the plurality of pins of the memory subsystem to measure memory parameters of the memory subsystem; each timing measurement unit includes: A switch has: a control terminal for receiving an external switch control signal, a first terminal for receiving the test signal source sent by the clock tree, a second terminal for receiving external data, a third terminal, and a fourth end; a plurality of series-connected delay circuits, an input end of a first-stage delay circuit of the delay circuit is coupled to the fourth end of the switch, and the last stage of the delay circuit outputs a ring oscillator output signal, the ring oscillator output signal is indicative of a resolution of the timing measurement circuit; and A multiplexer has: a control terminal, receiving an external delay control signal; a plurality of input terminals, respectively coupled to a plurality of output terminals of the delay circuit; and an output terminal, coupled to the memory sub the corresponding pin of the system; Wherein, the external switch control signal controls the operation mode of the timing measurement unit, and the external delay control signal controls a time difference between the test signal source and the output signal of the multiplexer. 9. A method for testing memory, the method comprising: sending a test signal in a balanced manner; respectively delaying the test signal to respectively generate a plurality of delayed test signals for inputting to a plurality of pins of the memory; and Checking whether an output data output by the memory is correct and performing timing adjustment on the delayed test signal input to the pin of the memory, so as to measure an AC timing parameter of the memory. 10. The method of claim 9, further comprising: In response to an external control signal, an external test data is sent to the memory for functional testing. 11. The method of claim 10, further comprising: In response to the external control signal, a timing measurement unit in the memory is made to perform a ring oscillation to measure a delay resolution. 12. The method of claim 9, further comprising: Making the delayed test signal input to an address pin of the memory ahead of the delayed test signal input to a clock pin of the memory to measure a set time parameter. 13. The method of claim 9, further comprising: Making the delayed test signal input to an address pin of the memory lag behind the delayed test signal input to a clock pin of the memory to measure a retention time parameter.

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