CN101276758A - Method for manufacturing semiconductor transistor element - Google Patents

Abstract

The present invention discloses a method for manufacturing a metal oxide semiconductor transistor element. A semiconductor substrate is provided; a gate dielectric layer is formed on the semiconductor substrate; a gate is formed on the gate dielectric layer; a liner layer is formed on the sidewall of the gate; a silicon nitride spacer is formed on the liner layer; a drain/source ion implantation process is performed on the semiconductor substrate to form a drain/source region on both sides of the gate; then, the silicon nitride spacer is removed; then, a silicide metal layer is formed on the drain/source region; then, a cap layer is deposited on the liner layer and the silicide metal layer, the cap layer is directly adjacent to the liner layer, and the cap layer has a specific stress state.

Description

Method for making semiconductor transistor element

technical field

The present invention relates to a method for manufacturing a semiconductor transistor element, in particular to a method for manufacturing a metal-oxide-semiconductor (MOS) field-effect transistor element without a silicon nitride spacer-less . The present invention is characterized in that it combines silicon nitride cap layers with different stresses (compression or tension), so that N or P-type metal oxide semiconductor field effect transistor elements can have higher saturation drain current at the same time (I _dsat ), thereby improving the operating performance of the semiconductor transistor device.

Background technique

As known to those in the industry, current high-speed metal-oxide-semiconductor transistor devices with strained silicon mainly utilize the fact that the lattice constant of the silicon-germanium layer is different from that of silicon, resulting in structural strain when silicon is epitaxy on silicon-germanium principle. In strained silicon-FET devices of this type, biaxial tensile strain of the silicon layer is usually involved, due to the fact that the silicon germanium layer has a larger lattice constant than silicon, which The band structure of silicon is changed, which in turn increases the mobility of carriers. Therefore, a component with a strained silicon structure in the channel region can obtain a speed gain of 1.5 times or even up to 8 times.

Please refer to FIG. 1 to FIG. 3 , which are schematic cross-sectional views of a method for manufacturing a semiconductor NMOS transistor device 10 in the prior art. Firstly, as shown in FIG. 1 , a known semiconductor NMOS transistor device 10 includes a semiconductor substrate including a silicon layer 16, in which a source 18 and a drain separated from the source 18 by a channel region 22 are formed. 20. According to the prior art, the silicon layer 16 may be a strained silicon layer epitaxially on a silicon germanium layer (not shown). Typically, the semiconductor NMOS transistor device 10 further has a shallow junction source extension 17 and a shallow junction drain extension 19 . A gate dielectric layer 14 is formed on the channel region 22 , and a gate 12 is formed on the gate dielectric layer 14 , wherein the gate 12 generally includes polysilicon.

In FIG. 1, the source 18 and the drain 20 of the semiconductor NMOS transistor element 10 are N+ doped regions implanted with arsenic, antimony or phosphorus, and the channel region 22 of the semiconductor NMOS transistor element 10 is P-type doped regions implanted with boron. In the region, a silicon nitride spacer 32 is formed on the sidewall of the gate 12 . Between the silicon nitride spacers 32 and the sidewalls of the gate 12 is a liner layer 30, which is usually made of silicon dioxide. A silicide layer 42 is formed on the exposed silicon surface of the semiconductor NMOS transistor device 10 , including the surface of the drain/source. Since the fabrication of the semiconductor NMOS transistor device 10 as shown in FIG. 1 is well known in the industry, the detailed fabrication procedures thereof will not be repeated here.

After the structure of the semiconductor NMOS transistor device 10 in FIG. 1 is completed, as shown in FIG. 2 , a silicon nitride capping layer 46 is usually deposited on the semiconductor substrate. Wherein, the silicon nitride capping layer 46 covers the metal silicide layer 42 and the silicon nitride spacer 32 , and the thickness of the silicon nitride capping layer 46 is generally between 200-400 angstroms. The purpose of depositing the silicon nitride capping layer 46 is to enable the subsequent contact hole etching to have an obvious etching end point, that is, to be used as a contact etch stop layer (contact etch stoplayer, CESL). After the silicon nitride capping layer 46 is deposited, a dielectric layer 48 such as a silicon oxide layer is deposited. Usually, the dielectric layer 48 is much thicker than the silicon nitride capping layer 46 .

Next, as shown in FIG. 3 , a contact hole 52 is formed in the dielectric layer 48 and the silicon nitride capping layer 46 by using known lithography and etching processes. As mentioned above, during the etching of the contact hole 52 , the function of the silicon nitride capping layer 46 is to provide an end point for the plasma dry etching, thereby mitigating the damage of the plasma etching components to the source or the drain.

However, there are still some shortcomings in the aforementioned prior art that need further improvement and improvement. Since the aforementioned prior art involves the use of a silicon germanium layer under the silicon channel, the silicon germanium layer is prone to lead to the occurrence of defects in the silicon layer, which are also called threading dislocations, which significantly affect the yield . In addition, the silicon germanium layer is deposited on a full-surface wafer, which makes it difficult to individually adjust or optimize NMOS and PMOS. Another disadvantage is that the SiGe layer has poor thermal conductivity. Furthermore, because part of the doping diffuses quickly in the silicon germanium layer, the doping distribution in the source or drain region is not ideal.

Contents of the invention

Therefore, the main purpose of the present invention is to provide a method for fabricating a semiconductor MOS transistor device without a silicon nitride spacer, so that it has optimal operating performance.

According to a first preferred embodiment of the present invention, the present invention provides a method of fabricating a Metal Oxide Semiconductor (MOS) transistor element. Firstly, a semiconductor substrate is provided; a gate dielectric layer is formed on the semiconductor substrate; a gate is formed on the gate dielectric layer, the gate has a side wall and an upper surface; a substrate is formed on the side wall of the gate A pad layer; forming a silicon nitride spacer on the pad layer; using the gate and the silicon nitride spacer as an implantation mask, performing a drain/source ion implantation process on the semiconductor substrate, thereby in the forming a drain/source region on both sides of the gate; removing the silicon nitride spacer; then, after removing the silicon nitride spacer, forming a silicide metal layer on the drain/source region; next, on the A cover layer is deposited on the liner layer and the silicide metal layer, the cover layer directly borders the liner layer, and the cover layer has a specific stress state.

According to a second preferred embodiment of the present invention, the present invention provides a method of fabricating a Complementary Metal Oxide Semiconductor (CMOS) transistor device. Also provide a semiconductor substrate with an NMOS region and a PMOS region thereon; then, form a first gate and a second gate in the NMOS region and the PMOS region respectively; on the sidewalls of the first gate and the second gate forming a liner layer; forming a silicon nitride spacer on the liner layer; then, performing ion implantation processes on the NMOS region and the PMOS region respectively, and implanting N-type doping and P-type doping into the NMOS region and the PMOS region respectively. In the semiconductor substrate in the PMOS region, a drain/source region is thus formed; then, the silicon nitride spacer is removed; after the silicon nitride spacer is removed, the metal silicide process is performed, and the drain/source A metal silicide layer is formed on the pole region.

According to a third preferred embodiment of the present invention, the present invention provides a method of fabricating a Metal Oxide Semiconductor (MOS) transistor element. Similarly, a semiconductor substrate is provided; then, a gate dielectric layer is formed on the semiconductor substrate; then a gate is formed on the gate dielectric layer, the gate has a sidewall and an upper surface; then the gate is formed on the gate forming a liner layer on the sidewall; depositing a silicon nitride layer on the liner layer; performing a dry etching process to etch the silicon nitride layer and the semiconductor substrate to form a silicon nitride spacer on the liner layer, and forming a recessed region next to the silicon nitride spacer; backfilling the recessed region with a semiconductor layer; using the gate and the silicon nitride spacer as an implantation mask, performing a drain/source ion implantation process on the semiconductor substrate , thereby forming a drain/source region on both sides of the gate; removing the silicon nitride spacer; and then, after removing the silicon nitride spacer, forming a silicide metal layer on the drain/source region.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and accompanying drawings of the present invention. However, the drawings are only for reference and auxiliary description, and are not intended to limit the present invention.

Description of drawings

FIG. 1 to FIG. 3 are schematic cross-sectional views of a method for fabricating a semiconductor MOS transistor device in the prior art.

4 to 8 are schematic cross-sectional views of the method for fabricating a semiconductor MOS transistor device according to the first preferred embodiment of the present invention.

9 to 14 are schematic cross-sectional views of a method for fabricating a semiconductor CMOS transistor device according to a second preferred embodiment of the present invention.

15 to 20 are schematic cross-sectional views of a method for manufacturing a semiconductor CMOS transistor device according to a third preferred embodiment of the present invention.

Explanation of reference signs

1NMOS area 2PMOS area

12 grid

14 gate dielectric layer 16 silicon layer

17 shallow junction source extension 18 source

19 shallow junction drain extension 20 drain

22 channel area 30 liner layer

32 Silicon nitride spacer 34 Thin oxide layer

42 suicide metal layer

46 silicon nitride capping layer 46a silicon nitride capping layer

48 dielectric layer 52 contact hole

60 ion implantation process 68 mask layer

78 mask layers 88 mask layers

112 grid

114 gate dielectric layer 116 silicon layer

117 shallow junction source extension 118 source

119 shallow junction drain extension 120 drain

122 channel area 130 liner layer

132 Silicon nitride spacer 134 Thin oxide layer

210 sunken area 220 sunken area

310 silicon carbide layer 320 silicon germanium layer

Detailed ways

Please refer to FIG. 4 to FIG. 8, which are schematic cross-sectional views of the method for manufacturing semiconductor MOS transistor elements according to the first preferred embodiment of the present invention, wherein the same elements or parts are still represented by the same symbols, and it should be noted that Shown is for illustrative purposes only and is not drawn to original size. In addition, in FIG. 4 to FIG. 8, some photolithography and etching steps related to the present invention are well known to those skilled in the art, so they are not specifically shown in the drawings.

The invention relates to a method of fabricating a MOS transistor element or a CMOS element in an integrated circuit. In FIGS. 4 to 8 , the MOS process is firstly used as an illustration, which can be applied in the field of NMOS process or PMOS process.

As shown in FIG. 4 , a semiconductor substrate including a silicon layer 16 is provided first. The aforementioned semiconductor substrate may be a silicon substrate, an epitaxial silicon, a silicon germanium semiconductor substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate or the like. First, using photolithography and etching processes, the gate dielectric layer 14 and the gate 12 are defined and formed on the silicon layer 16, wherein the gate dielectric layer 14 can be a silicon oxide layer, a silicon nitride oxide layer, or a silicon nitride layer. Or other high dielectric constant materials with a higher dielectric constant than silicon dioxide, for example, HfSiNO or ZrO ₂ . Then a silicon oxide liner layer 30 is formed on the sidewall of the gate 12, followed by an ion implantation process to form a shallow junction source extension (shallow junction source extension) 17 and a shallow junction drain extension (shallow junction drain) in the silicon layer 16 extension) 19, wherein the channel region 22 is between the shallow junction source extension 17 and the shallow junction drain extension 19. Furthermore, the gate 12 may be a polysilicon or a metal gate.

Then, a silicon nitride layer (not shown) is deposited on the silicon-oxygen liner layer 30, followed by an etch-back step to etch the silicon nitride layer, thereby forming a silicon nitride spacer 32 on the sidewall of the gate 12 . According to a preferred embodiment of the present invention, the thickness of the bottom of the silicon nitride spacer 32 is about 300-600 angstroms.

Next, an ion implantation process 60 is performed to implant dopant into the silicon layer 16 next to the silicon nitride spacer 32 to form the source 18 and the drain 20 . It should be noted that the aforementioned etching step for forming the silicon nitride spacer 32 stops at the silicon-oxygen liner layer 30, therefore, there will be a thin oxide layer 34 on the surface of the source electrode 18 and the drain electrode 20, and its thickness is about 30 to 40 Angstroms.

In addition, the silicon nitride spacers 32 may also be replaced by silicon oxy-nitride (SiON) or silicon carbide (SiC), not limited to silicon nitride.

Next, as shown in FIG. 5, an etching process is carried out, which can be a wet etching or a dry etching process, for example, utilizing a diluted hydrofluoric acid solution to etch away the thin oxide layer 34 on the surface of the source electrode 18 and the drain electrode 20 , thereby exposing the surfaces of the source electrode 18 and the drain electrode 20 .

As shown in FIG. 6, after removing the thin oxide layer 34, another etching process is then carried out, which can be wet etching, dry etching or gas etching, for example, using hot phosphoric acid solution (hot phosphoric acid solution), the grid 12 The silicon nitride spacers 32 on the sidewalls are completely etched away, leaving only the silicon oxide liner layer 30 on the sidewalls of the gate 12 .

Wherein, if the silicon nitride spacer 32 is etched using a dry etching method, a gas mixed with hydrogen fluoride (HF) gas and a gaseous oxidant can be used. The aforementioned oxidant, for example, nitric acid (HNO ₃ ), ozone ( O ₃ ), hydrogen peroxide (H ₂ O ₂ ), hypochlorous acid (HClO), chloric acid (HClO ₃ ), nitrous acid (HNO ₂ ), oxygen (O ₂ ), sulfuric acid (H ₂ SO ₄ ), chlorine (Cl ₂ ) or bromine (Br ₂ ).

If the silicon nitride spacer 32 is etched by a gas etching method, anhydrous hydrogen halogenide, such as hydrogen fluoride or hydrogen chloride (HCl) gas, may be used.

As shown in FIG. 7, after the silicon nitride spacer 32 is etched away, a metal silicide process is then performed to form a silicide metal layer 42, for example, nickel silicide (NiSi) in the source region and the drain region or on the gate. , cobalt silicide (CoSi), titanium silicide (TiSi), molybdenum silicide (SiMo), palladium silicide (SiPd) and platinum silicide (SiPt), etc. The important feature of the present invention is that there is no silicon nitride spacer on the sidewall of the gate, and after the silicon nitride spacer 32 is removed in the step, an approximately L-shaped liner is left on the sidewall of the gate 12 Layer 30 is then subjected to a metal silicide process to form a metal silicide layer 42 , so that damage to the metal silicide layer 42 can be avoided when etching the silicon nitride spacer 32 .

As shown in FIG. 8, a silicon nitride cap layer 46a is then deposited, preferably to a thickness between 30 and 2000 Angstroms. Since the silicon nitride spacer 32 has been removed, the silicon nitride capping layer 46 a directly adjoins the liner layer 30 on the sidewall of the gate 12 . According to the present invention, the silicon nitride capping layer 46a is first set to be deposited in a predetermined stress state during deposition, for example, for an NMOS element, this predetermined stress state is a tensile strain (tensile-stressed) state, and the magnitude of the stress is about 0.1 Between Gpa and 3Gpa, and for the PMOS element, the predetermined stress state is a compressive-stressed state, and the stress is between -0.1Gpa and -3Gpa.

A dielectric layer 48 is then deposited over the semiconductor substrate, covering the silicon nitride cap layer 46 . The aforementioned dielectric layer 48 can be made of silicon oxide, doped silicon oxide, or low dielectric constant material, and so on. In addition, according to another embodiment of the present invention, the dielectric layer 48 also has different specific stress states, for example, a tensile strain state or a compressive strain state. According to the spirit of the present invention, the silicon nitride capping layer 46a also acts as an etching stop layer in the subsequent dry etching of the contact hole, thereby reducing the damage of the plasma etching components to the source or the drain.

Next, please refer to FIG. 9 to FIG. 14 , which are schematic cross-sectional views of a method for manufacturing semiconductor CMOS transistor elements according to a second preferred embodiment of the present invention, wherein the same elements or parts are still represented by the same symbols.

As shown in FIG. 9 , a semiconductor substrate including a silicon layer 16 is prepared first, wherein the NMOS region 1 is used for manufacturing NMOS devices, and the PMOS region 2 is used for manufacturing PMOS devices. The aforementioned semiconductor substrate may be a silicon substrate, epitaxial silicon, silicon germanium semiconductor substrate, silicon carbide substrate or silicon-on-insulator (SOI) substrate, etc. In the region 1 , a shallow junction source extension 17 and a shallow junction drain extension 19 are formed in the silicon layer 16 , wherein an N channel 22 is formed between the shallow junction source extension 17 and the shallow junction drain extension 19 . A shallow junction source extension 117 and a shallow junction drain extension 119 are formed in the silicon layer 16 in the region 2 , wherein a P-channel 122 is formed between the shallow junction source extension 117 and the shallow junction drain extension 119 .

Gate oxide layers 14 and 114 and gates 12 and 112 are respectively formed on channels 22 and 122 , wherein gates 12 and 112 generally comprise polysilicon. The gate oxide layers 14 and 114 may be made of silicon dioxide. However, in other embodiments of the present invention, the gate oxide layers 14 and 114 may also be made of other high-k materials, for example, nitrided oxide, nitrogen compound, hafnium silicon oxynitride (HfSiNO) or zirconium oxide (ZrO ₂ ), etc.

There are also liner layers 30 and 130 between the gate and the silicon nitride spacer. The aforesaid liner layer can be made of silicon oxide, generally L-shaped and about 30 to 120 angstroms thick. Silicon nitride spacers 32 and 132 are then formed on the sidewalls of the gates 12 and 112 . The method for forming the silicon nitride spacers 32 and 132 is to deposit a silicon nitride layer (not shown), and then perform a dry etching step to etch the silicon nitride layer. The dry etch step of the silicon nitride spacers 32 and 132 stops on the silicon oxide liner layer 30, so there will be thin oxide layers 34 and 134 on the surface of the source and drain electrodes with a thickness of about 30 to 40 Angstroms. between.

As shown in FIG. 10 , after forming the silicon nitride spacers 32 and 132 , the region 2 is covered with a mask layer 68 of a material such as photoresist. Next, an ion implantation process is performed to implant N-type dopant species such as arsenic, antimony or phosphorus into the silicon layer 16 in the region 1, thereby forming the source region 18 and the drain region 20 of the NMOS device. After the aforementioned ion implantation process is completed, the mask layer 68 is stripped off immediately.

As shown in FIG. 11 , in a similar manner, area 1 is covered with a mask layer 78 of a material such as photoresist. Next, another ion implantation process is performed to implant P-type dopant species such as boron into the silicon layer 16 in the region 2 , thereby forming the source region 118 and the drain region 120 of the PMOS device. After the aforementioned ion implantation process is completed, the mask layer 78 is stripped off immediately. Those skilled in the art should understand that the aforementioned ion implantation sequence shown in FIG. 10 and FIG. 11 can be reversed. In other words, the P-type doping in the region 2 can be performed first, and then the N-type doping in the region 1 can be performed.

In addition, after the doping of the drain and the source is completed, the thermal process of annealing or activation doping can usually be performed. This step is also well known by those skilled in the art and will not be described here.

Next, as shown in Figure 12, carry out etching process, it can be wet etching or dry etching process, for example, utilize dilute hydrofluoric acid solution, etch away the thin oxide layer 34 on the surface of source electrode 18 and drain electrode 20 and 134, thereby exposing the surfaces of the source and drain.

After removing the thin oxide layers 34 and 134, another etching process is then carried out, which can be wet etching, dry etching or gas etching, for example, using hot phosphoric acid solution (hot phosphoric acid solution), the gate 12 on the sidewall The silicon nitride spacers 32 and 132 are completely etched away, leaving only the silicon oxide liner layers 30 and 130 on the sidewalls of the gates 12 and 112 .

Wherein, if the silicon nitride spacers 32 and 132 are etched using a dry etching method, a gas mixed with hydrogen fluoride (HF) gas and a gaseous oxidant can be used. The aforementioned oxidant, for example, nitric acid (HNO ₃ ), ozone (O ₃ ), hydrogen peroxide (H ₂ O ₂ ), hypochlorous acid (HClO), chloric acid (HClO ₃ ), nitrous acid (HNO ₂ ), oxygen (O ₂ ), sulfuric acid (H ₂ SO ₄ ), chlorine ( Cl ₂ ) or bromine (Br ₂ ).

If gas etching is used to etch the silicon nitride spacers 32 and 132 , dehydrated hydrogen halide, such as hydrogen fluoride or hydrogen chloride (HCl) gas may be used.

As shown in FIG. 13 , a silicide metal process is then performed to form a silicide metal layer 42 on the source region, drain region, and gate of the NMOS transistor element and the PMOS transistor element, for example, nickel silicide (NiSi), cobalt silicide ( CoSi), titanium silicide (TiSi), molybdenum silicide (SiMo), palladium silicide (SiPd) and platinum silicide (SiPt), etc.

The present invention is characterized in that there are no silicon nitride spacers on the gate sidewalls of NMOS transistor elements and PMOS transistor elements, and there are only approximately L-shaped pad layers 30 and 130 on the gate sidewalls, and in the steps , after the silicon nitride spacers 32 and 132 are removed, the metal silicide process begins. In addition, the liner layers 30 and 130 are not necessarily L-shaped, and a milder etching process can be performed to slightly etch the liner layers to reduce their thickness. In other embodiments, liner layers 30 and 130 may be completely removed.

Next, a silicon nitride capping layer 46a is deposited, preferably with a thickness between 30 and 2000 angstroms. Since the silicon nitride spacers 32 and 132 have been removed, the silicon nitride capping layer 46 a directly adjoins the liner layers 30 and 130 on the sidewalls of the gates 12 and 112 of the NMOS transistor device and the PMOS transistor device. According to the second preferred embodiment of the present invention, the silicon nitride capping layer 46a is first set to be deposited in a first stress state during deposition, such as a compressive-stressed state, and its stress size is about -0.1Gpa to -3Gpa between. In this way, the channel region 122 is subjected to the compressive stress of the silicon nitride capping layer 46a. Next, the silicon nitride capping layer 46 a located in the region 2 is covered by the mask layer 88 .

Then, the stress state of the silicon nitride capping layer 46a not covered by the mask layer 88 is changed to a second stress state, which is opposite to the first stress state, that is, the silicon nitride capping layer 46a in the region 2 is In the compressive strain state, the second stress state is a tensile strain (tensile-stressed) state, and the stress is between 0.1 GPa and 3 GPa. In this way, the channel region 22 is subjected to the tensile stress of the silicon nitride capping layer 46a.

According to a preferred embodiment of the present invention, the method of changing the stress state of the silicon nitride capping layer 46a in the region 1 may utilize germanium (Ge) ion implantation. However, those skilled in the art should understand that changing the stress state of the silicon nitride capping layer 46a in the region 1 can also be performed by using other methods to achieve the same purpose.

As shown in FIG. 14 , a dielectric layer 48 is then deposited on the semiconductor substrate, covering the silicon nitride capping layer 46 a in the regions 1 and 2 . The aforementioned dielectric layer 48 can be made of silicon oxide, doped silicon oxide, or low dielectric constant material, and so on. In addition, according to another embodiment of the present invention, the dielectric layer 48 also has different specific stress states, for example, the dielectric layer 48 in the region 1 is in a tensile strain state, and the dielectric layer 48 in the region 2 is in a compressive strain state. state.

Then, a known photolithography and etching process is performed to form a contact hole 52 in the dielectric layer 48 and the silicon nitride capping layer 46a, which leads to the drain or source region of the NMOS transistor device and the PMOS transistor device. In other embodiments, a contact hole leading to the gate can also be formed at the same time, but this is not explicitly shown in the figure. According to the spirit of the present invention, in addition to providing stress, the silicon nitride capping layer 46a also plays the role of a contact hole etching stop layer in the aforementioned dry etching of the contact hole, thereby reducing the impact of plasma etching components on the source or drain. s damage.

Next, please refer to FIG. 15 to FIG. 20 , which are schematic cross-sectional views of a method for manufacturing semiconductor CMOS transistor elements according to a third preferred embodiment of the present invention, wherein the same elements or parts are still represented by the same symbols.

As shown in FIG. 15 , the semiconductor substrate including the silicon layer 16 is firstly prepared. Similarly, area 1 is used for fabricating NMOS devices, and area 2 is used for fabricating PMOS devices. The aforementioned semiconductor substrate may be a silicon substrate, epitaxial silicon, silicon germanium semiconductor substrate, silicon carbide substrate or silicon-on-insulator (SOI) substrate, etc. In the region 1 , a shallow junction source extension 17 and a shallow junction drain extension 19 are formed in the silicon layer 16 , wherein an N channel 22 is formed between the shallow junction source extension 17 and the shallow junction drain extension 19 . A shallow junction source extension 117 and a shallow junction drain extension 119 are formed in the silicon layer 16 in the region 2 , wherein a P-channel 122 is formed between the shallow junction source extension 117 and the shallow junction drain extension 119 .

Gate oxide layers 14 and 114 and gates 12 and 112 are respectively formed on channels 22 and 122 , wherein gates 12 and 112 generally comprise polysilicon. The gate oxide layers 14 and 114 may be made of silicon dioxide. However, in other embodiments of the present invention, the gate oxide layers 14 and 114 may also be made of other high-k materials, for example, nitrided oxide, nitrogen compound, hafnium silicon oxynitride (HfSiNO) or zirconium oxide (ZrO ₂ ), etc.

There are also liner layers 30 and 130 between the gate and the silicon nitride spacer. The aforesaid liner layer can be made of silicon oxide, generally L-shaped and about 30 to 120 angstroms thick. Silicon nitride spacers 32 and 132 are then formed on the sidewalls of the gates 12 and 112 . The method for forming the silicon nitride spacers 32 and 132 is to deposit a silicon nitride layer (not shown), and then perform a dry etching step to etch the silicon nitride layer. The dry etching step of the silicon nitride spacers 32 and 132 etches through the silicon oxide liner layer 30, and continues to etch the silicon layer 16 to a predetermined depth, such as between 20 and 300 angstroms, thereby forming a gap between the silicon nitride spacers 32 and 132 Recessed areas (recessed areas) 210 and 220 are formed on one side.

As shown in FIG. 16 , semiconductor layers such as silicon carbide layer 310 and silicon germanium layer 320 are filled in the recessed region 210 in region 1 and the recessed region 220 in region 2 respectively.

As shown in FIG. 17, the region 2 is covered with a mask layer 68 of material such as photoresist. Next, an ion implantation process is performed to implant N-type dopant species such as arsenic, antimony or phosphorus into the silicon layer 16 in the region 1, thereby forming the source region 18 and the drain region 20 of the NMOS device. After the aforementioned ion implantation process is completed, the mask layer 68 is stripped off immediately.

As shown in FIG. 18, in a similar manner, area 1 is covered with a mask layer 78 of material such as photoresist. Next, another ion implantation process is performed to implant P-type dopant species such as boron into the silicon layer 16 in the region 2 , thereby forming the source region 118 and the drain region 120 of the PMOS device. After the aforementioned ion implantation process is completed, the mask layer 78 is stripped off immediately. Those skilled in the art should understand that the ion implantation sequence shown in FIG. 17 and FIG. 18 can be reversed. In other words, P-type doping in region 2 can be performed first, and then N-type doping in region 1 can be performed.

In addition, after the doping of the drain and source is completed, an annealing or a thermal process of activating the doping can usually be performed. This step is also well known by those skilled in the art and will not be described here.

Next, as shown in Figure 19, carry out etching process, it can be wet etching, dry etching or gas etching method, for example, utilize hot phosphoric acid solution, the silicon nitride spacers 32 and 132 on the gate 12 sidewalls are completely etched The silicon oxide pad layers 30 and 130 are left on the sidewalls of the gate electrodes 12 and 112 .

Wherein, if the silicon nitride spacers 32 and 132 are etched using a dry etching method, a gas mixed with hydrogen fluoride gas and a gaseous oxidant can be used. The aforementioned oxidant, for example, nitric acid (HNO ₃ ), ozone (O ₃ ), Hydrogen peroxide (H ₂ O ₂ ), hypochlorous acid (HClO), chloric acid (HClO ₃ ), nitrous acid (HNO ₂ ), oxygen (O ₂ ), sulfuric acid (H ₂ SO ₄ ), chlorine (Cl ₂ ) Or bromine (Br ₂ ).

If gas etching is used to etch the silicon nitride spacers 32 and 132 , dehydrated hydrogen halide gas, such as hydrogen fluoride or hydrogen chloride gas, can be used.

As shown in FIG. 20, the metal silicide process is then performed to form a metal silicide layer 42 on the source region, drain region, and gate of the NMOS transistor element and the PMOS transistor element, such as nickel silicide, cobalt silicide, titanium silicide, Molybdenum silicide, palladium silicide and platinum silicide, etc.

Next, a silicon nitride capping layer 46a is deposited, preferably with a thickness between 30 and 2000 angstroms. Since the silicon nitride spacers 32 and 132 have been removed, the silicon nitride capping layer 46 a directly adjoins the liner layers 30 and 130 on the sidewalls of the gates 12 and 112 of the NMOS transistor device and the PMOS transistor device. According to the third preferred embodiment of the present invention, the silicon nitride capping layer 46a can be deposited in a first stress state, such as a compressive strain state, and the stress is between -0.1GPa and -3GPa. In this way, the P-channel region 122 is subjected to the compressive stress of the silicon nitride capping layer 46a.

Next, the stress state of the silicon nitride capping layer 46a in region 1 is changed to a second stress state, which is opposite to the first stress state, that is, the silicon nitride capping layer 46a in region 2 is in a compressive strain state , then the second stress state is the tensile strain state, and its stress magnitude is about between 0.1 GPa and 3 GPa. In this way, the N-channel region 22 is subjected to the tensile stress of the silicon nitride capping layer 46a.

The advantage of the present invention over the prior art is that the NMOS transistor elements are covered with a silicon nitride cap layer in a state of tensile strain, while the PMOS transistor elements are covered with a silicon nitride cap layer in a state of compressive strain, whereby The characteristics of the NMOS element and the PMOS element are adjusted respectively.

In addition, because the present invention removes the silicon nitride spacers on the gate sidewalls, the aforementioned silicon nitride capping layer can be relatively close to the channels 22 and 122 of the NMOS and PMOS transistor elements, which can lead to an increase in the saturation current and make the elements Operational efficiency has been significantly improved. In terms of steps, the metal silicide process is performed after the silicon nitride spacer is removed to form the metal silicide layer. In this way, the metal silicide layer can be avoided from being damaged when the silicon nitride spacer is etched.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (31)

1. A method of making a metal oxide semiconductor transistor element, comprising: Provide a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming a gate on the gate dielectric layer, the gate has sidewalls and an upper surface; forming a liner layer on the sidewall of the gate; forming a silicon nitride spacer on the liner layer; Using the gate and the silicon nitride spacer as an implantation mask, performing a drain/source ion implantation process on the semiconductor substrate, thereby forming drain/source regions on both sides of the gate; removing the silicon nitride spacer; and After removing the silicon nitride spacers, a metal silicide layer is formed on the drain/source regions. 2. The method for manufacturing a metal oxide semiconductor transistor device as claimed in claim 1, wherein the method further includes the following steps after performing the drain/source ion implantation process and before removing the silicon nitride spacer step: An etching process is performed to remove the silicon oxide layer on the surface of the drain/source region. 3. The method for manufacturing a metal oxide semiconductor transistor device as claimed in claim 1, wherein, after forming the silicide metal layer on the drain/source region, the method further comprises the following steps: A cap layer is deposited on the liner layer and the silicide metal layer, the cap layer is directly bordered on the liner layer, and the cap layer has a specific stress state. 4. The method for fabricating a metal oxide semiconductor transistor device as claimed in claim 3, wherein the thickness of the capping layer is between 30 and 2000 angstroms. 5. The method for fabricating a metal oxide semiconductor transistor device as claimed in claim 3, wherein the capping layer acts as an etch stop layer when etching the contact hole. 6. The method for fabricating a metal oxide semiconductor transistor device as claimed in claim 3, wherein the metal oxide semiconductor transistor device is an N-type metal oxide semiconductor transistor device, and the capping layer is in a state of tensile strain. 7. The method for fabricating a metal oxide semiconductor transistor device as claimed in claim 3, wherein the metal oxide semiconductor transistor device is a P-type metal oxide semiconductor transistor device, and the capping layer is in a state of compressive strain. 8. The method for fabricating a metal oxide semiconductor transistor device as claimed in claim 3, wherein the capping layer comprises silicon nitride. 9. The method for fabricating a metal oxide semiconductor transistor device as claimed in claim 1, wherein the liner layer comprises silicon oxide. 10. The method of fabricating a metal oxide semiconductor transistor device as claimed in claim 1, wherein the method further comprises a step of annealing the drain/source region. 11. The method for fabricating a metal oxide semiconductor transistor device as claimed in claim 1, wherein the metal silicide layer comprises nickel silicide, cobalt silicide, titanium silicide, molybdenum silicide, palladium silicide, and platinum silicide. 12. The method of manufacturing a metal oxide semiconductor transistor device as claimed in claim 1, wherein the gate comprises polysilicon and metal. 13. The method for manufacturing a metal oxide semiconductor transistor device as claimed in claim 1, wherein after the silicon nitride spacer is formed, the following steps are further included: forming a recessed region next to the silicon nitride spacer; and The recessed area is backfilled with an epitaxial silicon layer. 14. The method for manufacturing a metal oxide semiconductor transistor device as claimed in claim 13, wherein the metal oxide semiconductor transistor device is an N-type metal oxide semiconductor transistor, and the epitaxial silicon layer is a silicon carbide layer. 15. The method for manufacturing a metal oxide semiconductor transistor device as claimed in claim 13, wherein the metal oxide semiconductor transistor device is a P-type metal oxide semiconductor transistor, and the epitaxial silicon layer is a silicon germanium layer. 16. The method for manufacturing a metal oxide semiconductor transistor device as claimed in claim 1, wherein the silicon nitride spacer is removed by wet etching, dry etching or gas etching. 17. The method for fabricating a metal oxide semiconductor transistor device as claimed in claim 16, wherein the wet etching method utilizes a hot phosphoric acid solution. 18. The method of fabricating a metal oxide semiconductor transistor device as claimed in claim 16, wherein the dry etching method utilizes a gas mixed with hydrogen fluoride gas and a gaseous oxidant. 19. The method for manufacturing a metal oxide semiconductor transistor device as claimed in claim 18, wherein the gaseous oxidant includes nitric acid, ozone, hydrogen peroxide, hypochlorous acid, chloric acid, nitrous acid, oxygen, sulfuric acid, chlorine or bromine. 20. The method of fabricating a metal oxide semiconductor transistor device as claimed in claim 16, wherein the gas etching method utilizes dehydrated hydrogen halide, including hydrogen fluoride or hydrogen chloride gas. 21. The method for manufacturing a metal oxide semiconductor transistor device as claimed in claim 1, further comprising forming an epitaxial silicon layer next to the silicon nitride spacer after the silicon nitride spacer is formed. 22. A method of fabricating a complementary metal-oxide-semiconductor transistor device, comprising: A semiconductor substrate is provided, having an N-type metal oxide semiconductor region and a P-type metal oxide semiconductor region thereon; Forming a first gate and a second gate in the N-type metal oxide semiconductor region and the P-type metal oxide semiconductor region respectively; forming a liner layer on sidewalls of the first gate and the second gate; forming a silicon nitride spacer on the liner layer; Performing an ion implantation process, respectively implanting N-type doping and P-type doping into the semiconductor substrate of the N-type metal oxide semiconductor region and the P-type metal oxide semiconductor region, thereby forming a drain/source region; removing the silicon nitride spacer; and After removing the silicon nitride spacers, a metal silicide process is performed to form a metal silicide layer on the drain/source regions. 23. The method for manufacturing a complementary metal-oxide-semiconductor transistor device as claimed in claim 22, wherein, after forming the silicide metal layer on the drain/source region, the method further comprises the following steps: forming a tensile strained capping layer on the NMOS region, and the tensile strained capping layer directly borders the liner layer; and A compressive strain capping layer is formed on the PMOS region. 24. The method of fabricating a CMOS transistor device as claimed in claim 23, wherein the tensile strain capping layer and the compressive strain capping layer comprise silicon nitride. 25. The method for fabricating a CMOS transistor device as claimed in claim 22, wherein the liner layer comprises silicon oxide. 26. The method of fabricating a CMOS transistor device as claimed in claim 22, wherein the method further comprises the step of annealing the drain/source region. 27. The method for fabricating a CMOS transistor device as claimed in claim 22, wherein the metal silicide layer comprises nickel silicide, cobalt silicide, titanium silicide, molybdenum silicide, palladium silicide and platinum silicide. 28. The method for fabricating a CMOS transistor device as claimed in claim 22, wherein the gate comprises polysilicon and metal. 29. The method for manufacturing a CMOS transistor device as claimed in claim 22, wherein the silicon nitride spacer is removed by wet etching, dry etching or gas etching. 30. The method for manufacturing a CMOS transistor device as claimed in claim 22, further comprising forming an epitaxial silicon layer next to the silicon nitride spacer after the silicon nitride spacer is formed. 31. The method for manufacturing a CMOS transistor device as claimed in claim 22, wherein after the silicon nitride spacer is formed, further comprising the following steps: forming a recessed region next to the silicon nitride spacer; and The recessed area is backfilled with an epitaxial silicon layer.

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