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CN101226888B - Heat radiation type chip packaging process and structure thereof - Google Patents

Heat radiation type chip packaging process and structure thereof Download PDF

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Publication number
CN101226888B
CN101226888B CN200810074323XA CN200810074323A CN101226888B CN 101226888 B CN101226888 B CN 101226888B CN 200810074323X A CN200810074323X A CN 200810074323XA CN 200810074323 A CN200810074323 A CN 200810074323A CN 101226888 B CN101226888 B CN 101226888B
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preimpregnation material
chip
base board
board unit
preimpregnation
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CN101226888A (en
Inventor
唐和明
赵兴华
李明锦
黄泰源
刘昭源
黄詠政
李德章
高仁杰
陈昭雄
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明公开了一种散热型芯片封装工艺及其构造。该散热型芯片封装工艺至少包含下列步骤：首先，提供包含有至少一基板单元的基板条；接着，设置至少一芯片于该基板单元的上表面，该芯片电性连接该基板单元；之后，提供预浸材及散热金属层，该散热金属层设置于该预浸材的第一表面，该预浸材的第二表面朝向该芯片；最后，压合该预浸材及该基板单元，以使该预浸材覆盖该芯片。

Figure 200810074323

The present invention discloses a heat dissipation chip packaging process and its structure. The heat dissipation chip packaging process at least comprises the following steps: first, providing a substrate strip comprising at least one substrate unit; second, arranging at least one chip on the upper surface of the substrate unit, the chip being electrically connected to the substrate unit; then, providing a prepreg and a heat dissipation metal layer, the heat dissipation metal layer being arranged on the first surface of the prepreg, the second surface of the prepreg facing the chip; finally, pressing the prepreg and the substrate unit together so that the prepreg covers the chip.

Figure 200810074323

Description

Heat sinking type chip packaging technology and structure thereof
Technical field
The present invention relates to a kind of packaging technology, particularly a kind of heat sinking type chip packaging technology.
Background technology
Need carry out one in the known package step and irritate mold technique with the seal protection chip; its required board cost and die cost is higher; and the technology contents complexity that is comprised, yet the cost of great number and technology are not proportional relation with the product quality that encapsulation is finished but, cause the waste of production cost in rain.
Summary of the invention
Main purpose of the present invention is to provide a kind of heat sinking type chip packaging technology, at first, provides substrate strip, and this substrate strip includes at least one base board unit; Then, chip is set in this base board unit, a plurality of projections of this chip electrically connect a plurality of connection gaskets of this base board unit; Afterwards, provide first preimpregnation material and the heat radiating metallic layer, this first preimpregnation material has first surface and second surface, and this heat radiating metallic layer is arranged at this first surface, and this second surface is towards the back side of this chip; At last, this first preimpregnation material of pressing and this base board unit are so that this first preimpregnation material covers this chip.The present invention replaces known filling mould with this first preimpregnation material of pressing with the step that forms packaging structure and inserts adhesive body to form the step of packaging structure, and it has the effect that stability is high and reduce cost.
Another object of the present invention is to provide a kind of substrate process, it can include in addition: provide and the pressing second preimpregnation material in this base board unit, this second preimpregnation material is between this first preimpregnation material and this base board unit, at least one opening of this second preimpregnation material is in alignment with this chip, and this first preimpregnation material of pressing, this second preimpregnation material and this base board unit are to coat this chip and to reduce the probability that bubble exists.
Description of drawings
Figure 1A to Fig. 1 G is the schematic cross-section according to a kind of heat sinking type chip packaging technology of the present invention's first specific embodiment.
Fig. 2 is the schematic cross-section according to this heat sinking type chip packaging structure of the present invention's first specific embodiment.
Fig. 3 is the schematic cross-section according to the another kind of heat sinking type chip packaging structure of the present invention's second specific embodiment.
Fig. 4 A to Fig. 4 F is the schematic cross-section according to the another kind of heat sinking type chip packaging technology of the present invention's the 3rd specific embodiment.
Fig. 5 is the schematic cross-section according to this heat sinking type chip packaging structure of the present invention's the 3rd specific embodiment.
Fig. 6 is the schematic cross-section according to the another kind of heat sinking type chip packaging structure of the present invention's the 4th specific embodiment.
Fig. 7 A to Fig. 7 F is the schematic cross-section according to the another kind of heat sinking type chip packaging technology of the present invention's the 5th specific embodiment.
Fig. 8 is the schematic cross-section according to this heat sinking type chip packaging structure of the present invention's the 5th specific embodiment.
Fig. 9 is the schematic cross-section according to the another kind of heat sinking type chip packaging structure of the present invention's the 6th specific embodiment.
Description of reference numerals
10 substrate strip, 20 anchor clamps
30 substrate strip, 40 substrate strip
100 heat sinking type chip packaging structures, 110 base board units
111 upper surfaces, 112 lower surfaces
113 first connection gaskets, 114 second connection gaskets
115 the 3rd connection gaskets, 120 chips
121 active faces, 122 back sides
123 projections, 130 primers
140 first preimpregnation materials, 141 first surfaces
142 second surfaces, 150 heat radiating metallic layers
160 second preimpregnation materials 161 the 3rd surface
162 the 4th surperficial 163 openings
170 soldered balls, 180 plated-through-holes
200 heat sinking type chip packaging structures, 210 base board units
211 upper surfaces, 212 lower surfaces
213 first connection gaskets, 214 second connection gaskets
215 the 3rd connection gaskets, 220 chips
221 active faces, 222 back sides
223 projections, 230 first preimpregnation materials
231 first surfaces, 232 second surfaces
240 heat radiating metallic layers, 250 second preimpregnation materials
252 the 4th surfaces, 251 the 3rd surfaces
253 openings, 260 soldered balls
270 plated-through-holes, 300 heat sinking type chip packaging structures
310 base board units, 311 upper surfaces
312 lower surfaces, 313 first connection gaskets
314 second connection gaskets 315 the 3rd connection gasket
320 chips, 321 active faces
330 bonding wires, 340 first preimpregnation materials
341 first surfaces, 342 second surfaces
350 heat radiating metallic layers, 360 second preimpregnation materials
362 the 4th surfaces, 361 the 3rd surfaces
363 openings, 370 soldered balls
380 plated-through-holes
Embodiment
See also Figure 1A to Fig. 1 G, disclose a kind of heat sinking type chip packaging technology according to a specific embodiment of the present invention, at first, see also Figure 1A, substrate strip 10 is provided, and this substrate strip 10 includes a plurality of base board units 110, and each base board unit 110 has upper surface 111, lower surface 112, a plurality of first connection gasket 113 and a plurality of second connection gasket 114, this first connection gasket 113 is formed at this upper surface 111, and this second connection gasket 114 is formed at this lower surface 112; Then, see also Figure 1B, a plurality of chips 120 this upper surface 111 in this base board unit 110 is set, and each chip 120 has active face 121, the back side 122 and a plurality of projection 123, and this projection 123 of this chip 120 electrically connects this first connection gasket 113 of this base board unit 110; Afterwards, see also Fig. 1 C, form primer 130 (underfill) in this upper surface 111, this primer 130 is in order to coat this active face 121 and this projection 123, and this primer 130 can appear this back side 122 of this chip 120, and this primer 130 is in order to strengthen the bond strength of this chip 120 and this base board unit 110; Then, see also Fig. 1 D, the first preimpregnation material 140 and heat radiating metallic layer 150 are provided, this first preimpregnation material 140 has first surface 141 and second surface 142, this second surface 142 is towards this back side 122 of this chip 120, this heat radiating metallic layer 150 is arranged at this first surface 141 of this first preimpregnation material 140, the material of this heat radiating metallic layer 150 is copper or surface treated copper layer, in this step, other comprises provides the second preimpregnation material 160, this second preimpregnation material 160 can be piled up in advance by a plurality of preimpregnation materials and form, perhaps, in another embodiment, this second preimpregnation material 160 is one-body molded with this first preimpregnation material 140, or be combined into one, this second preimpregnation material 160 is between this first preimpregnation material 140 and this base board unit 110, and this second preimpregnation material 160 has the 3rd surface 161, the 4th surface 162 and a plurality of openings 163, the 3rd surface 161 is towards this second surface 142 of this first preimpregnation material 140, and this opening 163 is formed at the 4th surface 162, preferably, this opening 163 runs through the 3rd surface 161 and the 4th surface 162, and this opening 163 is in alignment with this chip 120, in the present embodiment, this first preimpregnation material 140 has the characteristic of B-stage with this second preimpregnation material 160, this first preimpregnation material 140 is the semi-solid preparation colloidal state with this second preimpregnation material 160, so that this first preimpregnation material 140 has flowability with this second preimpregnation material 160; Afterwards, see also Fig. 1 E, utilize this first preimpregnation material 140, this heat radiating metallic layer 150 of anchor clamps 20 pressing simultaneously semi-solid preparation colloidal state, this second preimpregnation material 160 and this base board unit 110 of semi-solid preparation colloidal state, in addition, the step that also can heat in the process of this first preimpregnation material 140 of pressing, this heat radiating metallic layer 150, this second preimpregnation material 160 and this base board unit 110 is so that this first preimpregnation material 140 solidifies with this second preimpregnation material 160; Then, see also Fig. 1 F, after the pressing step is finished, this first preimpregnation material 140 covers this chip 120, this second preimpregnation material 160 is attached to this upper surface 111 of this base board unit 110 by pressing, and this second preimpregnation material 160 coats this primer 130, and a plurality of soldered balls 170 this lower surface 112 in this base board unit 110 then is set, and this soldered ball 170 connects this second connection gasket 114; At last, see also Fig. 1 G, cut this substrate strip 10 with form a plurality of lists from packaging structure 100.Because this first preimpregnation material 140 contains glass fiber material or filler (filler) with this second preimpregnation material 160, can increase structural strength and reliability with this base board unit 110.
See also Fig. 2, disclose a kind of heat sinking type chip packaging structure 100 according to a specific embodiment of the present invention, it comprises base board unit 110, chip 120, the first preimpregnation material 140 and heat radiating metallic layer 150, this base board unit 110 has upper surface 111, lower surface 112, a plurality of first connection gaskets 113 and a plurality of second connection gasket 114, this first connection gasket 113 is formed at this upper surface 111, this second connection gasket 114 is formed at this lower surface 112, this chip 120 is arranged at this upper surface 111 of this base board unit 110, this chip 120 has active face 121, the back side 122 and a plurality of projection 123, this projection 123 of this chip 120 electrically connects this first connection gasket 113 of this base board unit 110, this first preimpregnation material 140 has first surface 141 and second surface 142, this first preimpregnation material 140 covers this chip 120, this heat radiating metallic layer 150 is arranged at this first surface 141 of this first preimpregnation material 140 to promote heat radiation, preferably, this heat sinking type chip packaging structure 100 includes primer 130 (underfill) in addition, the second preimpregnation material 160 and a plurality of soldered ball 170, this primer 130 is formed at this upper surface 111 to coat this active face 121 and this projection 123, this second preimpregnation material 160 has the 3rd surface 161, the 4th surface 162 and one opening 163, this opening 163 is formed at the 4th surface 162, in the present embodiment, this opening 163 runs through the 3rd surface 161 and the 4th surface 162, this second preimpregnation material 160 is between this first preimpregnation material 140 and this base board unit 110, this chip 120 is arranged in this opening 163, and the 3rd surface 161 of this second preimpregnation material 160 connects this second surface 142 of this first preimpregnation material 140 with this chip 120 of complete coating, in another embodiment, this second preimpregnation material 160 is one-body molded with this first preimpregnation material 140, or be combined into one in advance, in the present embodiment, this second preimpregnation material 160 is attached to this upper surface 111 of this base board unit 110 by pressing, and this second preimpregnation material 160 coats this primer 130, this soldered ball 170 is arranged at this lower surface 112 of this base board unit 110, and this soldered ball 170 connects this second connection gasket 114, with external circuits plate (figure does not draw).
In addition, see also Fig. 3, in another embodiment, this heat sinking type chip packaging structure 100 includes at least one plated-through-hole 180 in addition, this plated-through-hole 180 is formed in this first preimpregnation material 140 and this second preimpregnation material 160, this base board unit 110 has a plurality of the 3rd connection gasket 115, the three connection gaskets 115 in addition and is formed at this first connection gasket, 113 outsides, and this plated-through-hole 180 connects this heat radiating metallic layer 150 and the 3rd connection gasket 115.Preferably, when this heat radiating metallic layer 150 is patterned line layer, another packaging structure (figure do not draw) can be set in these heat radiating metallic layer 150 tops, and by this plated-through-hole 180 electrically conduct this packaging structure and this heat sinking type chip packaging structure 100.
See also Fig. 4 A to Fig. 4 F, disclose another kind of heat sinking type chip packaging technology according to another specific embodiment of the present invention, at first, see also Fig. 4 A, substrate strip 30 is provided, this substrate strip 30 includes a plurality of base board units 210, and each base board unit 210 has upper surface 211, lower surface 212, a plurality of first connection gasket 213 and a plurality of second connection gasket 214 that is formed at this lower surface 212 that is formed at this upper surface 211; Then, see also Fig. 4 B, a plurality of chips 220 this upper surface 211 in this base board unit 210 is set, and each chip 220 has active face 221, the back side 222 and a plurality of projection 223, and this projection 223 of this chip 220 electrically connects this first connection gasket 213 of this base board unit 210; Afterwards, see also Fig. 4 C, the first preimpregnation material 230 and heat radiating metallic layer 240 are provided, this first preimpregnation material 230 has first surface 231 and second surface 232, this second surface 232 is towards this back side 222 of this chip 220, this heat radiating metallic layer 240 is arranged at this first surface 231 of this first preimpregnation material 230, the material of this heat radiating metallic layer 240 is copper or surface treated copper layer, in this step, other comprises provides the second preimpregnation material 250, this second preimpregnation material 250 can be piled up in advance by a plurality of preimpregnation materials and form, perhaps, in another embodiment, this second preimpregnation material 250 is formed in one with this first preimpregnation material 230, this second preimpregnation material 250 is between this first preimpregnation material 230 and this base board unit 210, and this second preimpregnation material 250 has the 3rd surface 251, the 4th surface 252 and a plurality of openings 253, the 3rd surface 251 is towards this second surface 232 of this first preimpregnation material 230, and this opening 253 is formed at the 4th surface 252, preferably, this opening 253 runs through the 3rd surface 251 and the 4th surface 252, and this opening 253 is in alignment with this chip 220, in the present embodiment, this first preimpregnation material 230 has the characteristic of B-stage with this second preimpregnation material 250, this first preimpregnation material 230 is the semi-solid preparation colloidal state with this second preimpregnation material 250, so that this first preimpregnation material 230 has flowability with this second preimpregnation material 250; Then, see also Fig. 4 D, utilize this first preimpregnation material 230 of anchor clamps 20 semi-solid preparation of pressing simultaneously colloidal state, this heat radiating metallic layer 240, this second preimpregnation material 250 and this base board unit 210 of semi-solid preparation colloidal state, in addition, at this first preimpregnation material 230 of pressing, this heat radiating metallic layer 240, the step that also can heat and vacuumize in the process of this second preimpregnation material 250 and this base board unit 210, so that this first preimpregnation material 230 and these second preimpregnation material, 250 curing, and this first preimpregnation material 230 and this second preimpregnation material 250 can be filled between this chip 220 and this base board unit 210 smoothly; Afterwards, see also Fig. 4 E, after the pressing step is finished, this first preimpregnation material 230 covers this chip 220, this second preimpregnation material 250 is attached to this upper surface 211 of this base board unit 210 by pressing, and this second preimpregnation material 250 coats this projection 223, and a plurality of soldered balls 260 this lower surface 212 in this base board unit 210 then is set, and this soldered ball 260 connects this second connection gasket 214; At last, see also Fig. 4 F, cut this substrate strip 30 with form a plurality of lists from packaging structure 200.Because this first preimpregnation material 230 contains glass fiber material or filler (filler) with this second preimpregnation material 250, can increase structural strength and reliability with this base board unit 210.
See also Fig. 5, disclose another kind of heat sinking type chip packaging structure 200 according to another specific embodiment of the present invention, it comprises base board unit 210, chip 220, the first preimpregnation material 230 and heat radiating metallic layer 240, this base board unit 210 has upper surface 211, lower surface 212, a plurality of first connection gasket 213 and a plurality of second connection gaskets 214 that are formed at this lower surface 212 that are formed at this upper surface 211, this chip 220 is arranged at this upper surface 211 of this base board unit 210, this chip 220 has active face 221, the back side 222 and a plurality of projection 223, this projection 223 of this chip 220 electrically connects this first connection gasket 213 of this base board unit 210, this first preimpregnation material 230 has first surface 231 and second surface 232, this first preimpregnation material 230 covers this chip 220, this heat radiating metallic layer 240 is arranged at this first surface 231 of this first preimpregnation material 230 to promote heat radiation, preferably, this heat sinking type chip packaging structure 200 includes the second preimpregnation material 250 and a plurality of soldered ball 260 in addition, this second preimpregnation material 250 has the 3rd surface 251, the 4th surface 252 and one opening 253, this opening 253 is formed at the 4th surface 252, in the present embodiment, this opening 253 runs through the 3rd surface 251 and the 4th surface 252, this second preimpregnation material 250 is between this first preimpregnation material 230 and this base board unit 210, this chip 220 is arranged in this opening 253, and the 3rd surface 251 of this second preimpregnation material 250 connects this second surface 232 of this first preimpregnation material 230 with this chip 220 of complete coating and this projection 223, in another embodiment, this second preimpregnation material 250 is one-body molded with this first preimpregnation material 230, or be combined into one in advance, in the present embodiment, this second preimpregnation material 250 is attached to this upper surface 211 of this base board unit 210 by pressing, this soldered ball 260 is arranged at this lower surface 212 of this base board unit 210, and this soldered ball 260 connects this second connection gasket 214, with external circuits plate (figure does not draw).
In addition, see also Fig. 6, in another embodiment, this heat sinking type chip packaging structure 200 includes at least one plated-through-hole 270 in addition, this plated-through-hole 270 is formed in this first preimpregnation material 230 and this second preimpregnation material 250, this base board unit 210 has a plurality of the 3rd connection gasket 215, the three connection gaskets 215 in addition and is formed at this first connection gasket, 213 outsides, and this plated-through-hole 270 connects this heat radiating metallic layer 240 and the 3rd connection gasket 215.Preferably, when this heat radiating metallic layer 240 is a patterned line layer, another packaging structure (figure do not draw) can be set in these heat radiating metallic layer 240 tops, and by this plated-through-hole 270 electrically conduct this packaging structure and this heat sinking type chip packaging structure 200.
See also Fig. 7 A to Fig. 7 F, disclose another kind of heat sinking type chip packaging technology according to a specific embodiment more of the present invention, at first, see also Fig. 7 A, substrate strip 40 is provided, this substrate strip 40 includes a plurality of base board units 310, and each base board unit 310 has upper surface 311, lower surface 312, a plurality of first connection gasket 313 and a plurality of second connection gasket 314 that is formed at this lower surface 312 that is formed at this upper surface 311; Then, see also Fig. 7 B, a plurality of chips 320 this upper surface 311 in this base board unit 310 is set, and form at least one bonding wire 330 to electrically connect this chip 320 and this base board unit 310, in the present embodiment, the radian that this bonding wire 330 is bonded to this first connection gasket 313 of this chip 320 and this base board unit 310 is ultralow radian (ultra low loop), and the radian of this bonding wire 330 meets the edge of this chip 320; Afterwards, see also Fig. 7 C, the first preimpregnation material 340 and heat radiating metallic layer 350 are provided, this first preimpregnation material 340 has first surface 341 and second surface 342, this second surface 342 is towards a plurality of active faces 321 of this chip 320, this heat radiating metallic layer 350 is arranged at this first surface 341 of this first preimpregnation material 340, the material of this heat radiating metallic layer 350 is copper or surface treated copper layer, in this step, other comprises provides the second preimpregnation material 360, this second preimpregnation material 360 has the 3rd surface 361, the 4th surface 362 and a plurality of openings 363, this second preimpregnation material 360 can be piled up in advance by a plurality of preimpregnation materials and form, perhaps, this second preimpregnation material 360 can be one-body molded with this first preimpregnation material 340, this second preimpregnation material 360 is between this first preimpregnation material 340 and this base board unit 310, and the 3rd surface 361 is towards this second surface 342 of this first preimpregnation material 340, this opening 363 is formed at the 4th surface 362, preferably, this opening 363 runs through the 3rd surface 361 and the 4th surface 362, and this opening 363 is in alignment with this chip 320, this first preimpregnation material 340 has the characteristic of B-stage with this second preimpregnation material 360, this first preimpregnation material 340 is the semi-solid preparation colloidal state with this second preimpregnation material 360, so that this first preimpregnation material 340 has flowability with this second preimpregnation material 360; Afterwards, see also Fig. 7 D, utilize this first preimpregnation material 340 of anchor clamps 20 semi-solid preparation of pressing simultaneously colloidal state, this heat radiating metallic layer 350, this second preimpregnation material 360 and this base board unit 310 of semi-solid preparation colloidal state, so that this first preimpregnation material 340 and this second preimpregnation material 360 coat this chip 320 and this bonding wire 330, to replace known mould envelope technology, in addition, at this first preimpregnation material 340 of pressing, this heat radiating metallic layer 350, the step that also can heat in the process of this second preimpregnation material 360 and this base board unit 310 is so that this first preimpregnation material 340 solidifies with this second preimpregnation material 360; Then, see also Fig. 7 E, a plurality of soldered balls 370 this lower surface 312 in this base board unit 310 is set, this soldered ball 370 connects this second connection gasket 314; At last, see also Fig. 7 F, cut this substrate strip 40 with form a plurality of lists from packaging structure 300.Because this first preimpregnation material 340 contains glass fiber material or filler (filler) with this second preimpregnation material 360, can increase the structural strength with this base board unit 310.
See also Fig. 8, disclose another kind of heat sinking type chip packaging structure 300 according to a specific embodiment more of the present invention, it comprises base board unit 310, chip 320, at least one bonding wire 330, the first preimpregnation material 340 and heat radiating metallic layer 350, this base board unit 310 has upper surface 311, lower surface 312, a plurality of first connection gasket 313 and a plurality of second connection gaskets 314 that are formed at this lower surface 312 that are formed at this upper surface 311, this chip 320 is arranged at this upper surface 311 of this base board unit 310, this chip 320 electrically connects this first connection gasket 313 of this base board unit 310 with this bonding wire 330, this first preimpregnation material 340 has first surface 341 and second surface 342, this first preimpregnation material 340 covers this chip 320, this heat radiating metallic layer 350 is arranged at this first surface 341 of this first preimpregnation material 340 to promote heat radiation, preferably, this heat sinking type chip packaging structure 300 includes the second preimpregnation material 360 and a plurality of soldered ball 370 in addition, this second preimpregnation material 360 has the 3rd surface 361, the 4th surface 362 and one opening 363, this opening 363 is formed at the 4th surface 362, in the present embodiment, this opening 363 runs through the 3rd surface 361 and the 4th surface 362, this second preimpregnation material 360 is between this first preimpregnation material 340 and this base board unit 310, this chip 320 is arranged in this opening 363, and the 3rd surface 361 of this second preimpregnation material 360 connects this second surface 342 of this first preimpregnation material 340 with this chip 320 of complete coating, in another embodiment, this second preimpregnation material 360 is can be with this first preimpregnation material 340 one-body molded or be combined into one in advance, in the present embodiment, this second preimpregnation material 360 is attached to this upper surface 311 of this base board unit 310 by pressing, this soldered ball 370 is arranged at this lower surface 312 of this base board unit 310, and this soldered ball 370 connects this second connection gasket 314, with external circuits plate (figure does not draw).
In addition, see also Fig. 9, in another embodiment, this heat sinking type chip packaging structure 300 includes at least one plated-through-hole 380 in addition, this plated-through-hole 380 is formed in this first preimpregnation material 340 and this second preimpregnation material 360, this base board unit 310 has a plurality of the 3rd connection gasket 315, the three connection gaskets 315 in addition and is formed at this first connection gasket, 313 outsides, and this plated-through-hole 380 connects this heat radiating metallic layer 350 and the 3rd connection gasket 315.Preferably, when this heat radiating metallic layer 350 is a patterned line layer, another packaging structure (figure do not draw) can be set in these heat radiating metallic layer 350 tops, and by this plated-through-hole 380 electrically conduct this packaging structure and this heat sinking type chip packaging structure 300.
Protection scope of the present invention is when looking being as the criterion that accompanying Claim defines, and any variation and modification that those skilled in the art are done without departing from the spirit and scope of the present invention all belong to protection scope of the present invention.

Claims (9)

1. heat sinking type chip packaging technology, it comprises:
Substrate strip is provided, and this substrate strip includes at least one base board unit, and this base board unit has upper surface and lower surface;
At least one chip this upper surface in this base board unit is set, and this chip electrically connects this base board unit;
First preimpregnation material and the heat radiating metallic layer is provided, and this first preimpregnation material has first surface and second surface, and this heat radiating metallic layer is arranged at this first surface, and this second surface of this first preimpregnation material is towards this chip;
The second preimpregnation material is provided, this second preimpregnation material is the B-stage material, and between this first preimpregnation material and this base board unit, this second preimpregnation material has the 3rd surface, the 4th surface and at least one opening, this opening is formed at the 4th surface, the 3rd surface is towards this second surface of this first preimpregnation material, and this opening is in alignment with this chip; And
This first preimpregnation material of pressing simultaneously, this second preimpregnation material and this base board unit so that this first preimpregnation material covers this chip, and make this second preimpregnation material be attached to this base board unit.
2. heat sinking type chip packaging technology as claimed in claim 1, wherein this opening runs through the 3rd surface and the 4th surface.
3. heat sinking type chip packaging technology as claimed in claim 1, wherein this base board unit has a plurality of first connection gaskets in addition, and this chip has active face, the back side and a plurality of projection, and this projection connects this first connection gasket, and this second preimpregnation material coats this projection.
4. heat sinking type chip packaging technology as claimed in claim 3, it includes in addition: carry out one and vacuumize step, so that this second preimpregnation material is filled between this chip and this base board unit and coats this projection.
5. heat sinking type chip packaging structure, it comprises:
Base board unit, it has upper surface and lower surface;
Chip, it is arranged at this upper surface, and this chip electrically connects this substrate;
The first preimpregnation material, it has first surface and second surface, and this first preimpregnation material covers this chip; And
Heat radiating metallic layer, it is arranged at this first surface of this first preimpregnation material.
The second preimpregnation material, this second preimpregnation material is the B-stage material, and between this first preimpregnation material and this substrate, this second preimpregnation material has the 3rd surface, the 4th surface and at least one opening, this opening is formed at the 4th surface, the 3rd surface connects this second surface of this first preimpregnation material, and this chip is arranged in this opening.
6. heat sinking type chip packaging structure as claimed in claim 5, wherein this opening runs through the 3rd surface and the 4th surface.
7. heat sinking type chip packaging structure as claimed in claim 5, wherein this substrate has a plurality of first connection gaskets in addition, and this chip has a plurality of projections, and this projection connects this first connection gasket, and this second preimpregnation material coats this projection.
8. heat sinking type chip packaging structure as claimed in claim 5, it includes at least one plated-through-hole in addition, and it is formed in this first preimpregnation material and this second preimpregnation material.
9. heat sinking type chip packaging structure as claimed in claim 8, wherein this substrate has a plurality of the 3rd connection gaskets in addition, and the 3rd connection gasket is formed at this first connection gasket outside, and this plated-through-hole connects this heat radiating metallic layer and the 3rd connection gasket.
CN200810074323XA 2008-02-15 2008-02-15 Heat radiation type chip packaging process and structure thereof Active CN101226888B (en)

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CN102368481A (en) * 2011-10-11 2012-03-07 常熟市广大电器有限公司 High-strength chip packaging structure
CN102324409B (en) * 2011-10-11 2013-11-20 日月光半导体制造股份有限公司 Semiconductor package with heat dissipation structure and manufacturing method thereof
TWI594379B (en) * 2014-06-13 2017-08-01 矽品精密工業股份有限公司 Semiconductor package and a method for fabricating the same
TWI649839B (en) * 2017-03-15 2019-02-01 矽品精密工業股份有限公司 Electronic package and substrate structure thereof

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