CN101150552A - Bit-mapping scheme for 16APSK system for low-density parity-check coding - Google Patents

Abstract

A digital communication system having a transmitter that transmits a digital signal; and a receiver that receives the digital signal; wherein the digital signal utilizes the 16APSK system and uses Gray mapping to bit map the signal and is based on a pair of The values of the likelihood ratios rank the bits of the digital signal.

Description

Bit mapping scheme for 16APSK system for low-density parity check coding

Technical Field

The present invention relates to digital communications, and in particular to a bit mapping scheme for a 16APSK system for LDPC (low density parity check) coding.

RELATED APPLICATIONS

The present application relates to a patent serial number filed # # # entitled "A Bit Mapping Scheme for An LDPC Coded 32APSK System", and An application filed # # with a sequence number No. entitled "An Interleaving Scheme for An LDPC Coded 16APSK System".

Background

Communication systems use Forward Error Control (FEC) coding to ensure reliable transmission of data over noisy communication channels. Based on the shannon theory, these communication channels have a certain capacity expressed in bits per symbol at a certain signal-to-noise ratio (SNR), which is defined as the shannon limit. One of the research areas in communication and coding theory involves designing coding schemes that provide performance approaching shannon limits with reasonable complexity. LDPC codes using Belief Propagation (BP) decoding have been shown to have controllable encoding and decoding complexity and can provide performance approaching the shannon limit.

In a recent paper by Yan Li and William Ryan entitled "Bit-Reliability Mapping in LDPC-Codes Modulation systems" by IEEE Communications Letters, vol.9, no.1, january 2005, the authors investigated the performance of Modulation systems employing LDPC coding of 8 PSK. With the author's proposed bit reliability mapping strategy, a performance improvement of about 0.15dB over the non-interleaved scheme is achieved. The authors also show that gray mapping is more suitable for higher order modulation than other mapping schemes, such as natural mapping.

Disclosure of Invention

Various embodiments of the present invention relate to bit mapping schemes in 16APSK modulation systems. The techniques of these embodiments are particularly well suited for use with LDPC codes.

Gallager first described LDPC codes in the 60 s. The performance of the LDPC code is very close to the Shannon limit. A binary (N, K) LDPC code having a code length N and a dimension K is defined by a parity check matrix H of (N-K) rows and N columns. Most elements of the matrix H are zero and only a few elements are one, so the matrix H is sparse. Each row of the matrix H represents a checksum and each column represents a variable, e.g., a bit or a symbol. The LDPC code described by Gallager is regular, that is, the parity check matrix H has a constant row weight and column weight.

Regular LDPC codes can be extended to form irregular LDPC codes in which the row and column weights are varied. The irregular LDPC code is specified by degree distribution polynomials (x) and c (x) that define the degree distribution of variables and check nodes, respectively. More specifically, the irregular LDPC code may be defined as follows:

and

wherein the variable d _vmax And d _cmax Are the maximum variable node degree and the check node degree, respectively, and v _j (c _j ) Represents the fraction (fraction) of an edge (edge) emanating from a variable (check) node of degree j. While irregular LDPC codes are more complex to represent and/or implement than regular LDPC codes, both theoretically and empirically it has been shown that irregular LDPC codes with appropriately chosen degree distributions are superior to regular LDPC codes. FIG. 1 illustrates a parity check matrix representation of an exemplary irregular LDPC code having a codeword length of six.

LDPC codes may also be represented by bipartite graphs or Tanner graphs. In the Tanner graph, one set of nodes, called variable nodes (or bit nodes), corresponds to the bits of the codeword, while another set of nodes, called constraint nodes (or check nodes), corresponds to a set of parity check constraints defining the LDPC code. The bit nodes and check nodes are connected by edges and are considered to be adjacent or neighboring if they are connected by edges. In general, it is assumed that a pair of nodes is connected by at most one edge.

FIG. 2 illustrates a bipartite graph representation of an irregular LDPC code as shown in FIG. 1.

LDPC codes can be decoded in a variety of ways, such as majority logic decoding and iterative decoding. LDPC codes are mostly logically decodable because of the structure of their parity check matrix. While most logical decoding requires minimal complexity and can achieve reasonably good error performance for some types of LDPC codes (e.g., euclidean geometry LDPC and projection geometry LDPC codes) with relatively high column weights in the parity check matrix, iterative decoding methods gain more attention because of their better performance versus complexity trade-off. Unlike most logical decoding, iterative decoding improves the reliability of each symbol by backtracking the received symbol based on constraints that define the pattern. In the first iteration, the iterative decoder uses only the channel output as input and produces a reliability output for each symbol.

The reliability metric output for the decoded symbol at the end of each decoding iteration process is then used as input for the next iteration. The decoding process ends until a stop condition is met, after which a final decision is made based on the decoded symbol output reliability metric from the last iteration. Iterative decoding algorithms can be further divided into hard decision, soft decision and hybrid decision algorithms, depending on the different characteristics of the reliability metrics used during each iteration. The corresponding commonly used algorithms are the iterative Bit Flipping (BF), belief Propagation (BP) and Weighted Bit Flipping (WBF) decoding algorithms, respectively. It has been demonstrated that the BP algorithm is capable of maximum likelihood decoding when the corresponding Tanner graph is acyclic, and thus it is the most popular decoding method.

BP of the LDPC code is a kind of message passing decoding (message passing decoding). The information sent along the edges of the graph is the log-likelihood ratios associated with the variable nodes corresponding to the codeword bits

In this expression, p ₀ And p ₁ Respectively representing the value of the relevant bitA probability of 0 or 1. BP decoding typically comprises two steps, a horizontal step and a vertical step. In the horizontal step, each check node c _m Will be based on the bit b in addition to _n All but entry check c _m Is sent to the adjacent node b _n . In the vertical step, each bit node b _n Will be based on other than from check node c _m All outer incoming bits b _n Is sent to the adjacent check node c _m . These two steps are repeated until a usable codeword is found or the maximum number of iterations is reached.

Irregular LDPC codes are one of the best choices for many applications because they exploit the significant performance of BP decoding. Various communication and storage standards, such as DVB-S2/DAB, wireline ADSL, IEEE802.11n and IEEE802.16, etc., have adopted, or are under consideration to adopt, various irregular LDPC codes.

The threshold of the LDPC code is defined as a minimum SNR value at which the bit error probability can be made arbitrarily small as the codeword length approaches infinity. The value of the LDPC code threshold can be determined by an analysis tool called density evolution (density evolution).

The concept of density evolution can also be traced back to Gallager's results. To determine the performance of BF decoding, gallager derives a calculation formula for the output BER at each iteration as a function of the input BER at the start of the iteration, and may iteratively calculate the BER at a given number of iterations. For continuous character tables (alphabe)t), the calculation is more complicated. A probability density function (pdf) of the confidence messages exchanged between the bits and the check nodes needs to be computed one after another and the average BER for each iteration is derived based on these pdfs. In both check node processing and bit node processing, each outgoing confidence information is a function of the incoming confidence information. Degree of convergence d _c Each outgoing information U can be represented by d _c -1 functional representation of incoming information,

wherein, F _c Representing the check node processing function determined from BP decoding. Similarly, for degree d _v Each outgoing information V can be represented by d _v -1 incoming messages and channel configuration messages U _ch Is indicative of the function of (a) to (b),

wherein, F _v Representing the bit node processing function. Although for checksum bit node processing, the pdf of the inbound information may be derived based on it for a given decoding algorithm, there may be an exponentially large number of possible forms of inbound information. Therefore, the density evolution process seems difficult. Fortunately, it has been demonstrated that for a given information transfer algorithm and noisy channel, the decoded BER is independent of the transmitted sequence x if some symmetry condition is met. That is, based on the symmetry assumption, the decoded BER of the all-zero transmission sequence x =1 is the same as that of the arbitrarily randomly selected sequence, and thus the derivation of the density evolution can be significantly simplified. The symmetry conditions required for efficient density evolution are channel symmetry, check node symmetry, and bit node symmetry. Another assumption for density evolution is that the Tanner graph is acyclic (cyclic free).

According to these assumptions, the incoming information to the bits and check nodes is independent, and thus the derivation of the pdf of the information can be significantly simplified. For many LDPC codes that have practical roles, the corresponding Tanner graph includes a cycle. When the minimum length of the cycle (or girth) in the Tanner graph of an LDPC code is equal to 4 × l, then the independence assumption does not hold after the l-th decoding iteration when using standard BP decoding. However, for a given number of iterations, as the code length increases, independent conditions can be satisfied for the increased number of iterations. Therefore, density evolution can predict the asymptotic performance of a set of LDPC codes, and the so-called "asymptotic" property needs to be in the sense of code length.

According to various embodiments of the present invention, a bit mapping scheme provides a good threshold for LDPC codes. In addition, the bit mapping scheme can facilitate the design of interleaving settings in a 16APSK modulation system.

According to various embodiments of the present invention, the disclosed bit mapping provides good performance of LDPC coded 16APSK systems and simplifies the interleaving setup in 16APSK systems.

According to various embodiments of the present invention, a method for bit mapping in a 16APSK system using FEC codes comprises: transmitting a digital signal from a transmitter; and receiving a digital signal at the receiver, wherein the digital signal utilizes a 16APSK system with FEC encoding, and bit mapping the signal prior to transmission according to the formula represented in fig. 4.

According to various embodiments of the present invention, the FEC code is a regular LDPC code.

According to various embodiments of the present invention, the FEC code is an irregular LDPC code.

According to various embodiments of the present invention, the FEC code is a regular repeating accumulated code.

According to various embodiments of the present invention, the FEC code is an irregular repeat accumulate code.

According to various embodiments of the present invention, a digital communication system comprises: a transmitter for transmitting a digital signal; and a receiver receiving the digital signal; wherein the digital signal utilizes a 16APSK system with FEC encoding and the signal is bit mapped according to the formula shown in fig. 4 prior to transmission.

According to various embodiments of the present invention, a digital communication system comprises: a transmitter which transmits a digital signal; and a receiver receiving the digital signal; wherein the digital signal utilizes a 16APSK system with FEC encoding and the signal is mapped using gray mapped bits and bits of the digital signal are ordered based on values of log likelihood ratios from the communication channel.

Drawings

The present invention is illustrated by way of example, and not by way of limitation, in the accompanying drawings. In the drawings wherein like reference numerals represent similar parts throughout the several views:

FIG. 1 is a parity check matrix representation of an exemplary irregular LDPC code of codeword length six;

FIG. 2 illustrates a bipartite graph representation of an irregular LDPC code as shown in FIG. 1;

FIG. 3 illustrates a bit mapping function in 16APSK modulation, in accordance with various embodiments of the invention; and

FIG. 4 illustrates bit mapping for a 16APSK symbol, in accordance with various embodiments of the invention;

FIG. 5 illustrates an example of a communication system employing LDPC codes and 16APSK modulation in accordance with various embodiments of the present invention;

FIG. 6 illustrates an example of a transmitter employing the 16APSK modulation of FIG. 5, in accordance with various embodiments of the invention; and

fig. 7 illustrates an example of a receiver employing 16APSK modulation in fig. 5, in accordance with various embodiments of the invention.

Detailed Description

A detailed description is given of a bit mapping method using exemplary encoding of an LDPC code according to various embodiments of the present invention with reference to the accompanying drawings.

Although the present invention is described in terms of LDPC codes, it should be appreciated that the bit mapping method may be used in other codes as well. Additionally, it should be understood that the method may be implemented in a non-coded system.

Fig. 5 is an exemplary diagram of a communication system employing LDPC codes with 16APSK modulation in accordance with various embodiments of the present invention. The exemplary communication system includes a transmitter 501 that generates a signal waveform over a communication channel 502 to a receiver 503. The transmitter 501 includes an information source for generating a discrete set of possible information. Each of these pieces of information corresponds to a signal waveform. The waveform enters the channel 502 and is corrupted by noise. LDPC codes are employed to reduce interference introduced by channel 502 and 16APSK modulation schemes are employed to convert LDPC coded bits into signal waveforms.

Fig. 6 depicts an exemplary transmitter in the communication system of fig. 5, which employs LDPC codes and 16APSK modulation. LDPC encoder 602 encodes the information bits from source 601 into LDPC codewords. The mapping from each information block to each LDPC codeword is determined by the parity check matrix (or equivalent generator matrix) of the LDPC code. The LDPC codeword is interleaved and modulated into a signal waveform based on the 16APSK bit mapping scheme by the interleaver/modulator 603. These signal waveforms are sent to the transmit antenna 604 and propagated to the receiver as shown in fig. 7.

Fig. 7 depicts the exemplary receiver of fig. 5 employing an LDPC code and a 16APSK demodulator. The signal waveform is received by a receiving antenna 701 and distributed to a demodulator/deinterleaver 702. The signal waveform is demodulated by a demodulator and deinterleaved by a deinterleaver, and then distributed to an LDPC decoder 703 that iteratively decodes the received message and outputs an estimate of the transmitted codeword. The 16APSK demodulation rules employed by the demodulator/deinterleaver 702 should match the 16APSK modulation rules employed by the interleaver/modulator 603.

According to various embodiments of the invention, an exemplary 16APSK bit-to-symbol mapping is shown in FIG. 3The circuit uses four bits per operation (b) _4i ，b _4i+1 ，b _4i+2 ，b _4i+3 ) And map them to I and Q values, where I =0,1, 2. The bit mapping logic is shown in fig. 4. According to various embodiments of the present invention, the mapping of bits is defined by:

the bit mapping scheme of fig. 4 uses gray mapping, meaning that the binary representations of neighboring points differ by only one bit, in accordance with various embodiments of the present invention. Density evolution analysis shows that the exemplary gray mapping scheme can provide the best threshold given the LDPC coded 16APSK system. The bit mapping scheme of fig. 4 also arranges the bits in an order based on the values of the log-likelihood ratios from the communication channels. This process simplifies the design of the interleaving scheme for the 16APSK system.

Although the present invention has been described by way of exemplary embodiments, it should be understood that numerous other variations and modifications could be made within the spirit and scope of the invention. Therefore, it is the object of the appended claims to cover all such modifications and variations as come within the true spirit and scope of the invention.

Claims (10)

1. A method of number mapping in a 16APSK system, the method comprising:

transmitting a digital signal from a transmitter; and

receiving the digital signal at a receiver;

wherein the digital signal is bit mapped prior to transmission according to the following equation, wherein R ₁ Is the radius of the inner ring and R ₂ Is the radius of the outer ring:

2. the method of claim 1, wherein the system uses FEC codes.

3. A digital communication system, comprising:

a transmitter for transmitting the digital signal is provided,

wherein the digital signal uses a 16APSK system with FEC encoding and the signal is bit mapped using gray mapping and bits of the digital signal are ordered based on values of log likelihood ratios from the communication channel.

4. The method of claim 3, wherein the FEC code is a regular LDPC code.

5. The method of claim 3, wherein the FEC code is an irregular LDPC code.

6. The method of claim 3, wherein the FEC code is a regular repeating accumulation code.

7. The method of claim 3, wherein the FEC code is an irregular repeat accumulate code.

8. A digital communication system, comprising:

a transmitter for transmitting a digital signal, wherein for i =0,1,2 _4i ，b _4i+1 ，b _4i+2 ，b _4i+3 ) Is modulated as a 16APSK symbol:

wherein R is ₁ Is the radius of the inner ring and R ₂ Is the radius of the outer ring.

9. A digital communication system, comprising:

a receiver for receiving a digital signal, wherein the receiver comprises a demodulator for mapping 16APSK symbols to a four-ratio based on the following 16APSK constellation definitionSpecific group (b) _4i ，b _4i+1 ，b _4i+2 ，b _4i+3 ) Message evaluation of composition:

wherein R is ₁ Is the radius of the inner ring and R ₂ Is the radius of the outer ring.

10. A computer readable medium storing a computer program in which, for i =0,1,2 _4i ，b _4i+1 ，b _4i+2 ，b _4i+3 ) Mapping to 16APSK symbols:

wherein R is ₁ Is the radius of the inner ring and R ₂ Is the radius of the outer ring.

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