CN100590850C - Fabrication method of fully self-aligned strip gate power vertical double diffused field effect transistor - Google Patents

Abstract

The invention relates to the technical field of semiconductor devices and integrated circuit manufacturing technology, and discloses a method for manufacturing a fully self-aligned strip gate power DMOS transistor, including: A. growing epitaxy on a substrate, and then performing field oxidation to form a field Oxide layer; B. Etching the field oxide layer in the active area, performing gate oxidation, depositing polysilicon, and doping the deposited polysilicon; C. Performing photolithography, etching, and boron implantation on the doped polysilicon. High-temperature advancement to form a P-well region; D. Perform arsenic implantation on polysilicon to form a shallow source region, then deposit and reverse etch to form sidewalls; E. Perform boron implantation on polysilicon and deposit a cobalt film to form a cobalt silicide, Using cobalt silicide to form P-well contacts; F. performing borophosphosilicate glass deposition, photolithography and etching lead holes; G. metal sputtering and performing photolithography and etching. The invention simplifies the manufacturing process, reduces the manufacturing cost and improves the operating frequency of the power DMOS transistor.

Description

Fabrication method of fully self-aligned strip gate power vertical double diffused field effect transistor

technical field

The invention relates to the technical field of semiconductor devices and integrated circuit manufacturing techniques, in particular to a method for manufacturing a fully self-aligned strip gate power vertical double-diffusion field-effect transistor (VerticalDouble-diffusion MOSFET, DMOS).

Background technique

Power DMOS transistors have been widely used in various electronic devices. Power DMOS transistors have the characteristics of fast switching speed, high input impedance, low driving power consumption, good frequency characteristics, highly linear transconductance, etc., and have a negative temperature coefficient, no secondary breakdown problem of bipolar power transistors, and a large safe working area . Therefore, whether it is a switching application or a linear application, DMOS transistors are ideal power devices.

In the traditional power DMOS transistor manufacturing process, the polysilicon boundary is used as the alignment point, and the uniform channel length in the entire chip is realized through P-well and N+ source alignment implantation. However, in order to form a good contact between the metal and the P-well and the N+ source, two photolithography masks (P-well contact injection mask, N+ source injection mask) are usually required, and a total of 7 to 9 masks are required. , It is not conducive to the reduction of the chip area, the process is complicated, and the cost of the chip is high; at the same time, polysilicon is used as the gate interconnection, and the series resistance is large, which limits the increase of the operating frequency.

Contents of the invention

(1) Technical problems to be solved

In view of this, the main purpose of the present invention is to provide a method for manufacturing a fully self-aligned strip gate power vertical double-diffused field effect transistor, so as to simplify the manufacturing process, reduce the manufacturing cost, and increase the operating frequency of the power DMOS transistor.

(2) Technical solution

In order to achieve the above object, the present invention provides a method for making a fully self-aligned strip gate power vertical double-diffused field effect transistor, the method comprising:

A. Epitaxy is grown on the substrate, and then field oxidation is performed to form a field oxide layer;

B. Etching the field oxide layer in the active region, performing gate oxidation, depositing polysilicon, and doping the deposited polysilicon;

C. Perform photolithography and etching on the entire doped silicon wafer, boron implantation, and high-temperature advancement to form a P-well region;

D. Perform arsenic implantation on the entire silicon wafer to form a shallow source region, then deposit and reverse etch to form side walls;

E. Boron implantation is performed on the entire silicon wafer, and a cobalt film is deposited to form a cobalt silicide, and a P-well contact is formed using the cobalt silicide;

F. Carry out borophosphosilicate glass deposition, photolithography and etching lead holes;

G. Metal sputtering and photolithography and etching.

In the above scheme, the step A includes: growing an n-type Si epitaxial layer on an n+ type Si substrate, followed by field region oxidation to form a field oxide layer on the n-type Si epitaxial layer.

In the above scheme, the step B includes: using a field oxygen etching mask to define the active area on the field oxide layer, after defining the active area, etching away the field oxide layer in the active area, and then performing gate oxidation, And deposit polysilicon, and then perform a high-temperature phosphorus diffusion on the polysilicon at 1000°C to form n+ type polysilicon with low resistivity less than 10Ω/sq.

In the above scheme, the step C includes: using polysilicon to etch the mask plate, etching the entire doped silicon wafer, and then performing boron implantation on the entire etched silicon wafer and performing high-temperature advancement at 1100°C to form P- well area.

In the above scheme, performing arsenic implantation on the entire silicon wafer as described in step D uses polysilicon as a mask to perform arsenic implantation on the entire silicon wafer;

Depositing and etching back to form sidewalls in step D is to deposit a layer of orthoethyl silicate TEOS, and to etch back the deposited TEOS to form sidewalls.

In the above scheme, the step E includes: performing a high energy of 90keV and a large dose of boron implantation of 2×10 ¹⁵ n/cm ² on the entire silicon wafer, the high energy enables the implanted boron ions to pass through the N+ source region, and the main distribution Under the N+ source region, a large dose makes the P-well region form a high-concentration P+ region, which is conducive to the formation of ohmic contacts; then deposit a cobalt film and anneal quickly at 670 ° C for 5 seconds to make cobalt and silicon react to form cobalt silicide , carve off the unreacted cobalt on the side wall, and then quickly anneal at 800°C for 10 seconds to turn the silicide into a low-resistance state of 16-18μΩ.cm; then use cobalt silicide to penetrate the source region of the shallow source junction structure and The underlying P-well forms a contact.

In the above solution, the step F includes: performing borophosphosilicate glass deposition, performing high temperature reflow at 950° C., and using a contact hole etching mask to perform lead hole photolithography and etch the lead hole.

In the above solution, the step G includes: sputtering the metal layer, and using a metal etching mask to perform photolithography and etching on the metal layer to form a fully self-aligned strip gate power vertical double-diffused field effect transistor.

(3) Beneficial effects

As can be seen from the foregoing technical solutions, the present invention has the following beneficial effects:

1. The method for making fully self-aligned strip gate power vertical double-diffused field-effect transistors provided by the present invention adopts the strip gate structure design, and the strip gate DMOS is a new type of planar structure DMOS. Its polysilicon gate distributed in stripes. The strip gate structure can integrate a larger channel width per unit active area, and at the same time, the contact hole area of the source area is increased, and the gate area is reduced. It has the characteristics of small on-resistance, high switching speed and good working stability. .

2. The method for making the full self-aligned strip gate power vertical double-diffusion field-effect transistor provided by the present invention has few photolithographic reticles and needs 4 photolithographic reticles altogether, including field oxygen etching reticles, The polysilicon etching mask, the contact hole etching mask, and the metal etching mask greatly simplify the manufacturing process and reduce the manufacturing cost.

3. The method for making a fully self-aligned strip gate power vertical double-diffused field effect transistor provided by the present invention adopts an N+ shallow source junction so that the silicide behind can penetrate the N+ source region and contact the P- well below .

4. The method for making a fully self-aligned strip gate power vertical double-diffused field-effect transistor provided by the present invention adopts a sidewall process, and deposits a layer of orthoethyl silicate (TEOS) after etching the entire silicon wafer. And back etched to form side walls, in order to carry out the following P-well contact implantation.

5. In the method for making a fully self-aligned strip gate power vertical double-diffusion field effect transistor provided by the present invention, the P-well contact implantation adopts high-energy and large-dose boron implantation, and the purpose of high energy is to make boron penetrate the N+ source region , mainly concentrated in the P-well region, the purpose of a large dose on the one hand can make the following silicide and P-well form a good ohmic contact, on the other hand can reduce the reverse depletion width of the PN junction in the P-well region, Improve device reverse withstand voltage. In this step, the P-well contact implantation mask in the traditional DMOS process is omitted, and the contact implantation of the P-well region is formed by using the sidewall as a mask.

6. The method for manufacturing a fully self-aligned strip gate power vertical double-diffused field effect transistor provided by the present invention uses cobalt silicide. Deposit the cobalt film and anneal rapidly at 670°C for 5 seconds to make the cobalt and silicon react to form silicide. Carve off the unreacted cobalt on the side wall, and then quickly anneal at 800°C for 10 seconds to turn the silicide into a low-resistance state. Because the N+ source region has a shallow source junction structure, the cobalt silicide in the N+ source region penetrates the source region and contacts the P- well below. In addition, the use of cobalt makes the polysilicon gate form a silicide form with low resistivity, which reduces the series resistance of the gate of the device, and is beneficial to improve the switching speed and operating frequency of the device.

Description of drawings

Fig. 1 is the flow chart of the method for making full self-aligned strip gate power DMOS transistor provided by the present invention;

2 is a schematic diagram of the layout of a fully self-aligned strip gate power DMOS transistor according to an embodiment of the present invention;

Fig. 3 is a process flow chart of making a fully self-aligned strip gate power DMOS transistor according to an embodiment of the present invention; wherein,

Fig. 3-1 is a schematic diagram of epitaxial layer growth and field region oxidation according to an embodiment of the present invention;

Fig. 3-2 is a schematic diagram of defining active region etching, field oxide layer gate oxidation and depositing polysilicon according to an embodiment of the present invention;

3-3 is a schematic diagram of etching the entire silicon wafer and the remaining field oxide layer according to an embodiment of the present invention;

3-4 are schematic diagrams of forming a P-well region by boron implantation according to an embodiment of the present invention;

3-5 are schematic diagrams of performing arsenic implantation on a silicon wafer to form a shallow junction N+ source region according to an embodiment of the present invention;

3-6 are schematic diagrams of depositing tetraethyl orthosilicate (TEOS) and etching back to form sidewalls according to an embodiment of the present invention;

3-7 are schematic diagrams of performing high-energy and large-dose boron implantation on the entire silicon wafer according to an embodiment of the present invention;

3-8 are schematic diagrams of depositing a cobalt film to form a silicide according to an embodiment of the present invention;

3-9 are schematic diagrams of borophosphosilicate glass deposition, photolithography and etching lead holes according to an embodiment of the present invention;

3-10 are schematic diagrams of metal sputtering followed by photolithography and etching according to an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

As shown in Figure 1, Figure 1 is a flow chart of a method for making a fully self-aligned strip gate power DMOS transistor provided by the present invention, the method includes the following steps:

Step 101: growing epitaxy on the substrate, and then performing field oxidation to form a field oxide layer;

Step 102: etching the field oxide layer of the active region, performing gate oxidation, depositing polysilicon, and doping the deposited polysilicon;

Step 103: Perform photolithography and etching on the entire doped silicon wafer, boron implantation, and high-temperature advancement to form a P-well region;

Step 104: performing arsenic implantation on the entire silicon wafer to form a shallow source region, and then depositing and etching back to form side walls;

Step 105: perform boron implantation on the entire silicon wafer, and deposit a cobalt film to form a cobalt silicide, and use the cobalt silicide to form a P-well contact;

Step 106: performing borophosphosilicate glass deposition, photolithography and etching lead holes;

Step 107: metal sputtering and photolithography and etching.

Based on the flow chart of the method for fabricating a fully self-aligned strip-gate power DMOS transistor shown in FIG. 1 , the method for fabricating a fully self-aligned strip-gate power DMOS transistor of the present invention will be further described in detail below in conjunction with specific embodiments.

The method for making a fully self-aligned strip gate power DMOS transistor provided by the present invention has a simple process and fewer photolithography masks, and realizes full self-alignment of P-well implantation, N+ source implantation, and P-well contact implantation . In this embodiment, a strip gate structure is adopted, and the layout style is shown in FIG. 2 . FIG. 2 is a schematic diagram of the layout of a fully self-aligned strip gate power DMOS transistor fabricated according to an embodiment of the present invention.

Below in conjunction with accompanying drawing 3, the preparation method of fully self-aligned strip gate power DMOS transistor is further explained:

As shown in Figure 3-1, on an n+ type Si substrate, an n-type Si epitaxial layer is grown, followed by field oxidation to form a field oxide layer on the n-type Si epitaxial layer.

As shown in Figure 3-2, the first mask (field oxygen etching mask) is used to define the active area on the field oxide layer. After the active area is defined, the field oxide layer in the active area is etched away. Then gate oxidation is performed, and polysilicon is deposited, followed by a high temperature phosphorus diffusion of 1000°C on the polysilicon to form n+ type polysilicon with low resistivity less than 10Ω/sq.

As shown in FIG. 3-3, use the second mask (polysilicon etching mask) to etch the entire doped silicon wafer and the remaining field oxide layer.

As shown in Figure 3-4, perform boron implantation on the entire silicon wafer after etching and carry out high-temperature advancement at 1100°C to form a P-well region.

As shown in Figure 3-5, silicon wafers are implanted with arsenic. In this step, arsenic implantation is performed instead of phosphorus implantation in the traditional DMOS process. The purpose is to form a shallow junction N+ source region. Silicon wafers are implanted.

As shown in Figure 3-6, a layer of orthoethyl silicate (TEOS) is deposited and etched back to form sidewalls for the following P-well contact implantation.

As shown in Figure 3-7, the entire silicon wafer is implanted with a large energy of 90keV and a large dose of boron of 2×10 ¹⁵ n/cm ^2. The high energy allows the implanted boron ions to pass through the N+ source region, mainly distributed in the N+ Under the source, a large dose makes the P-well region form a high-concentration P+ region, which is conducive to the formation of a good ohmic contact.

As shown in Figure 3-8, a cobalt film is deposited and rapidly annealed at 670°C for 5 seconds to make cobalt and silicon react to form silicide. Carve off the unreacted cobalt on the side wall, and then quickly anneal at 800°C for 10 seconds to convert the silicide into a low resistance state of 16-18μΩ.cm. Because the N+ source region has a shallow source junction structure, the cobalt silicide in the N+ source region penetrates the source region and contacts the P- well below.

As shown in Figure 3-9, borophosphosilicate glass is deposited and reflowed at a high temperature of 950°C, and the third mask (contact hole etching mask) is used to perform lead hole photolithography and etch the lead hole.

As shown in Figure 3-10, the metal layer is finally sputtered, and the metal layer is photoetched and etched using the fourth mask (metal etching mask).

In the above embodiments, the strip gate structure design is adopted, and the strip gate DMOS is a new type of DMOS with a planar gate structure, and its polysilicon gates are distributed in strips. P-well, P-well contact implantation, and N+ source implantation all adopt self-alignment process, no need to add photolithography mask, only 4 masks are needed, the process is simple, and the chip processing cost is reduced. At the same time, the adoption of the silicide process can effectively reduce the gate series resistance and increase the operating frequency of the power DMOS transistor. The N+ source mask in the traditional DMOS process is omitted, and only polysilicon is used as a mask; arsenic implantation is performed instead of phosphorus implantation in the traditional DMOS process, and the purpose is to form a shallow junction N+ source region. The P+ well contact injection template in the traditional DMOS process is omitted, and the sidewall is used as a mask.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (8)

1. A method for making a fully self-aligned strip gate power vertical double-diffused field-effect transistor, characterized in that the method comprises: A. Epitaxy is grown on the substrate, and then field oxidation is performed to form a field oxide layer; B. Etching the field oxide layer in the active region, performing gate oxidation, depositing polysilicon, and doping the deposited polysilicon; C. Perform photolithography and etching on the entire doped silicon wafer, boron implantation, and high-temperature advancement to form a P-well region; D. Perform arsenic implantation on the entire silicon wafer to form a shallow source region, then deposit and reverse etch to form side walls; E. Boron implantation is performed on the entire silicon wafer, and a cobalt film is deposited to form a cobalt silicide, and a P-well contact is formed using the cobalt silicide; F. Carry out borophosphosilicate glass deposition, photolithography and etching lead holes; G. Metal sputtering and photolithography and etching. 2. The method for manufacturing a fully self-aligned strip gate power vertical double-diffused field-effect transistor according to claim 1, wherein said step A comprises: On the n+ type Si substrate, an n-type Si epitaxial layer is grown, followed by field oxidation to form a field oxide layer on the n-type Si epitaxial layer. 3. The method of manufacturing a fully self-aligned strip gate power vertical double-diffused field-effect transistor according to claim 1, wherein the step B includes: Use the field oxygen etching mask to define the active area on the field oxide layer. After defining the active area, etch away the field oxide layer in the active area, then perform gate oxidation, and deposit polysilicon, and then conduct a polysilicon Phosphorus diffuses at a high temperature of 1000°C to form n+ type polysilicon with low resistivity less than 10Ω/sq. 4. The method for manufacturing a fully self-aligned strip gate power vertical double-diffused field effect transistor according to claim 1, wherein said step C comprises: Using polysilicon to etch the mask plate, etch the whole doped silicon wafer, then perform boron implantation on the whole etched silicon wafer and carry out high-temperature advancement at 1100°C to form a P-well region. 5. The method for manufacturing a fully self-aligned strip gate power vertical double-diffused field-effect transistor according to claim 1, wherein the arsenic implantation to the entire silicon wafer in step D is performed using polysilicon as a mask , perform arsenic implantation on the entire silicon wafer; Depositing and etching back to form sidewalls in step D is to deposit a layer of orthoethyl silicate TEOS, and to etch back the deposited TEOS to form sidewalls. 6. The method for manufacturing a fully self-aligned strip gate power vertical double-diffused field effect transistor according to claim 1, wherein the step E includes: The entire silicon wafer is implanted with a high energy of 90keV and a large dose of boron of 2×10 ¹⁵ n/cm ^2. The high energy enables the implanted boron ions to pass through the N+ source region and mainly distribute under the N+ source region. The P-well region forms a high-concentration P+ region, which is conducive to the formation of ohmic contacts; Then deposit cobalt film, anneal quickly at 670°C for 5 seconds, make cobalt and silicon react to form cobalt silicide, carve off the unreacted cobalt on the side wall, and then anneal quickly at 800°C for 10 seconds to convert the silicide to 16-18μΩ .cm low resistance state; Cobalt silicide is then used to penetrate the source region of the shallow source junction structure and form contact with the underlying P-well. 7. The method for manufacturing a fully self-aligned strip gate power vertical double-diffused field-effect transistor according to claim 1, wherein said step F comprises: Carry out borophosphosilicate glass deposition, and carry out the high temperature reflow of 950 ℃, use the contact hole etching mask to carry out lead hole photolithography and etch lead hole. 8. The method for manufacturing a fully self-aligned strip gate power vertical double-diffused field effect transistor according to claim 1, wherein said step G comprises: The metal layer is sputtered, and the metal layer is photoetched and etched using a metal etching mask to form a fully self-aligned strip gate power vertical double-diffused field effect transistor.

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