CN100587845C - Semiconductor memory device that transmits voltage to selected word lines using only single-channel transistors - Google Patents

Abstract

A semiconductor memory device disclosed herein comprises a memory cell array in which memory cells are arranged in a matrix and a row decoder circuit for selecting a word line in this memory cell array and for applying a voltage to the selected word line. The decoder circuit includes a plurality of first transistors of a first conductivity type in which one end of each current path is directly connected to each of the word lines, and a second transistor of a second conductivity type opposite to the first conductivity type for applying a voltage to a gate of the first transistor connected to aselected word line at the time of the operation for applying a voltage to the selected word line. The application of a voltage to the selected word line is performed only by the first transistor of the first conductivity type.

Description

Semiconductor memory device that transmits voltage to selected word lines using only single-channel transistors

This application is a divisional application of the invention patent application with the application number 01120869.4, the application date is June 8, 2001, and the invention title is "semiconductor storage device that only uses single-channel transistors to transmit voltage to selected word lines".

technical field

The present invention relates to a semiconductor storage device, and more specifically to a nonvolatile semiconductor storage device such as a NAND cell, a NOR cell, a DINOR cell, and an AND cell type EEPROM.

Background technique

Conventionally, an electrically rewritable EEPROM is known as a semiconductor memory device. What is striking is that the NAND cell type EEPROM, in which a plurality of memory cells are connected in series to form a NAND cell block, can be highly integrated.

A memory cell, one of the NAND cell types EEPEOM, has a FET-MOS structure in which a floating gate (charge storage layer) and a control gate are laminated on a semiconductor substrate with a spacer insulating film interposed therebetween. Then a plurality of adjacent memory cells are connected in series in the form of sharing the source and drain to form a NAND cell, which is connected to the bit line as a cell. Such NAND cells are arranged in a matrix to form a memory cell array. The memory cell array is integrated on a p-type semiconductor substrate, or in a p-type well region.

The drains at one end of the NAND cells arranged in the column direction of the memory cell array are commonly connected to the bit line via select gate transistors, and the sources at the other end are also connected to the common source line through the select gate transistors. The control gates of the memory transistors and the gate electrodes of the select gate transistors are commonly connected as control gate lines (word lines) and select gate lines in the row direction of the memory cell array.

The operation of this NAND cell type EEPROM is as follows. The data writing operation is mainly performed sequentially from the memory cell at the farthest position from the bit line contact. First, when the data write operation starts, the bit line is given 0V ("1" data write bit line) or power supply voltage Vcc ("0" data write bit line) according to the write data, and the selected bit line is given The select gate line on the contact side is Vcc. In this case, in the selected NAND cell connected to the "1" data writing bit line, the channel part in the NAND cell is fixed at 0V via the selection gate transistor. On the other hand, in the selected NAND cell connected to the "0" data writing bit line, the channel part in the NAND cell is charged to [Vcc-Vtsg] (Vtsg is the selection gate After the threshold voltage of the pole transistor), it becomes a floating state. Next, select the control gate line in the selected memory cell in the NAND cell from 0V to Vpp (=20V: a high voltage for writing), and select another control gate line in the NAND cell from 0V to Vmg (= 10V: intermediate voltage).

In the selected NAND cell connected to the "1" data writing bit line, since the channel part in the NAND cell is fixed at 0V, the control gate line side of the selected memory cell in the selected NAND cell ( =Vpp potential) and the channel portion (=0V) have a large potential difference (=20V), and electron injection occurs from the channel portion to the floating gate. Therefore, the threshold voltage of the selected memory cell changes to the positive direction, and writing of "1" data ends.

On the contrary, in the selected NAND cell connected to the "0" data writing bit line, since the channel part in the NAND cell is in a floating state, since the control gate line and the channel in the selected NAND cell Influenced by capacitive coupling between parts, the potential of the channel part rises from [Vcc-Vtsg] potential to Vmch (=8V) while maintaining the floating state as the voltage of the control gate line rises (0V→Vpp, Vmg). At this time, since the potential difference between the control gate line (=Vpp potential) and the channel portion (=Vmch) of the selected memory cell in the selected NAND cell is as small as 12V, electron injection does not occur. Therefore, the threshold voltage of the selected memory cell is maintained in a negative state without changing.

Data erasing is performed simultaneously on all the memory cells in the selected NAND cell block. That is, all the control gate lines in the selected NAND cell block are set to 0V, and the control in the bit line, source line, p-type well region (or p-type semiconductor substrate), and non-selected NAND cell block A high voltage of 20V is applied to the gate lines and all the select gate lines. As a result, electrons in the floating gates of all the memory cells in the selected NAND cell block are released to the p-type well region (or p-type semiconductor substrate), and the threshold voltage is shifted to a negative direction.

On the other hand, in the data read operation, the control gate line of the selected memory cell is set to 0V, and the control gate line and selection gate line of the other memory cells are set to the middle voltage for reading. The voltage Vread (approximately 4V) is performed by detecting whether or not current flows in the selection memory.

From the above description of the operation, it can be seen that in the NAND cell type EEPROM, during the data writing operation, it is necessary to transmit Vpp (about 20V) to the selected control gate line in the selected block, and to transmit Vpp (about 20V) to the non-selected control gate line in the selected block. A voltage higher than the supply voltage Vmg (approximately 10V) is transmitted on the control gate line.

In order to transmit the above-mentioned voltages Vpp and Vmg, in the row decoder circuit, NMOS transistors (n-channel type MOS transistors) and PMOS transistors (p-channel type MOS transistor) controls the current path of both the NMOS transistor and the PMOS transistor in the selected block to be in the on state, and in the non-selected block, both of them are in the off state.

FIG. 1 is a circuit diagram showing a partial configuration example of a row decoder circuit in such a conventional semiconductor memory device.

In the circuit shown in FIG. 1 , [one NMOS transistor (Qn1 to Qn8 )+one PMOS transistor (Qp1 to Qp8 )] is connected to one control gate line. Complementary control signals are supplied from nodes N1 and N2 to these transistors Qn1 to Qn8 and Qp1 to Qp8, respectively.

At the time of data writing, the power supply node VPPRW and the selected control gate line voltage are at the same level as power supply node VPPRW=[selected control gate line voltage]=20V. In this case, since [1 NMOS transistor+1 PMOS transistor] is connected to each control gate line, 20V can be transmitted to the control gate line even when the power supply node VPPRW is at 20V. Accordingly, in the selected block, two voltages of 0V and Vpp can be transmitted without raising the power supply node VPPRW to (20V+Vth).

In the circuit shown in FIG. 1 , memory cells M ₁ -M ₈ are connected in series to form a current path, forming a NAND cell. One end of each of the above NAND cells is connected to the bit lines BL1-BLm through the current path of the selection gate transistor _S1 , and the other end is commonly connected to the source line (Cell-Source) through the current path of the selection gate transistor _S2 . ). The control gate lines CG(1)-CG(8) are respectively connected to the control gates of the memory cells _M1 - _M8 in each NAND unit, and the select gate lines SG(1) and SG(2) are respectively are commonly connected to the gates of select gate transistors S ₁ and S ₂ . Decoder signals are supplied to respective signal input nodes CGD1 to CGD8, SGD, SGS, and SGDS. In addition, the row decoder enable signal RDEC is at Vcc during normal data writing/reading/erasing operations, and is at 0 V during non-operations. All of the block address signals RA1, RA2, and RA3 are at Vcc in the selected block, and at least one of them is at 0V in the non-selected block.

Here, all the PMOS transistors provided in the region HV indicated by the dotted line are formed in the n-well region to which the write high voltage Vpp is applied, and one of the above-mentioned nodes N1 and N2 needs to be turned on during the write operation. Same potential as Vpp. In addition, the potential of node SGDS becomes 0V during the write operation.

However, in the above configuration, since two transistors Qp1 to Qp8 and Qn1 to Qn8 are required for each of the control gates CG ( 1 ) to CG ( 8 ), the number of elements in the row decoder circuit increases and there is a problem. There is a problem that the cost per chip increases due to an increase in the pattern occupation area of the row decoder circuit.

On the other hand, in order to prevent the increase of the number of components in the row decoder circuit, as shown in FIG. ) circuit. In the circuit shown in Figure 2, the memory cell block 2 has the same structure as that in Figure 1, and a part of the row decoder circuit (control gate lines CG(1)~CG(8), and the selection gate transistor S ₁ , S ₂ are different in circuit configuration of transistor parts) 5a, 5b for transmitting a voltage, and in that a pump circuit PUMP is provided.

In the case of this circuit configuration, in order to transmit the writing high voltage Vpp to the control gate lines CG( 1 ) to CG( 8 ), as a voltage supplied to the control gate lines CG( 1 ) to CG( 8 ), ) on the gates of the NMOS transistors QN1 to QN8 need to be [Vpp+Vtn] (Vth is the threshold voltage of the NMOS transistors QN1 to QN8 connected to the control gate lines CG(1) to CG(8)) . Therefore, a pump circuit PUMP is provided in the row decoder circuit.

The pump circuit PUMP is composed of capacitors C1 and C2, NMOS transistors QN21 to QN23, an inverter 6, a NAND gate 7, and depletion NMOS transistors QN24 and QN25.

In the circuit shown in FIG. 2, the signal OSCRD becomes an oscillating signal during the data writing/reading operation, and the voltage boosted in the pump circuit PUMP is output to the node N1, and the current path through the transistors QN1 to QN8 is directed to the control circuit. The gate lines CG( 1 )˜CG( 8 ) transmit voltages. Furthermore, the signal TRAN is usually fixed at 0V.

However, since the above-mentioned pump circuit PUMP includes a plurality of elements and capacitors C1 and C2, the circuit area increases. In particular, the pattern area required for the two capacitors C1 and C2 is generally larger than other components. Therefore, there is a problem that it is impossible to sufficiently reduce the pattern area of the row decoder circuit by reducing the number of transistors for voltage transmission.

In this way, conventional EEPROMs such as NAND cell type require a function of supplying a high voltage to a word line, and therefore require a plurality of transistors connected to the word line for each word line in the row decoder circuit. Therefore, there is a problem that the pattern area of the row decoder circuit increases.

In addition, in order to solve this problem, if the transistors connected to the word lines are provided as one per word line in the row decoder circuit, a pump circuit is required in the row decoder circuit, and since the pattern area of the pump circuit However, there is still the problem that the pattern area of the row decoder circuit increases.

Furthermore, when the row decoder circuit is provided with one transistor connected to the word line per word line, and no pump circuit is provided in the row decoder circuit, it cannot be achieved without a voltage drop. Transmission of high voltage for writing to the word line increases the risk that a sufficient data writing operation cannot be realized.

Contents of the invention

Therefore, it is an object of the present invention to provide a semiconductor memory device capable of transmitting a high voltage to a word line without voltage drop and reducing the pattern area of a row decoder circuit.

Another object of the present invention is to provide a monolithic semiconductor memory device capable of achieving high reliability at low cost.

Still another object of the present invention is to provide a semiconductor memory device capable of transmitting a high voltage to a word line without a voltage drop and realizing a sufficient data writing operation.

To this end, the present invention provides a semiconductor memory device comprising: a memory cell array in which memory cells are arranged in a matrix; and a row decoder circuit for transmitting a voltage to a word line while selecting a word line of the memory cell array, It is characterized in that: the row decoder circuit includes: a plurality of first transistors of the first conductivity type, one end of the current path of which is respectively directly connected to each word line; and a first transistor with opposite polarity to the first conductivity type The second transistor of the 2 conductivity type transmits a voltage to the gate of the first transistor connected to the selected word line when performing an operation of transmitting a voltage to the selected word line; The voltage transmission of the word line is performed only by the first transistor of the first conductivity type, the row decoder circuit further includes a first voltage switching circuit for applying a voltage to the gate of the first transistor, and the second transistor is set In the voltage switching circuit, when the voltage is transferred to the selected word line, a voltage higher than the voltage of the selected word line is input to the voltage switching circuit and transferred to the voltage switching circuit via the second transistor. The gate of the first transistor is connected to the selected word line.

In the semiconductor memory device of the present invention, the voltage applied to the gate of the second transistor in the non-selected block is higher than the power supply voltage.

In addition, the semiconductor memory device of the present invention further includes: a logic circuit receiving a block address signal and outputting a determination signal corresponding to a selection/non-selection determination result of a block; including the second transistor, receiving a determination signal output from the logic circuit signal, the first voltage switching circuit for respectively setting the gate voltage of the first transistor; A voltage switching circuit, wherein the voltage applied to the gate of the second transistor in the non-selected block is a voltage level of a determination signal output from the second voltage switching circuit.

If the above structure is adopted, since only the first transistor of the first conductivity type is used to transmit the voltage to the selected word line, the number of transistors connected to the word line in the row decoder circuit is one for each word line. The pattern area of the row decoder circuit is reduced. In addition, since a voltage is transmitted to the gate of the first transistor described above via a second transistor of the second conductivity type, for example, if an n-channel type is used as the first conductivity type, and a p-channel type is used as the second conductivity type transistor, it is possible to prevent a drop in the transfer voltage due to the threshold voltage of the second transistor, and it is possible to set the gate of the first transistor to a high voltage without providing a pump circuit. As a result, a high voltage can be transferred to the word line without lowering the potential.

In addition, since a row decoder circuit with a small pattern area can be realized, a highly reliable monolithic circuit can be realized at low cost.

Furthermore, a high voltage can be transmitted to the word line without lowering the potential, and a sufficient data writing operation can be realized.

Description of drawings

FIG. 1 is a circuit diagram showing a partial configuration example of a row decoder circuit and a memory cell array in a conventional semiconductor memory device.

2 is a circuit diagram showing another configuration example of a row decoder circuit and a part of a memory cell array in a conventional semiconductor memory device.

3 is a diagram for explaining a semiconductor memory device according to an embodiment of the present invention, and is a block diagram showing a schematic configuration of a NAND-type EEPROM.

FIG. 4A is a graphic plan view of a portion of a NAND cell in the memory cell array shown in FIG. 3. FIG.

FIG. 4B is an equivalent circuit diagram of a portion of a NAND cell in the memory cell array shown in FIG. 3 .

Fig. 5A is a cross-sectional view taken along line 5A-5A of Fig. 4A.

Fig. 5B is a cross-sectional view taken along line 5B-5B of Fig. 4A.

FIG. 6 is an equivalent circuit diagram of a memory cell array in which the above-mentioned NAND cells are arranged in a matrix.

7 is a circuit diagram showing a partial configuration example of a row decoder circuit and a memory cell array in the semiconductor memory device according to Embodiment 1 of the present invention.

8 is a timing chart showing a data writing operation in the semiconductor memory device according to Embodiment 1 of the present invention.

9 is a timing chart showing a data read operation in the semiconductor memory device according to Embodiment 1 of the present invention.

10 is a timing chart showing a data erasing operation in the semiconductor memory device according to Embodiment 1 of the present invention.

11 is a circuit diagram showing a partial configuration example of a row decoder circuit and a memory cell array in the semiconductor memory device according to Embodiment 1 of the present invention.

12A and 12B are diagrams for explaining the shape of the n-well region in the row decoder circuit in the semiconductor memory device according to Embodiment 1 and Embodiment 2, respectively.

13 is a circuit diagram showing a partial configuration example of a row decoder circuit and a memory cell array in a semiconductor memory device according to Embodiment 3 of the present invention.

14 is a circuit diagram showing a partial configuration example of a row decoder circuit and a memory cell array in a semiconductor memory device according to Embodiment 4 of the present invention.

15 is a diagram showing a first block configuration example of a memory cell array and a row decoder circuit in a semiconductor memory device according to an embodiment of the present invention.

16 is a diagram showing a second block configuration example of a memory cell array and a row decoder circuit in the semiconductor memory device according to the embodiment of the present invention.

17 is a diagram showing a third block configuration example of a memory cell array and a row decoder circuit in a semiconductor memory device according to an embodiment of the present invention.

18 is a diagram showing a block configuration of a memory cell array and a row decoder circuit in a semiconductor memory device according to an embodiment of the present invention, and a first example of the shape of an n-well region.

19 is a diagram showing a block configuration of a memory cell array and a row decoder circuit in a semiconductor memory device according to an embodiment of the present invention, and a second example of the shape of an n-well region.

20 is a diagram showing a block configuration of a memory cell array and a row decoder circuit in a semiconductor memory device according to an embodiment of the present invention, and a third example of the shape of an n-well region.

21A to 21E are diagrams for respectively explaining the block configuration of the row decoder circuit in the semiconductor memory device according to Embodiment 1 to Embodiment 4 of the present invention, and semiconductor memory devices according to other embodiments, and the n-well A diagram of the shape of the region.

22 is a diagram showing a block address decoder in a row decoder circuit and a voltage switching circuit in a semiconductor memory device according to Embodiment 1 to Embodiment 4 of the present invention, and semiconductor memory devices according to other embodiments. 1 constitutes the circuit diagram.

23 is a diagram showing a block address decoder and a voltage switching circuit in a row decoder circuit in a semiconductor memory device according to Embodiment 1 to Embodiment 4 of the present invention, and semiconductor memory devices according to other embodiments. 2 constitute the circuit diagram.

24 is a diagram showing a block address decoder and a voltage switching circuit in a row decoder circuit in a semiconductor memory device according to Embodiment 1 to Embodiment 4 of the present invention, and semiconductor memory devices according to other embodiments. 3 constitute the circuit diagram.

25 is a diagram showing a block address decoder in a row decoder circuit and a voltage switching circuit in a semiconductor memory device according to Embodiment 1 to Embodiment 4 of the present invention, and semiconductor memory devices according to other embodiments. 4 constitute the circuit diagram.

26 is a diagram for explaining a block configuration of a row decoder circuit of a semiconductor memory device according to other embodiments, and a shape of an n-well region.

27 is a diagram for explaining a block configuration of a row decoder circuit of a semiconductor memory device according to other embodiments, and a shape of an n-well region.

28 is a diagram for explaining a block configuration of a row decoder circuit of a semiconductor memory device according to other embodiments, and a shape of an n-well region.

29A and 29B are diagrams for further explaining the block configuration of the row decoder circuit in the semiconductor memory device according to other various embodiments, and the shape of the n-well region, respectively.

30 is a diagram showing another configuration example of a row decoder circuit in a semiconductor memory device according to Embodiment 5 of the present invention.

31A to 31D are circuit diagrams each showing a specific configuration example of a voltage switching circuit in the circuit shown in FIG. 30 .

32 is a circuit diagram showing another configuration example of the row decoder circuit of the semiconductor memory device according to Embodiment 6 of the present invention.

33A to 33D are circuit diagrams each showing a specific configuration example of a voltage switching circuit in the circuit shown in FIG. 32 .

34 is a diagram for explaining a semiconductor memory device according to another embodiment of the present invention, and is a circuit diagram extracting and showing a portion of a circuit that supplies a high voltage to a voltage switching circuit in each of the above embodiments.

35 is a diagram for explaining a semiconductor memory device according to still another embodiment of the present invention, and is a circuit diagram extracting and showing a portion of a circuit that supplies a high voltage to a voltage switching circuit in each of the above embodiments.

FIG. 36 is an equivalent circuit diagram showing a memory cell array in a NOR cell type EEPROM.

FIG. 37 is an equivalent circuit diagram showing a memory cell array in a DINOR cell type EEPROM.

FIG. 38 is an equivalent circuit diagram showing a memory cell array in an AND cell type EEPROM.

FIG. 39 is an equivalent circuit diagram showing a memory cell array in a NOR cell type EEPROM with selection transistors.

Detailed ways

3 is a diagram for explaining a semiconductor memory device according to an embodiment of the present invention, and is a block diagram showing a schematic configuration of a NAND-type EEPROM. To the memory cell array 101, a bit line control circuit (sense amplifier and data latch) 102 for performing data writing, reading, rewriting, and verify reading is connected. The bit line control circuit 102 is connected to a data input/output buffer 106 and receives an output of a column decoder 103 that receives an address signal from an address buffer 104 as an input.

In addition, on the above-mentioned memory cell array 101, a row decoder 105 for controlling the control gate and the select gate, and a p-type silicon substrate (or p-type well) for controlling the formation of the memory cell array 101 are connected. region) potential of the substrate potential control circuit 107. In addition, in order to generate high voltage Vpp (approximately 20 V) and intermediate voltage Vmg (approximately 10 V) for write, high voltage generator circuit 109 for write and intermediate voltage generator circuit 110 for write are provided. Furthermore, a read intermediate voltage generation circuit 111 is provided to generate a read intermediate voltage Vread at the time of data read. In addition, a high voltage generating circuit 112 for erasing is provided in order to generate a high voltage Vpp for erasing (approximately 20 V) during an erasing operation.

The bit line control circuit 102 is mainly composed of a CMOS flip-flop circuit, and performs data latching for writing, readout for reading the potential of the bit line, and readout for verify readout after writing. action, and then perform rewrite data latching.

4A and 4B are respectively a graphic plan view and an equivalent circuit diagram of a NAND cell part in the above-mentioned memory cell array 101, and FIGS. 5A and 5B are respectively along the 5A-5A line of FIG. 4A and the section of the 5B-5B line picture. On a p-type silicon substrate (or p-type well region) 11 surrounded by an element isolation oxide film 12, a memory cell array composed of a plurality of NAND cells is formed. If it is described as one NAND cell, in this embodiment, eight memory cells M ₁ to M ₈ are connected in series to form one NAND cell.

The memory cells M ₁ to M ₈ have floating gates 14 (14 ₁ , 14 ₂ , . . . , 14 ₈ ) formed on the substrate 11 via the gate insulating film 13, The insulating film 15 forms a control gate 16 (=word line: 16 ₁ , 16 ₂ , . . . , 16 ₈ ). N-type diffusion layers 19 (19 ₀ , 19 ₁ , . . . , 19 ₁₀ ) serving as sources and drains of these memory cells are connected in common between adjacent ones, whereby the memory cells are connected in series.

Select gates 14 ₉ , 16 9 , and 14 ₁₀ , _{16 10 formed} simultaneously with the floating gates and control gates of the memory cells are provided on the drain side and the source side of the NAND cells, respectively. The element-formed substrate 11 is covered with a CVD oxide film 17, and a bit line 18 is arranged thereon. The bit line 18 is contacted on the drain side diffusion layer 19 at one end of the NAND cell. The control gates 16 of the NAND cells arranged in the row direction are commonly arranged as control gate lines CG( 1 ), CG( 2 ), . . . , CG( 8 ). These control gates become word lines. The selection gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ are also continuously arranged in the row direction as selection gate lines SG( 1 ), SG( 2 ).

FIG. 6 is an equivalent circuit showing a memory cell array in which such NAND cells are arranged in a matrix. A group of NAND cells sharing the same word line and select gate line is called a block, and an area surrounded by a dotted line in FIG. 6 is defined as one block. During a normal read/write operation, only one of a plurality of blocks is selected (referred to as a selected block).

FIG. 7 shows a partial configuration example of a row decoder circuit and a memory cell array in the semiconductor memory device according to Embodiment 1 of the present invention. FIG. 7 shows a configuration in which elements in one circuit are arranged on both sides of a memory cell block 2 . The circuit shown in FIG. 7 is characterized in that the transistors QN0 to QN10 connected to the control gate lines CG (1) to CG (8) and the selection gate lines SG (1) to SG (2) are n-channel only. type; the transistors QN1-QN8 connected to the control gate lines CG(1)-CG(8) are one for each control gate line; they are connected to the control gate lines CG(1)-CG (8) PMOS transistors QP11 and QP12 are provided between output node N1 and power supply node VPPRW of voltage switching circuit 54A for selecting gate voltages of transistors QN0 to QN10 on gate lines SG(1) and SG(2).

That is, current paths of NMOS transistors QN1 to QN8 are connected between control gate lines CG( 1 ) to CG( 8 ) and signal input nodes CGD1 to CGD8 , respectively. In addition, current paths of NMOS transistors QN0 and QN9 are connected between select gate line SG(1) and signal input nodes SGD and SGDS, respectively. Furthermore, a current path of the NMOS transistor QN10 is connected between the selection gate line SG(2) and the signal input node SGS.

The aforementioned voltage switching circuit 54A is configured to include PMOS transistors QP11 , QP12 , NMOS transistors QN11 , QN12 , and an inverter 55 . The PMOS transistors QP11, QP12, and NMOS transistors QN11, QN12 are connected to function as a trigger circuit 56, and one end and the back gate of the current paths of the PMOS transistors QP11, QP12 are respectively connected to the power supply node VPPRW at one end. . The current paths of the NMOS transistors QN11 and QN12 are connected between the other end of the current paths of the PMOS transistors QP11 and QP12 and the other power supply node, for example, a ground point. The gate of the PMOS transistor QP11 is connected to the other end of the current path of the PMOS transistor QP12 and the node N1, and the gate of the PMOS transistor QP12 is connected to the other end of the current path of the PMOS transistor QP11. Then, the output terminal of the inverter 55 is connected to the gate of the NMOS transistor QN12, and the input terminal is connected to the gate of the NMOS transistor QN11.

The signal RDEC is supplied to the first input terminal of the NAND gate 57, and the signals RA1, RA2 and RA3 are respectively supplied to the second to fourth input terminals. The input of an inverter 58 and the node N2 are connected to the output of the NAND gate 57 . Then, the input terminal of the inverter 55 and the gate of the NMOS transistor QN11 are connected to the output terminal (node N0 ) of the inverter 58 .

Furthermore, signal RDEC in FIG. 7 is a row decoder activation signal, which is at Vcc during normal data writing, reading, and erasing operations, and is at 0V during non-operations. In addition, the signals RA1, RA2, and RA3 are block address signals, all of which are at Vcc in the selected block, and at least one of them is at 0V in the non-selected block. Therefore, only the node N0 of the active selected block is at Vcc, and the normal node N0 is at 0V in the non-operating or non-selected block.

Timing charts showing the operations of data writing, data reading, and data erasing in the case of using the circuit of FIG. 7 are shown in FIGS. 8 to 10, respectively. Each operation timing will be briefly described below. Furthermore, in the data writing and reading operations in FIGS. 8 and 9 and thereafter, among the eight control gate lines CG(1) to CG(8) in the selected block, the selected control gate line CG(2 ) will be described as an example, but the same applies to the case of selecting other control gate lines.

In the data write operation shown in FIG. 8, when the operation starts, the row decoder circuit of the selected block is first selected, the nodes N0 and N1 are at Vcc, and the node N2 is at 0V. Also, while the bit line whose write data is "0" data is charged from 0V to Vcc, SG(1) in the selected block becomes [Vcc-Vtsg]. Next, since the power supply node VPPRW changes from Vcc to (20V+Vtn) (Vtn is the threshold voltage of the NMOS transistors QN1 to QN8 directly connected to the control gate lines CG(1) to CG(8), the voltage switching circuit 54A The output node N1 of VCC also changes from Vcc to (20V+Vtn).

Then, if the signal input node CGD2 changes from 0V to 20V, the signal input nodes CGD1, CGD3～CGD8 change from 0V to 10V, because the gate voltage of the NMOS transistor connected to the control gate line is at (20V+ Vtn), so the voltage is transmitted from the signal input node CGDi to the control gate line CG(i) without voltage drop, the control gate line CG(2) changes from 0V to 20V, and the control gate line CG(1) , CG(3)~CG(8) change from 0V to 10V. At this time, the channel part voltage Vchannel of the NAND cell in the selected block connected to the "1" writing bit line is fixed at 0V, and the channel voltage Vchannel of the NAND cell in the selected block connected to the "0" writing bit line The channel part voltage Vchannel rises to 8V due to the capacitive coupling with the control gate line. Since this state is held for a while, electrons are injected into the floating gate of the memory cell whose write data is "1", and data writing is performed. Next, after the control gate lines CG(1) to CG(8) in the selected block are all turned to 0V, while the "0" data write bit line and the selected gate line SG(1) are turned to 0V, The power supply node VPPRW becomes Vcc. Finally, at the same time as the source line (Cell-Source) becomes 0V, the nodes N0, N1, and N2 become 0V, 0V, and Vcc, respectively, and the data writing operation ends.

In the data read operation shown in FIG. 9, when the operation starts, the row decoder circuit of the selected block is first selected, the nodes N0 and N1 are at Vcc, and the node N2 is at 0V. In addition, the bit line from which data is read is precharged to Vcc. Next, when the power supply node VPPRW and the node N1 become (4V+Vtn), if the signal input nodes CGD1, CGD3~CGD8 and the signal input nodes SGD, SGS change from 0V to 4V, and the signal input node CGD2 is fixed at 0V, then Since a threshold voltage higher than 4V is applied to the gate of the NMOS transistor connected to the control gate line and the selection gate line, it is possible to supply the control gate line and the selection gate line without lowering the potential. transmit voltage. Therefore, at this time, the non-selected control gate lines CG(1), CG(3) to CG(8) and the selection gate lines SG(1) and SG(2) in the selected block are changed from 0V to 4V, The selected control gate line is fixed at 0V. Since this state is maintained for a while, the data of the selected memory cell is read. Next, when the control gate lines CG(1) to CG(8) and the selection gate lines SG(1) and SG(2) in the selected block all become 0V, the power supply node VPPRW changes from (4V +Vtn) becomes Vcc, the bit line becomes 0V, and the nodes N0, N1, and N2 become 0V, 0V, and Vcc, respectively, so that the data read operation ends.

In the data erasing operation shown in FIG. 10, when the operation starts, the row decoder circuit of the selected block is first selected, the nodes N0 and N1 are at Vcc, and the node N2 is at 0V. In addition, since the signal input nodes SGD, SGS, and SGDS are all Vcc, the selection gate line SG(1) of both the selected block and the non-selected block and the selection gate line SG(2) of the selected block are all charged. After reaching (Vcc-Vtn), it becomes a floating state. In addition, at this time, all the control gate lines and the selection gate line SG( 2 ) in the non-selected block are in a floating state at a voltage of 0V. Next, when the p-type well region (Cell-pwell) constituting the memory cell array changes from 0V to 20V, the selection gate lines SG(1) and SG(2) of both the selected block and the non-selected block in the floating state ) and the control gate lines in the non-selection blocks are all affected by the capacitive coupling with the p-type well region to rise to 20V, and only the control gate lines in the selection block are fixed at 0V. Since this state is maintained for a while, electrons are released from the floating gates of the memory cells in the selected block to the p-type well region, and data erasing is performed. Next, since the p-type well region becomes 0V, the selection gate lines SG(1) and SG(2) in both the selected block and the non-selected block in the floating state and the control gate lines in the non-selected block It falls to 0V to Vcc due to the influence of the capacitive coupling of the p-type well region, and then is fixed to 0V. Finally, the nodes N0, N1, and N2 become 0V, 0V, and Vcc, respectively, and the data erasing operation ends.

As described above, in the row decoder circuit shown in FIG. 7, during the data writing operation and the data reading operation, by applying a ratio to the control gate line and the selection gate line on the power supply node VPPRW, The highest voltage is higher than the voltage of Vtn (threshold voltage of the transistors QN0 to QN10 that transmit the voltage), even if the transistors connected to one control gate line and selection gate line are only NMOS transistors, the potential does not drop In this case, a high voltage for writing and a high voltage for reading are applied to the control gate line, and a highly reliable operation can be realized.

In addition, by setting the transistors connected to one control gate line as one NMOS transistor, a row decoder circuit with a small number of components can be realized, and the reduction in the pattern area of the row decoder circuit can be achieved. The size of the single chip is reduced, that is, the cost of the single chip is reduced.

Furthermore, since it is possible to use the voltage switching circuit 54A that outputs a "high" potential via the PMOS transistors QP11 and QP12 of opposite polarity to the transistors connected to the control gate line and the selection gate line, the number of constituent elements is small and The voltage switching circuit 54 with a small pattern occupation area can realize a row decoder circuit with a small number of elements and a small pattern occupation area, and can realize the single-chip size reduction by reducing the pattern area of the row decoder circuit, that is, realize the single-chip cost. reduce.

FIG. 11 shows another partial configuration example of the row decoder circuit of the semiconductor memory device according to Embodiment 2 of the present invention. The difference between the circuit of FIG. 11 and that of FIG. 7 is the circuit configuration of the voltage switching circuit 54B, and a depletion NMOS transistor QD1 is provided between the power supply node VPPRW and the transistors QP11 and QP12. Timing charts showing respective operations of data writing, reading, and erasing when the circuit of FIG. 11 is used are the same as those in FIGS. 8 to 10 .

Hereinafter, the advantages of providing the above-mentioned transistor QD1 will be described.

In the circuit of FIG. 7, since the potential of the power supply node VPPRW is directly applied to the sources of the PMOS transistors QP11 and QP12 and the n-well regions constituting QP11 and QP12, it is necessary to set all The source n-well regions of the transistors QP11, QP12 in the block are charged to the potential of the power supply node VPPRW. Usually, since there are hundreds to thousands of blocks in a single chip, the source and n-well regions of hundreds to thousands of elements are charged at the same time, and the capacitance value of the power supply node VPPRW becomes very large. . In the data write operation and read operation, since boosted voltages such as (20V+Vtn) and (4V+Vtn) are applied to the power supply node VPPRW, if the capacitance value of the power supply node VPPRW is large, a boost will occur. The area of the voltage generating circuit is increased, the power consumption is increased, and the operation time is prolonged due to the time required for charging the boosted voltage.

On the other hand, in the circuit of FIG. 11, in the selection block, since the voltage of the node N0 is "high" level (=Vcc), the voltage of the node N1 input to the gate of the transistor QD1 is "high". level (=VPPRW potential), because the potential of node N3, which is the source/n-well potential of transistors QP11 and QP12, also becomes "high" potential (=VPPRW potential), so it can be determined regardless of the presence or absence of transistor QD1. Realize the actions in Fig. 8 to Fig. 10 . In the non-selected block when the circuit of FIG. 11 is used, since the voltage of the node N0 is at 0V of "low" potential, the voltage of the node N1 input to the gate of QD1 is fixed at 0V, and thus the node N3 is at Vtd (Vtd is the highest value of the voltage that can be transmitted via the transistor QD1 when the gate voltage of the transistor QD1=0V, and is usually a voltage below Vcc).

Thus, by using the circuit shown in FIG. 11, the source/n well potentials of the transistors QP11 and QP12 can be changed between the selected block and the non-selected block.

The shape of the n-well region constituting the above-mentioned transistors QP11, QP12 is shown in FIGS. 12A and 12B. 12A and 12B show examples of formation of the n-well region when the circuit configurations of FIGS. 7 and 11 are used, respectively. In the circuit shown in FIG. 7 , since the n-well voltages are at the same potential in all blocks, as shown in FIG. 12A , one n-well region NW across all blocks Block1 to BlockN is formed, and a PMOS is usually formed in this region NW. The way of transistor QP11, QP12.

On the other hand, in the circuit of FIG. 11, since the n-well voltage is different between the selected block and the non-selected block, as shown in FIG. 12B, one n-well is formed in each of the blocks Block1 to BlockN. In the regions NW1 to NWN, it is effective to form the PMOS transistors QP11 and QP12 in these regions NW1 to NWN. By dividing each block into an n-well area and charging only the selected n-well area with a boosted voltage (20V, 4V, etc.) higher than the power supply voltage, the load capacitance value of the boosted voltage can be greatly reduced. Therefore, it is possible to reduce the area of the boosted voltage generating circuit, reduce the power consumption, and speed up the operation by shortening the time required for charging the boosted voltage.

FIG. 13 shows still another partial configuration example of a row decoder circuit in a semiconductor memory device according to Embodiment 3 of the present invention. The difference between the circuit of FIG. 13 and the circuits of FIGS. 7 and 11 is the configuration of the voltage switching circuit 54C. The configuration of this voltage switching circuit 54C includes a depletion NMOS transistor QD2, a PMOS transistor QP13, and depletion NMOS transistors QD3 and QD4. One end of the current path of the NMOS transistor QD2 is connected to the power supply node VPPRW, and its gate is connected to the node N1. One end of the current path of the PMOS transistor QP13 and the back gate are connected to the other end of the current path of the NMOS transistor QD2, the other end of the current path is connected to the node N1, and the gate is connected to the "NAND" gate 57 output. One end of the current path of the NMOS transistor QD3 is connected to the node N1, and the power supply voltage Vcc is applied to the gate. Then, one end of the current path of the NMOS transistor QD4 is connected to the other end of the current path of the NMOS transistor QD3, and the other end of the current path is connected to the output terminal of the inverter 58 to supply the signal TRAN to the gate.

The circuit operation waveform in FIG. 13 is the same as the waveforms in FIGS. 8 to 10 , and the voltage at node N1 in FIG. 13 becomes the same as that at node N3 in FIG. 11 . Therefore even when using the circuit of FIG. 13, also when using the circuit of FIG. 11, the voltage of the node N4 is different between the selected block and the non-selected block, that is, the "high" level (=boosted voltage) is transmitted to the node N1. ) of the PMOS transistor QP13 and the voltages of the source and n-well regions differ between selected and non-selected blocks. Therefore, an n-well configuration as shown in FIG. 12B can be used, and as a result, the load capacity of the boosted voltage can be reduced. In addition, the signal TRAN is normally used with a fixed value of 0V. In the non-selected block, since the node N0 is 0V, 0V is transmitted to the node N1 via the depletion NMOS transistors QD4 and QD3. Furthermore, in the selected block, since node N=Vcc and node N1≧Vcc, NMOS transistor QD4 is turned off, and the "high" potential of node N1 is maintained.

As other advantages of the above-mentioned circuit of FIG. 13, the first is that the number of components constituting the voltage switching circuit 54C is smaller than that of the circuit of FIG. The potential difference between the source, drain, and n-well regions is reduced. Regarding the latter, when the transistor QP13 is turned on, usually the source=drain=n well region, and when it is turned off, the source=n well region=Vtd (Vtd can be obtained when the gate voltage of QD2=0V The highest value of the voltage transmitted through the transistor QD2 is usually a voltage below Vcc) and the drain = 0V, regardless of whether there is an action of applying a high voltage (about 20V) for writing, between the source, drain, and n-well regions Even if the potential difference is the highest, it is only Vcc.

Furthermore, in the above-mentioned embodiment, as shown in FIGS. 7, 11 and 13, it is assumed that row decoder circuits for driving control gate lines and selection gate lines in one block are arranged on both sides of the memory cell array as an example. The present invention has been described, but in other cases, the present invention is also effective even when a row decoder circuit corresponding to one block is arranged on one side of the memory cell array as shown in FIG. 14, for example. In FIG. 14 , a specific circuit configuration is not shown as the voltage switching circuit 54D, but various circuit configurations may be used, such as the circuits in FIGS. 7 , 11 and 13 .

Next, configuration examples of the row decoder circuit are shown in FIGS. 15 to 17 . FIG. 15 shows a case in which row decoder circuits for driving control gate lines and selection gate lines in one block are arranged on both sides of a memory cell array, and corresponds to the embodiments in FIGS. 11 and 13 . 16 and 17 show the case where row decoder circuits corresponding to one block are arranged on one side of the memory cell array, and correspond to FIG. 14 . As the width (pitch) of the pattern of row decoders made into one block, it is the length of one NAND cell (the length in the bit line direction of one NAND cell) in the case of using the method shown in FIG. 15 . In the case of 16 and 17 methods, the pitch can be secured because the length becomes 2 NAND cells.

FIGS. 18 to 20 show the case where the n-well region for forming the PMOS transistor is added to the above-mentioned FIGS. 15 to 17 . 15 to 17 correspond to FIGS. 18 to 20, respectively. It can also be seen from FIGS. 18 to 20 that in the case of using the method of FIG. 14, compared with the case of using FIGS. 11 and 13, the pitch for pattern formation of the row decoder circuit is doubled. In this case, the pitch of the n-well region for forming the PMOS transistor is also doubled. Therefore, design rules can be relaxed, and a single chip with higher reliability and high yield can be realized. In addition, even if the design rules are reduced in the future, the method shown in FIG. 14 has the advantage that n-well regions can be divided and formed in each block compared to the cases using the methods shown in FIGS. 11 and 13. The advantage of high probability (or high probability).

However, the arrangement of the above-mentioned n-well region can also be considered other than the above-mentioned arrangement, for example, it can be arranged as shown in FIGS. 21A to 21E. 21A to 21E are diagrams showing the area of the row decoder, depicting only adjacent blocks in the pattern forming area of the row decoder.

FIG. 21A is a diagram showing the modes of FIGS. 18, 19, and 20 (=a mode in which the mode of FIG. 21A is applied to the block configurations of FIGS. N-well regions NWi, NWj are formed in the respective regions.

21B, 21C, and 21D are for the case where the n-well regions NWi, NWj are formed across a plurality of blocks Block-i, Block-j with respect to the row decoder regions corresponding to each block. In the n-well region Nwi The design rules around NWj are such that, assuming a pitch of one block for forming row decoders, it is effective to form one n-well region in a region of two blocks as shown in FIGS. 21B, 21C, and 21D.

When the design rules are more stringent in the future, as shown in Figure 21E, it is enough to form one n-well region NWi-NW1 in the region of 4 Block-i and Block-1, and then it can be applied to 3 and 5 Various methods such as forming one n-well region in the region of the above block.

In this way, applying the method of FIGS. 21B to 21E to the block configurations of FIGS. 15 to 17 is very effective when the design rule is reduced. In particular, as shown in the above-mentioned PMOS transistors QP11, QP12, QP13, etc., it is difficult to reduce the design rule of the n-well region to which a voltage higher than the power supply voltage (boost voltage, etc.) It is an extremely effective method.

In addition, in FIGS. 11, 12A, 12B, 13 and 14, FIGS. 18 to 20 and FIGS. 21A to 21E, implementation in the case where one n-well region for forming a PMOS transistor is provided for one row decoder circuit is described. plan. However, the present invention is also effective in other cases, for example, when one n-well region is shared between adjacent blocks.

In FIGS. 22 to 25, in the case of the above-mentioned circuit, and in the row decoder circuit of two adjacent blocks in the case of sharing one n-well region between adjacent blocks, the address decoder section · voltage An example of the circuit configuration of the switching circuit section 54 ( 54A, 54B, 54C, 54D). FIG. 22 corresponds to the circuit of FIG. 11 , and FIG. 23 corresponds to the circuit of FIG. 13 . FIG. 24 is an example of a circuit configuration when one n-well region is shared between adjacent blocks, and corresponds to an example based on the circuit of FIG. 11 . FIG. 25 is an example of a circuit configuration when one n-well region is shared between adjacent blocks, and corresponds to an example based on the circuit of FIG. 13 . Figure 24 does not increase the number of elements in Figure 22, while Figure 25 adds one depletion-type NMOS transistor per block relative to Figure 23.

When using the circuits shown in Figures 24 and 25, in the case of selecting one of the two blocks sharing the n-well region, or selecting both, the n-well region becomes the voltage at the time of selection (20V+ at the time of writing) Vtn, 4V+Vtn when reading, Vcc when erasing), and the n-well region is set to the non-selection voltage Vtd in other cases. Also in this case, since the n-well region to which the boosted voltage is applied includes only the selection block, there is an advantage that the load capacity of the boosted voltage can be significantly reduced compared to the conventional case (corresponding to FIG. 12A ).

Furthermore, in FIGS. 22 to 25, as an adjacent block, the present invention has been described as an example in the case where the continuous address blocks of Block-i and Block-(i+1) are adjacent in the row decoder circuit, However, it is needless to say that the present invention is also effective when the n-well region is shared between adjacent blocks in the row decoder circuit region even if it is not a block of consecutive addresses.

26 to 28 show examples of formation of n-well regions when the circuit configurations shown in FIGS. 24 and 25 are used, and one n-well region is shared between adjacent blocks. By using Figures 24, 25 and Figures 26 to 28, compared with the case of using Figures 22, 23 and Figures 18 to 20, the pitch of the n-well region can also be enlarged. Therefore, because of the design rules around the n-well region is relaxed, it is possible to achieve improvement in reliability, improvement in yield, and the like. In particular, it is difficult to reduce the design rules of the n-well region to which a voltage higher than the power supply voltage (boosted voltage, etc.) is applied like the above-mentioned PMOS transistors QP11, QP12, QP13, etc. effective method.

Furthermore, if the method of FIGS. 24, 25 and 26 to 28 is used, since the number of n-well regions is halved, there is an advantage that the pattern area of the row decoder circuit can be reduced. Furthermore, as a method of easing the design rules, as shown in FIGS. 29A and 29B, there is a method of providing an n-well region shared by two blocks at a pitch of 3 to 4 blocks. The method of consideration is the same as that of FIGS. 21D in the same way. The method of Figures 29A and 29B is also very effective.

FIG. 30 shows another partial configuration example of the row decoder circuit in the semiconductor memory device according to Embodiment 5 of the present invention. The circuit shown in FIG. 30 has a configuration in which a voltage switching circuit 54E is added to the circuit shown in FIG. 14 . That is, the row decoder activation signal RDEC is supplied to the first input terminal of the NAND gate 57, and the block address signals RA1, RA2, and RA3 are supplied to the second to fourth input terminals, respectively. An input terminal of an inverter 58 is connected to an output terminal of this NAND gate 57, and an output signal in1 of this inverter 58 is supplied to voltage switching circuits 54D and 54E. The voltage Vm is applied as an operating power supply voltage to the voltage switching circuit 54E. Then, the output signal out1 of the voltage switching circuit 54E is supplied to the voltage switching circuit 54D. Since other circuit parts are the same as the circuit shown in FIG. 14, the same symbols are assigned to the same parts, and detailed description thereof will be omitted.

31A to 31D are circuit diagrams each showing a specific configuration example of the voltage switching circuit 54E in the circuit shown in FIG. 30 described above. The output signal in1 of the inverter 58 is input to any voltage switching circuit 54E, 0V is output when the signal in1 is "high" level, and a Vm level signal out1 is output when the signal in1 is "low" level.

The circuit shown in FIG. 31A is composed of an inverter INVa, NMOS transistors QN13, QN14, and PMOS transistors QP14, QP15. The output signal in1 of the inverter 58 is supplied to the input terminal of the inverter INVa and the gate of the NMOS transistor QN14, respectively. The gate of the NMOS transistor QN13 is connected to the output terminal of the inverter INVa. The sources of the NMOS transistors QN13 and QN14 are connected to another power supply node, such as a ground point, and the drains and sources of the PMOS transistors QP14 and QP15 are respectively connected between the respective drains and the voltage node Vm. The gate of the PMOS transistor QP14 is connected to the drain-common contact of the PMOS transistor QP15 and the NMOS transistor QN14, and the drain of the PMOS transistor QP15 is connected to the drain-common contact of the PMOS transistor QP14 and the NMOS transistor QN13. Then, the output signal Out1 obtained from the drain common contact of the transistors QP15, QP14 is supplied to the input terminal of the power switching circuit 54D.

In addition, the circuit shown in FIG. 31B is composed of an inverter INVb, NMOS transistors QN15, QN16, PMOS transistors QP16, QP17, and a depletion NMOS transistor QD5. The output signal in1 of the inverter 58 is supplied to the input terminal of the inverter INVb and the gate of the NMOS transistor QN16, respectively. The gate of the NMOS transistor QN15 is connected to the output terminal of the inverter INVb. The sources of the NMOS transistors QN15 and QN16 are commonly connected to the ground point, and the drains of the NMOS transistors QP16 and QP17 are respectively connected to the drains. The gate of the PMOS transistor QP16 is connected to the drain common contact of the PMOS transistor QP17 and the NMOS transistor QN16, and the drain of the PMOS transistor QP17 is connected to the drain common contact of the PMOS transistor QP16 and the NMOS transistor QN15. Between the sources of the PMOS transistors QP16, QP17 and the voltage node Vm, the drain and the source of the depletion NMOS transistor QD5 are connected, and the gate thereof is connected to the drain-common contact of the transistors QP17, QN16. Then, the output signal out1 obtained from the drain common contact of the transistors QP17, QN16 is supplied to the input terminal of the power switching circuit 54D.

The circuit shown in FIG. 31C is composed of an NMOS transistor QN17, a PMOS transistor QP18, and a depletion NMOS transistor QD6. The current paths of the transistors QN17, QN18, QN6 are connected in series between the ground point and the voltage contact Vm, and the output signal in1 of the inverter 58 is supplied to the gates of the transistors QN17, QP18. In addition, the gate of the transistor QD6 is connected to the drain common contact of the transistors QN17 and QP18. Then, the output signal out1 obtained from the drain common contact of the transistors QN17 and QP18 is supplied to the input terminal of the voltage switching circuit 54D.

Furthermore, the circuit shown in FIG. 31D is composed of an inverter INVd, an NMOS transistor QN18, a PMOS transistor QP19, and a depletion NMOS transistor QD7. The output signal in1 of the inverter 58 is supplied to the input terminal of the inverter INVd and the gate of the PMOS transistor QP19. One end of the current path of the NMOS transistor QN18 is connected to the output terminal of the inverter INVd, and the power supply voltage Vcc is applied to the gate of the transistor QN18. Between the other end of the current path of the transistor QN18 and the voltage node Vm, the current paths of the PMOS transistor QP19 and the depletion NMOS transistor QD7 are connected in series. The gate of the transistor QD7 is connected to the junction of the current paths of the transistors QN18 and QP19. Then, the output signal out1 obtained from the junction of the current path of the above-mentioned transistors QN18, QP19 is supplied to the input terminal of the voltage switching circuit 54D.

Furthermore, as the circuit configuration of the above voltage switching circuit 54D, the voltage switching circuit 54A in the circuit shown in FIG. 7, the voltage switching circuit 54B in the circuit shown in FIG. 11, and the voltage switching circuit 54C in the circuit shown in FIG. , or any circuit shown in Figure 22 to Figure 25 is also applicable.

The voltage of the voltage contact Vm in the above-mentioned circuit shown in FIG. 30 can be, for example, higher than the power supply voltage (or the power supply voltage of the "NAND" gate 57 and the inverter 58), and higher than the highest voltage of the power supply node VPPRW (usually It is a voltage lower than the level of the writing high voltage Vpp). In the case of using the method shown in FIG. 30 , the voltage at the "high" state of one of the two signals input to the voltage switching circuit 54D (the signal corresponding to out1 in FIG. 30 ) increases from the power supply voltage to the voltage Vm. . That is, in the row decoder circuit corresponding to the non-selected block, because the output of the "NAND" gate 57 becomes "high", the signal in1 output from the inverter 58 becomes "low", and the signal out1 becomes Vm level. As a result, a Vm level signal is input to the voltage switching circuit 54D.

The premise that it is particularly effective when the circuit system shown in FIG. 30 is used is that the voltage switching circuit 54C in the circuit shown in FIG. 13 is used as the voltage switching circuit 54D, or the circuit configuration shown in FIGS. 23 and 25 .

Hereinafter, the effects of the case where the voltage switching circuit 54C among the circuits shown in FIG. 13 is used as the voltage switching circuit 54D will be described as an example. When using the circuit configuration as shown in FIG. 30, in the row decoder corresponding to the non-selected block, since the voltage input to the gate of the transistor QP13 rises from the power supply voltage to the Vm level, it is possible to reduce the voltage passing through the transistor QP13. The advantage of the leakage current. In general, since several hundred to tens of thousands of row decoder circuits are installed in a single chip, even if the leakage current in one row decoder circuit is not too large, it becomes large in all the chips. current. Therefore, the leakage current reduction method using the circuit shown in FIG. 30 can obtain a remarkable effect. This effect can be similarly obtained not only when the voltage switching circuit 54C in the circuit shown in FIG. 13 is applied to the voltage switching circuit 54D in FIG. 30 but also in the case of applying the circuit configurations in FIGS.

Also, in the circuits shown in FIGS. 31B to 31D, depletion type NMOS transistors QD5 to QD7 are used. The highest value Vm of the voltage applied to these transistors QD5 to QD7 is higher than the highest value VPPRW of the voltage applied to the depletion NMOS transistors QD1 to QD4 in the circuits shown in FIGS. 11 and 13 and FIGS. 22 to 25. (usually VPP) is also low. Therefore, the thickness of the gate oxide film of transistors QD5 to QD7 can be made thinner than that of the gate oxide film of transistors QD1 to QD4. Therefore, compared with the case where the thickness of the gate oxide film is thick, it is possible to reduce the area of the transistors QD5 to QD7 (because the lower the maximum applied voltage is, the lower the gate oxide film thickness is, the lower the gate oxide film thickness per unit area of the transistor is). The more the flow rate increases, it is possible to reduce the graphics footprint of the transistor) advantages.

For the same reason, the thickness of the gate oxide film of transistors QP14 to QP19, QN13 to QN18 may be thinner than that of transistors QP11 to QP13, QN13 to QN18. Therefore, in this case, there is an advantage that the area occupied by the pattern of the transistor can be made smaller than when the thickness of the gate oxide film is thin.

So far, Embodiment 5 has been described using FIG. 30 and FIGS. 31A to 31D, but the present invention can be modified in various ways. For example, the present invention is also effective when using a circuit configuration as shown in FIG. 32 and FIGS.

Fig. 32 shows a partial configuration example of a row decoder circuit in a semiconductor memory device according to Embodiment 6 of the present invention. The circuit shown in FIG. 32 supplies the output signal in1 of the inverter 58 and the output signal in2 of the NAND gate 57 in the circuit shown in FIG. 30 to the voltage switching circuit 54F respectively, and switches the voltage Output signals out1 and out2 of 54F are supplied to voltage switching circuit 54D.

33A to 33D are circuit diagrams each showing a specific configuration example of the voltage switching circuit 54F in the circuit shown in FIG. 32 described above. In these voltage switching circuits 54F, the output signal in1 of the input inverter 58 and the output signal in2 of the "NAND" gate 57, in the circuits shown in FIGS. 33A and 33B, when the signal in1 is "high" level ( When signal in2 is "low" level), signal out1 is 0V, signal out2 becomes Vm level, and signal out1 is Vm level when signal in1 is "low" level (signal in2 is "high" level), The signal out2 becomes 0V. In addition, in the circuit shown in Fig. 33C and 33D, when signal in1 is "high" level (signal in2 is "low" level), signal out1 is 0V, and signal out2 becomes Vcc level, when signal in1 is "Low" level (signal in2 is "high" level), the signal out1 becomes Vm level, and the signal out2 becomes 0V.

The circuit shown in FIG. 33A is composed of NMOS transistors QN13, QN14, and PMOS transistors QP14, QP15. The output signal in1 of the inverter 58 is supplied to the gate of the NMOS transistor QN14, and the output signal in2 of the NAND gate 57 is supplied to the gate of the NMOS transistor QN13. The sources of the NMOS transistors QN13 and QN14 are grounded, and the drains and sources of the PMOS transistors QP14 and QP15 are connected between the drain and the voltage node Vm, respectively. The gate of the PMOS transistor QP14 is connected to the drain common contact of the PMOS transistor QP15 and the NMOS transistor QN14, and the gate of the PMOS transistor QP15 is connected to the drain common contact of the PMOS transistor QP14 and the NMOS transistor QN13. Then, the output signal out11 is obtained from the gate common contact of the above-mentioned transistors QP15 and QN14, and the output signal out2 is obtained from the drain common contact of the above-mentioned transistors QP14 and QN13. are supplied to the input terminals of the voltage switching circuit 54D, respectively.

In addition, the circuit shown in FIG. 33B is composed of NMOS transistors QN15, QN16, PMOS transistors QP16, QP17, and a depletion NMOS transistor QD5. The output signal in1 of the inverter 58 is provided to the gate of the NMOS transistor QN16, the output signal in2 of the "NAND" gate 57 is provided to the gate of the NMOS transistor QN15, and the sources of the above-mentioned NMOS transistors QN15 and QN16 are grounded. The drains of the PMOS transistors QP16 and QP17 are connected to the drains, respectively. The gate of the PMOS transistor QP16 is connected to the drain common contact of the PMOS transistor QP17 and the NMOS transistor QN16, and the gate of the PMOS transistor QP17 is connected to the drain common contact of the PMOS transistor QP16 and the NMOS transistor QN15. . The drain and source of the depletion NMOS transistor QD5 are connected between the sources of the PMOS transistors QP16 and QP17 and the voltage contact Vm, and the gates thereof are connected to the common drain contact of the transistors QP17 and QN16. Then, the output signal out1 obtained from the drain common contact of the transistors QP17, QN16 and the output signal out2 obtained from the drain common contact of the transistors QP16, QN15 are supplied to the input terminal of the voltage switching circuit 54D, respectively.

The circuit shown in FIG. 33C is composed of an inverter INVe, an NMOS transistor QN17, a PMOS transistor QP18, and a depletion mode NMOS transistor QD6. The current paths of the transistors QN17, QP18, QD6 are connected in series between the ground point and the voltage node Vm, and the output signal in1 of the inverter 58 is supplied to the gates of the transistors QN17, QP18. In addition, the gate of the transistor QD6 is connected to the drain common contact of the transistors QN17 and QP18. Furthermore, the output signal in2 of the NAND gate 57 is supplied to the input terminal of the inverter INVe. Then, the output signal out1 obtained from the drain common contact of the transistors QN17, QP18 and the output signal out2 output from the output terminal of the inverter INVe are supplied to the input terminal of the voltage switching circuit 54D, respectively.

Furthermore, the circuit shown in FIG. 33D is composed of an inverter INVf, an NMOS transistor QN18, a PMOS transistor QP19, and a depletion NMOS transistor QD7. The output signal in1 of the inverter 58 is supplied to the gate of the PMOS transistor QP19, and the output signal in2 of the NAND gate 57 is supplied to one end of the current path of the NMOS transistor QN18 and the input end of the inverter INVf, respectively. The power supply voltage Vcc is applied to the gate of the transistor QN18, and the current paths of the PMOS transistor QP19 and the depletion NMOS transistor QD7 are connected in series between the other end of the current path of the transistor QN18 and the voltage node Vm. The gate of the transistor QD7 is connected to the connection point of the transistors QN18 and QP19. Then, the output signal out1 obtained from the drain-common connection point of the transistors QN18, QP19 and the signal out2 output from the output terminal of the inverter INVf are supplied to the input terminal of the voltage switching circuit 54D, respectively.

32 and 33A to 33D have the same advantages as the circuit configurations described in FIGS. 30 and 31A to 31D, and substantially the same effects can be obtained.

Furthermore, as n-well regions for constituting the PMOS transistors QP14 to QP19 in the circuits shown in FIGS. 31A to 31D and FIGS. 33A to 33D described above, in the case of the circuits shown in FIGS. Since the voltage VPPRW is applied to the n-well region in between, the above-mentioned configuration as shown in FIG. 12A is applicable. On the other hand, in the configurations shown in FIGS. 31B to 31D and FIGS. 33B to 33D, since the n-well voltage is not shared, the , 28 and the configurations shown in FIGS. 29A and 29B are applicable.

34 and 35 are diagrams showing a circuit portion that supplies voltage VPPRW to voltage switching circuits 54 (54A to 54D) in Embodiments 1 to 5 described above to illustrate semiconductor memory devices according to other embodiments of the present invention, respectively. These circuits switch the state of the power supply node VPPRW between the standby state and the active state according to the signal activity (Active).

That is, the circuit portion shown in FIG. 34 is composed of a high voltage generating circuit 60, an inverter 61, a PMOS transistor QP20, and a depletion mode NMOS transistor QD8. The output terminal of the high voltage generating circuit 60 is connected to the power supply node VPPRW of the voltage switching circuit 54, and the current paths of the transistors QD8 and QP20 are connected in series between the node VPPRW and the power supply voltage Vcc. The signal activity is supplied to the gate of the PMOS transistor QP20 via the inverter 61, and the signal activity is supplied to the gate of the depletion NMOS transistor QD8.

In the configuration as above, the active signal is 0 V in the standby state and Vcc level in the active state, and is generated based on, for example, a single-chip enable signal input from the /CE pin. In addition, the above-mentioned high voltage generating circuit 60 is configured to be in a non-operating state in the standby state.

In the standby state, since the transistor QP20 is turned off when the signal activity is 0V, the power supply node VPPRW is in a floating state. On the contrary, if the signal active becomes Vcc level in the active state, the node VPPRW is charged to a high voltage because the transistor QP20 is turned on. Thereafter, by the high voltage generating circuit 60, while the node VPPRW is set at a high potential, the signal activity becomes 0V, the transistor QD8 is turned off, and the power supply node VPPRW is disconnected from the power supply Vcc.

Therefore, in the standby state, the occurrence of leakage current can be suppressed, and in the active state (since Vcc can be charged at a high speed), the voltage of the power supply node VPPRW can be rapidly increased.

On the other hand, the circuit portion shown in FIG. 35 is composed of a high voltage generating circuit 60 and a depletion NMOS transistor QP9. The output terminal of the high voltage generating circuit 60 is connected to the power supply node VPPRW of the voltage switching circuit 54, and the current path of the transistor QD9 is connected between the node VPPRW and the power supply Vcc. Then, a signal activity is applied to the gate of the above-mentioned depletion NMOS transistor QD9.

Even in this configuration, the same operation as that of the above-mentioned circuit of FIG. 34 can be performed, and the same effect can be obtained.

As mentioned above, the present invention has been described using the embodiments, but the present invention is not limited to the above-described embodiments, and various modifications are possible.

For example, in the above embodiments, the present invention has been described by taking the case where a voltage of 0 V or more is transmitted to the selected word line as an example, but in the case where the polarity is reversed, that is, in the case of transmitting a voltage of 0 V or less to the selected word line The present invention is also effective. In this case, while changing the NMOS transistors in the above-mentioned voltage switching circuit to PMOS transistors, and changing the PMOS transistors in the above-mentioned voltage switching circuit to NMOS transistors, the word lines connected in series The present invention can be applied to methods such as changing the transistor from an NMOS transistor to a PMOS transistor, reversing the polarity, and the like.

In addition, in the above-mentioned embodiment, the present invention has been described by taking the case where the present invention is applied to the row decoder circuit as an example, but in other cases, various changes are possible, for example, in other peripheral circuits, the above-mentioned The configuration and connection relationship of the voltage switching circuit and the word line connection transistor in the embodiment, and the voltage transmission and the like are performed.

In addition, in the above embodiment, the case where the number of memory cells connected in series in one NAND cell is 8 is described, but the number of memory cells connected in series is not 8 but, for example, 2, 4, The present invention can also be applied to 16, 32, 64, etc. cases. Also, the present invention can be similarly applied to a case where there is only one memory cell located between select gate transistors. In addition, in the above-mentioned embodiment, the present invention is described by taking NAND type EEPROM as an example, but the present invention is not limited to the above-mentioned embodiment, in other equipment, for example, in NOR cell type EEPROM, DINOR cell type EEPROM, AND cell type EEPROM , NOR cell type EEPROM with selection transistors, etc. can also be applied.

36 shows an equivalent circuit diagram of a memory cell array in a NOR cell type EEPROM. In the memory cell array, NOR cells Mj0 are arranged at intersections of word lines WLj, WLj+1, WLj+2, ... and bit lines BL0, BL1, ..., BLm. ~Mj+2m, the control gates of each NOR unit Mj0~Mj+2m are respectively connected to word lines WLj, WLj+1, WLj+2,... on each row, and the drains are respectively connected to each column They are connected to the bit lines BL0, BL1, . . . BLm, and the sources are commonly connected to the source line SL.

In addition, an equivalent circuit of a memory cell array in a DINOR cell type EEPROM is shown in FIG. 37 . In the DINOR cell type memory cell array, DINOR cells are provided corresponding to the main bit lines D0, D1, . . . , Dn. Each DINOR unit is composed of selection gate transistors SQ0, SQ1, . . . , SQn and memory cells M00-M31n. Connected to the main bit lines D0, D1, ..., Dn, the gate is connected to the selection gate line ST, and the source is connected to the local bit lines LB0, LB1, ..... .LBn on. The drains of the memory cells M00-M31n are connected to the local bit lines LB0, LB1, ..., LBn in each column, and the control gates are connected to the word lines W0-W31 in each row. , the sources are commonly connected to the source line SL.

FIG. 38 is an equivalent circuit diagram showing a memory cell array in an AND cell type EEPROM. In the AND cell type memory cell array, AND cells are provided corresponding to the main bit lines D0, D1, . . . , Dn. Each AND unit is composed of first selection gate transistors SQ10, SQ11, ..., SQ1n, memory cells M00-M31n, and second selection gate transistors SQ20, SQ21, ..., SQ2n. The drains of the first selection gate transistors SQ10, SQ11, ..., SQ1n are respectively connected to the main bit lines D0, D1, ... Dn, and the gates are connected to the first selection gate The pole line ST1 and the source are respectively connected to the local bit lines LB0, LB1, . . . , LBn. The drains of each memory cell M00-M31n are connected to the local bit lines LB0, LB1, ... LBn in each column, the control gates are connected to the word lines W0-W31 in each row, and the source are connected to local source lines LS0, LS1, . . . LSn. The drains of the second selection gate transistors SQ20, SQ21, ..., SQ2n are respectively connected to the local source lines LS0, LS1, ..., LSn, and the gates are connected to The source of the second selection gate ST2 is commonly connected to the main source line MSL.

Furthermore, FIG. 39 shows an equivalent circuit diagram of a memory cell array in a NOR cell type EEPROM with selection transistors. This memory cell array is constituted by arranging memory cells MC composed of select transistors SQ and memory cell transistors M in a matrix. The drain of each selection transistor SQ is connected to the bit lines BL0, BL1, . . . , BLn in each column, the gate is connected to the selection gate line ST in each row, and the source is connected to on the drain of the corresponding memory cell transistor M. The control gates of the memory cell transistors M are connected to the word line WL for each row, and the sources are commonly connected to the source SL.

Furthermore, for details about the DINOR cell type EEPROM, please refer to "H. Onda et al., IEDM Tech. Digest, 1992, pp.599-602", and for details about the above-mentioned AND cell type EEPROM, please refer to "H.Kume et al. ., IEDM Tech. Digest, 1992, pp.991-993.

In addition, in the above-mentioned embodiments, the present invention has been described by taking an electrically rewritable nonvolatile semiconductor memory device as an example, but the present invention can also be used in other devices, for example, even in other nonvolatile memory devices It is also applicable to devices such as DRAM and SRAM.

Although the present invention has been described using the above embodiments, the present invention is not limited to the above embodiments, and various modifications can be made within a range not departing from the gist thereof during implementation. Furthermore, inventions at various stages are included in the above-described embodiments, and various inventions can be extracted by appropriately combining a plurality of constituent elements shown. For example, even if several constituent elements are deleted from all the constituent elements shown in the embodiments, at least one of the problems described in the subject to be solved by the invention can be solved, and the effect described in the effect of the invention can be obtained. In the case of at least one of the components, the configuration in which the constituent elements have been eliminated can be extracted as an invention.

According to the present invention as described above, since the voltage switching circuit including PMOS transistors is provided in the row decoder circuit, even if the transistor connected to the word line in the row decoder circuit is provided with one NMOS transistor per word line In this case, the gate of the NMOS transistor can be set to a high voltage without providing a pump circuit.

Therefore, a high voltage can be transmitted to the word line without a potential drop, and a semiconductor memory device in which the pattern area of the row decoder circuit can be reduced can be obtained.

In addition, since a row decoder circuit with a small pattern area can be realized, a highly reliable monolithic semiconductor memory device can be realized at an inexpensive price.

Furthermore, a high voltage can be transmitted to the word line without a potential drop, and a semiconductor memory device capable of realizing a sufficient data writing operation can be obtained.

Claims (28)

1. semiconductor storage comprises:

Memory cell is arranged in the memory cell array of matrix, comprises a plurality of word lines;

The 1st transistor of the 1st conduction type, the described the 1st transistorized source electrode is connected with a corresponding word line in a plurality of described word lines;

With the 2nd transistor of opposite polarity the 2nd conduction type of the 1st conduction type, described the 2nd transistor drain is connected with the described the 1st transistorized grid;

The 3rd transistor of the 1st conduction type, the described the 3rd transistorized source electrode is connected with the described the 1st transistorized grid;

Wherein, read action in data, in at least one action in data write activity and the data erase action, the voltage level of described the 2nd transistorized source electrode is different with the voltage level of described the 3rd transistor drain, read action in data, in at least one action in data write activity and the data erase action, the described the 2nd transistorized grid has different voltage levels with described the 3rd transistor drain, and when described the 3rd transistor drain becomes low logic level and high logic level, the described the 2nd transistorized grid becomes high logic level and low logic level respectively

Wherein, at least a portion of described data write activity, the voltage level that is connected to described the 1st transistorized grid of selected word line is higher than the voltage level of described the 1st transistor drain that is connected to selected word line.

2. according to the semiconductor storage of claim 1, comprising:

Row decoder circuits is used for selecting the word line of above-mentioned memory cell array and is used for providing voltage to described word line,

Wherein, described row decoder circuits comprises described the 1st transistor, the 2nd transistor and the 3rd transistor.

3. according to the semiconductor storage of claim 1, comprising:

A plurality of, each of described has the memory cell that is connected with 2 or more word line; With

Row decoder circuits is used for selecting the word line of above-mentioned memory cell array and is used for providing voltage to described word line,

Wherein, be each the described described row decoder circuits of configuration, described row decoder circuits comprises described the 1st transistor, the 2nd transistor and the 3rd transistor.

4. according to the semiconductor storage of claim 3, wherein, the described 1st transistorized described grid of described the 2nd transistor in the row decoder circuits corresponding with selecting piece provides the 1st voltage; The described 1st transistorized described grid of described the 3rd transistor in the row decoder circuits corresponding with non-selection piece provides the 2nd voltage; Described the 1st voltage is different with described the 2nd voltage.

5. according to the semiconductor storage of claim 3, wherein, described the 2nd transistor turns in the row decoder circuits corresponding with selecting piece; Described the 2nd transistor in the row decoder circuits corresponding with non-selection piece ends; Described the 3rd transistor turns in the row decoder circuits corresponding with non-selection piece.

6. according to the semiconductor storage of claim 3, wherein,

In the 1st action, the described 1st transistorized described grid of described the 2nd transistor in the row decoder circuits corresponding with selecting piece provides the 1st voltage; The described 1st transistorized described grid of described the 3rd transistor in the row decoder circuits corresponding with non-selection piece provides the 2nd voltage;

In the 2nd action, the described 1st transistorized described grid of described the 3rd transistor in the row decoder circuits corresponding with selecting piece provides the 3rd voltage; The described 1st transistorized described grid of described the 3rd transistor in the row decoder circuits corresponding with non-selection piece provides the 4th voltage;

Described the 1st voltage is different with described the 2nd voltage, and described the 3rd voltage is different with described the 4th voltage.

7. according to the semiconductor storage of claim 6, wherein, described the 1st action is the data write activities, and described the 2nd action is the data erase action.

8. according to the semiconductor storage of claim 3, wherein,

In the 1st action, described the 2nd transistor turns in the row decoder circuits corresponding with selecting piece; Described the 2nd transistor in the row decoder circuits corresponding with non-selection piece ends; Described the 3rd transistor in the row decoder circuits corresponding with selecting piece ends; Described the 3rd transistor turns in the row decoder circuits corresponding with non-selection piece,

In the 2nd action, described the 2nd transistor in the row decoder circuits corresponding with non-selection piece ends; Described the 3rd transistor turns in the row decoder circuits corresponding with selecting piece; Described the 3rd transistor turns in the row decoder circuits corresponding with non-selection piece.

9. semiconductor storage according to Claim 8, wherein, described the 1st action is the data write activities, described the 2nd action is the data erase action.

10. according to the semiconductor storage of claim 1, wherein, the described the 3rd transistorized threshold voltage is lower than the described the 1st transistorized threshold voltage.

11. according to the semiconductor storage of claim 1, wherein, described the 3rd transistor is a depletion mode transistor.

12. according to the semiconductor storage of claim 1, wherein, the described the 1st transistorized threshold voltage is higher than 0V.

13. the semiconductor storage according to claim 1 also comprises:

The 4th transistor of the 1st conduction type, described the 3rd transistor of described the 4th transistor AND gate is connected, and described the 3rd transistor series of wherein said the 4th transistor AND gate connects, and described the 3rd transistor is connected between described the 4th transistor AND gate the described the 1st transistorized grid.

14. according to the semiconductor storage of claim 13, wherein, the described the 4th transistorized threshold voltage is lower than the described the 1st transistorized threshold voltage.

15. according to the semiconductor storage of claim 13, wherein, described the 3rd transistor and described the 4th transistor all are depletion mode transistors.

16. the semiconductor storage according to claim 3 also comprises:

Logical circuit, being used to receive block address signal and output is to select or the corresponding decision signal of non-selected result of determination with piece;

Wherein, described the 3rd transistor is sent to the described the 1st transistorized grid in the non-selection piece with corresponding decision signal.

17. the semiconductor storage according to claim 3 also comprises:

Logical circuit, being used to receive block address signal and output is to select or the corresponding decision signal of non-selected result of determination with piece;

Wherein, described decision signal is sent to described the 3rd transistor drain, and have the logic level opposite with the level of described decision signal paraphase decision signal be input into the described the 2nd transistorized grid.

18. according to the semiconductor storage of claim 1, wherein, when described the 2nd transistor ended, described the 3rd transistor provided voltage to the described the 1st transistorized grid.

19. the semiconductor storage according to claim 1 also comprises:

With the 4th transistor of selecting gate line to be connected,

Wherein, the described the 4th transistorized source electrode or drain electrode are connected with described selection gate line; The described the 4th transistorized grid is connected with the described the 1st transistorized grid.

20. the semiconductor storage according to claim 1 also comprises:

The 4th transistor of the 1st conduction type, the described the 4th transistorized source electrode is connected with the described the 2nd transistorized source electrode;

Wherein, described the 4th transistor drain is not connected with the described the 1st transistorized grid, and the described the 4th transistorized grid is connected with the described the 1st transistorized grid.

21. according to the semiconductor storage of claim 20, wherein, the described the 4th transistorized threshold voltage is lower than the described the 1st transistorized threshold voltage.

22. according to the semiconductor storage of claim 20, wherein, described the 4th transistor is a depletion mode transistor.

23., wherein, only apply voltage to each described word line by described the 1st transistor according to the semiconductor storage of claim 1.

24. according to the semiconductor storage of claim 1, wherein,

When selecting word line to be applied in the 2nd voltage, described the 2nd transistor applies the 1st voltage to the described the 1st transistorized grid that is connected with described selection word line,

Wherein, described the 1st voltage is that data write voltage; Described the 1st voltage is higher than supply voltage; Described the 2nd voltage is higher than described the 1st voltage.

25. according to the semiconductor storage of claim 3, wherein,

In data are read at least one action in action, data write activity and the data erase action, the 1st voltage is applied on the described the 2nd transistorized source electrode, and described the 2nd transistor is only to transmitting described the 1st voltage with selecting the described the 1st transistorized grid in the corresponding row decoder circuits of piece.

26. according to the semiconductor storage of claim 1, wherein, the described the 2nd transistorized grid is set to following voltage, this voltage is substantially equal to the supply voltage in the non-selection piece, and is lower than the supply voltage of selecting in the piece.

27. according to the semiconductor storage of claim 1, wherein, described memory cell is the memory cell with Nonvolatile semiconductor memory device of selecting gridistor.

28. according to the semiconductor storage of claim 1, wherein, described memory cell is the memory cell of NAND haplotype EEPROM.

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