CN100571329C - A kind of method of video-frequency picture geometrical distortion correction - Google Patents
A kind of method of video-frequency picture geometrical distortion correction Download PDFInfo
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Abstract
A kind of method of video-frequency picture geometrical distortion correction comprises step: a1, read the row value and the train value of pixel address in the frame memory; A2, according to certain mode described row value and train value among the step a1 are changed, the frame memory after obtaining proofreading and correct reads the address, this is read the address deposit in and read addressed memory; A3, the mode that foundation is certain change described row value and train value among the step a1, and the pixel explicit address after obtaining proofreading and correct deposits this explicit address in the explicit address memory.Adopt technical solution of the present invention, can carry out precorrection to the display image dot matrix that produces geometric distortion effectively.
Description
Technical field
The present invention relates to the video display technology field, be specifically related to a kind of method of video-frequency picture geometrical distortion correction.
Background technology
Along with science and technology and rapid development of economy, display device has become government's office, the education demonstration, indispensable important component part in commercial activity and even the home entertaining, various customer groups to the demand of display effect in continuous lifting, and for special display modes such as Projection Display, owing to the asymmetry of light path design or the reasons such as restriction of service condition, can cause last resulting display image more serious trapezoidal distortion to occur, to this distortion as can not on signal processing, carrying out precorrection, will influence its result of use greatly, be restricted thereby make to use.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of method of video-frequency picture geometrical distortion correction.
The present invention adopts following technical scheme:
A kind of method of video-frequency picture geometrical distortion correction comprises step:
A1, read the row value and the train value of pixel address in the frame memory;
A2, according to certain mode described row value and train value among the step a1 are changed, the frame memory after obtaining proofreading and correct reads the address, this is read the address deposit in and read addressed memory;
A3, the mode that foundation is certain change described row value and train value among the step a1, and the pixel explicit address after obtaining proofreading and correct deposits this explicit address in the explicit address memory.
Described method, wherein: described step a2 may further comprise the steps:
A21, the columns of pixel in the frame memory is deducted the horizontal direction minimum number of pixels of display image dot matrix and deposits first memory cell in, with the row among the step a1 on duty with first memory cell value and deposit second memory cell in, the line number of pixel in the frame memory is deducted the vertical direction minimum number of pixels of display image dot matrix and deposits the 3rd memory cell in, the train value among the step a1 be multiply by the value of the 3rd memory cell and deposits the 4th memory cell in;
A22, with first memory cell on duty with the train value among the step a1 and deposit first memory cell in, with the value of second memory cell divided by the line number of pixel in the frame memory and deposit second memory cell in, on duty with the 3rd memory cell with the row value and deposit the 3rd memory cell among the step a1, with the value of the 4th memory cell divided by the columns of pixel in the frame memory and deposit the 4th memory cell in;
A23, on duty with first memory cell with the row value and deposit first memory cell among the step a1, the columns of pixel in the frame memory is deducted the value of second memory cell and deposits second memory cell in, the 3rd memory cell on duty with the train value among the step a1 and deposit the 3rd memory cell in, deducted the line number of pixel in the frame memory value of the 4th memory cell and deposit the 4th memory cell in;
A24, with the value of first memory cell divided by the line number of pixel in the frame memory and deposit first memory cell in, with the value of the 3rd memory cell divided by the columns of pixel in the frame memory and deposit the 3rd memory cell in;
A25, with the train value among the value of first memory cell and the step a1 mutually adduction deposit first memory cell in, with the row value among the value of the 3rd memory cell and the step a1 mutually adduction deposit the 3rd memory cell in;
A26, with the value of first memory cell divided by the value of second memory cell and deposit first memory cell in, with the value of the 3rd memory cell divided by the value of the 4th memory cell and deposit the 3rd memory cell in;
A27, the value of first memory cell is rounded operation, the frame memory after obtaining proofreading and correct reads the row value of address, and the value of the 3rd memory cell is rounded operation, and the frame memory after obtaining proofreading and correct reads the train value of address.
Described method, wherein: described step a3 may further comprise the steps:
A31, the columns of pixel in the frame memory is deducted the horizontal direction minimum number of pixels of display image dot matrix and deposits first memory cell in, the line number of pixel in the frame memory is deducted the vertical direction minimum number of pixels of display image dot matrix and deposits second memory cell in;
A32, on duty with first memory cell with the row value and deposit first memory cell among the step a1, with second memory cell on duty with the capable value among the step a1 and deposit second memory cell in;
A33, with first memory cell on duty with the train value among the step a1 and deposit first memory cell in, with second memory cell on duty with the train value among the step a1 and deposit second memory cell in;
A34, with the value of first memory cell divided by the line number of pixel in the frame memory and deposit first memory cell in, with the value of second memory cell divided by the columns of pixel in the frame memory and deposit second memory cell in;
A35, with first memory cell on duty with 2 and deposit first memory cell in, with second memory cell on duty with 2 and deposit second memory cell in;
A36, get value reciprocal of first memory cell and deposit first memory cell in, get value reciprocal of second memory cell and deposit second memory cell in;
Train value among the value of a37, first memory cell and step a1 adduction mutually deposits first memory cell in, and the row value among the value of second memory cell and step a1 adduction mutually deposits second memory cell in;
A38, the value of first memory cell is rounded operation, the row value of the pixel explicit address after obtaining proofreading and correct rounds operation, the train value of the pixel explicit address after obtaining proofreading and correct to the value of second memory cell.
Described method, wherein: the operation that rounds of described step a27 and a38 adopts the mode that rounds up to carry out.
Adopt technical solution of the present invention, can carry out precorrection to the display image dot matrix that produces geometric distortion effectively.
Description of drawings
Fig. 1 is the pixel-matrix schematic diagram of vertical trapezium distortion through showing on display screen or display light chip after the precorrection;
Fig. 2 is the pixel-matrix schematic diagram of vertical trapezium distortion through showing on display screen or display light chip after the symmetrical precorrection;
Fig. 3 is a horizontal direction trapezoidal distortion profile schematic diagram;
Fig. 4 is compound trapezoidal distortion profile schematic diagram;
Fig. 5 is the system configuration schematic diagram of video-frequency picture geometrical distortion correction of the present invention.
Embodiment
Below in conjunction with drawings and Examples the present invention is described in further detail:
Vertical trapezium distortion
Fig. 1 is the pixel-matrix schematic diagram of vertical trapezium distortion through showing on display screen or display light chip after the precorrection, wherein, L is that horizontal direction is to proofread and correct vertical trapezium distortion minimum number of pixels in the horizontal direction, compare with the initial pictures display format, its horizontal direction minor face than long limit pixel count reduction is
ΔHM＝N-L 2-1
Because image outline is a trapezoidal distortion, the minimizing of Horizontal number of pixels is a linear change vertically, and therefore, for any row (it is capable to be made as i) wherein, the reduction of its pixel count is
ΔHi＝ΔHM*(i-1)/(M-1)＝(N-L)*(i-1)/(M-1)
2-2
In the ordinary course of things, satisfy M＞i＞＞1, so
ΔHi≈(N-L)*i/M 2-3
For the capable any pixel of i, each pixel average column address variable quantity of reading of data from frame memory is
ΔaHi＝ΔHi/(l-1)≈ΔHi/l
2-4
Wherein, 1=N-Δ Hi=N-(N-L) * i/M, so
ΔaHi＝ΔHi/(N-ΔHi)＝((N-L)*i/M)/(N-(N-L)*i/M)
2-5
So for carrying out any pixel a ' ij that vertically trapezoidal (in advance) distortion correction shows, the column address of reads pixel data is in the frame memory
aH?ij＝j+(j-1)*ΔaHi 2-6
For ordinary circumstance, satisfy j＞＞1, so
aH?ij≈INT(j+j*ΔaHi)＝INT(j+((N-L)*j*i/M)/(N-(N-L)*i/M))
2-7
Because memory address must be an integer, the aH ij that following formula is calculated is by " rounding up " round numbers.
Therefore, for any pixel a ' ij, have
a′ij＝a[aH?ij，i]＝a[INT(j+((N-L)*j*i/M)/(N-(N-L)*i/M))，i].
2-8
To be arranged in horizontal direction be asymmetric to the represented pixel distribution of new demonstration trapezoidal distortion image after overcorrect in Fig. 1, this does not conform to general situation, general demonstration trapezoidal distortion (such as the projection optical axis oblique distortions) is symmetrical, so the predistortion of required demonstration also is symmetrical, therefore to each display pixel, can on the basis of original explicit address, add an address offset amount Δ Ai as finally going up new explicit address at display screen (or display light chip), this address side-play amount changes according to the residing line number of pixel, for the capable pixel of i, its final display offset amount is
ΔAi＝INT(1/2*ΔHi)＝INT(1/2*(N-L)*i/M)
2-9
Promptly for any pixel a ' ij, its original explicit address is [j, i], and after overcorrect, its new display column address is
AHij＝j+ΔAi＝j+INT(1/2*(N-L)*i/M)＝
INT(j+(1/2*(N-L)*i/M))
2-10
For the pixel of the capable j row of i, press [INT (j+ ((N-L) * j*i/M)/(N-(N-L) * i/M)), i] address read pixel value from frame memory, and on display screen or display light chip, show by [INT (j+ (1/2* (N-L) * i/M)), i] address.If the pixel of the capable j row of i is a in the new display format " ij, then
a″ij＝a[INT(j+(1/2*(N-L)*i/M))，i]
2-19
The pixel-matrix that shows on display screen or display light chip after the symmetrical precorrection of vertical trapezium distortion process as shown in Figure 2.
Horizontal trapezoidal distortion
Have the symmetry situation of keystone correction in advance for horizontal direction, its image fault profile as shown in Figure 3.
Copy Fig. 1, establish horizontal trapezoidal distortion through in the pixel-matrix form of precorrection, the pixel count on long limit is M, and the pixel count of minor face is F, and according to same analytical method, for any pixel a ' ij, the read row address of its pixel value should be as can be known
aV?ij＝INT(i+((M-F)*i*j/N)/(M-(M-F)*j/N))
2-20
Promptly
a′ij＝a[j，INT(i+((M-F)*i*j/N)/(M-(M-F)*j/N))]
2-21
Its new display line address is
Avij＝INT(i+(1/2*(M-F)*j/N)) 2-22
Promptly
a″ij＝a?[j，INT(i+(1/2*(M-F)*j/N))] 2-23
Pixel for the capable j row of i, should be according to address [j, INT (i+ ((M-F) * i*j/N)/(M-(M-F) * j/N))] read pixel value from frame memory, go up demonstration according to new address [j, INT (i+ (1/2* (M-F) * j/N))] at display screen (or display light chip) again.
Compound trapezoidal distortion
The situation that all has a trapezoidal distortion for level and vertical both direction as shown in Figure 4, if the maximum pixel number of horizontal direction is N, minimum number of pixels is L, the maximum pixel number of vertical direction is M, minimum number of pixels is F, then for initial pictures, and its any pixel a ' ij, its pixel value should read from frame memory according to address [INT (j+ ((N-L) * j*i/M)/(N-(N-L) * i/M)), INT (i+ ((M-F) * i*j/N)/(M-(M-F) * j/N))].Promptly
a′ij＝a[INT(j+((N-L)*j*i/M)/(N-(N-L)*i/M))，
INT(i+((M-F)*i*j/N)/(M-(M-F)*j/N))]
2-24
Equally, for the compound pre-keystone correction of symmetry,, go up the new address that shows at display screen (or display light chip) and should be [INT (j+ (1/2* (N-L) * i*j/M)), INT (i+ (1/2* (M-F) * i*j/N))] for the pixel of the capable j row of i.Promptly
a″ij＝[INT(j+(1/2*(N-L)*i*j/M))，INT(i+(1/2*(M-F)*i*j/N))]
2-25
Fig. 5 is the system configuration schematic diagram of video-frequency picture geometrical distortion correction of the present invention, as shown in Figure 5, described system comprises microprocessor, clock generator, signal processor, display driver, it is characterized in that: also comprise the frame memory that is used to store the picture signal that receives, be used for the addressed memory that writes that the control chart image signal writes frame memory, be used to store correction back frame memory and read the addressed memory of reading of address, be used to store the explicit address memory of the explicit address of proofreading and correct the back pixel, write addressed memory and read addressed memory and link to each other with frame memory by address bus, the explicit address memory links to each other with display driver by address bus, and microprocessor is by control bus and write addressed memory, read addressed memory, explicit address memory and signal processor link to each other.
Microprocessor calculates reading the address and be stored in and reading in the addressed memory of each pixel value correspondence according to formula 2-8 or 2-21 or 2-24 when adopting this circuit system to carry out keystone correction, calculate the explicit address of each pixel and be stored in the explicit address memory according to formula 2-19 or 2-23 or 2-25, display screen (or display light chip) carries out screen display by this address, in three groups of formula, 2-8 and 2-19 are at the situation of having only vertical trapezium distortion, 2-21 and 2-23 are at the situation of having only horizontal trapezoidal distortion, 2-24 and 2-25 have considered the situation of vertical and horizontal both direction trapezoidal distortion simultaneously, be that formula 2-24 and 2-25 have more generality, as general formula, only need adopt these two formula just passable during calculating.
Concrete video-frequency picture geometrical distortion correction is taked following steps:
A1, read the row value and the train value of pixel address in the frame memory;
A2, according to certain mode described row value and train value among the step a1 are changed, the frame memory after obtaining proofreading and correct reads the address, this is read the address deposit in and read addressed memory;
A3, the mode that foundation is certain change described row value and train value among the step a1, and the pixel explicit address after obtaining proofreading and correct deposits this explicit address in the explicit address memory.
Described step a2 may further comprise the steps:
A21, the columns of pixel in the frame memory is deducted the horizontal direction minimum number of pixels of display image dot matrix and deposits first memory cell in, with the row among the step a1 on duty with first memory cell value and deposit second memory cell in, the line number of pixel in the frame memory is deducted the vertical direction minimum number of pixels of display image dot matrix and deposits the 3rd memory cell in, the train value among the step a1 be multiply by the value of the 3rd memory cell and deposits the 4th memory cell in;
A22, with first memory cell on duty with the train value among the step a1 and deposit first memory cell in, with the value of second memory cell divided by the line number of pixel in the frame memory and deposit second memory cell in, on duty with the 3rd memory cell with the row value and deposit the 3rd memory cell among the step a1, with the value of the 4th memory cell divided by the columns of pixel in the frame memory and deposit the 4th memory cell in;
A23, on duty with first memory cell with the row value and deposit first memory cell among the step a1, the columns of pixel in the frame memory is deducted the value of second memory cell and deposits second memory cell in, the 3rd memory cell on duty with the train value among the step a1 and deposit the 3rd memory cell in, deducted the line number of pixel in the frame memory value of the 4th memory cell and deposit the 4th memory cell in;
A24, with the value of first memory cell divided by the line number of pixel in the frame memory and deposit first memory cell in, with the value of the 3rd memory cell divided by the columns of pixel in the frame memory and deposit the 3rd memory cell in;
A25, with the train value among the value of first memory cell and the step a1 mutually adduction deposit first memory cell in, with the row value among the value of the 3rd memory cell and the step a1 mutually adduction deposit the 3rd memory cell in;
A26, with the value of first memory cell divided by the value of second memory cell and deposit first memory cell in, with the value of the 3rd memory cell divided by the value of the 4th memory cell and deposit the 3rd memory cell in;
A27, the value of first memory cell is rounded operation, the frame memory after obtaining proofreading and correct reads the row value of address, and the value of the 3rd memory cell is rounded operation, and the frame memory after obtaining proofreading and correct reads the train value of address.
Described step a3 may further comprise the steps:
A31, the columns of pixel in the frame memory is deducted the horizontal direction minimum number of pixels of display image dot matrix and deposits first memory cell in, the line number of pixel in the frame memory is deducted the vertical direction minimum number of pixels of display image dot matrix and deposits second memory cell in;
A32, on duty with first memory cell with the row value and deposit first memory cell among the step a1, with second memory cell on duty with the capable value among the step a1 and deposit second memory cell in;
A33, with first memory cell on duty with the train value among the step a1 and deposit first memory cell in, with second memory cell on duty with the train value among the step a1 and deposit second memory cell in;
A34, with the value of first memory cell divided by the line number of pixel in the frame memory and deposit first memory cell in, with the value of second memory cell divided by the columns of pixel in the frame memory and deposit second memory cell in;
A35, with first memory cell on duty with 2 and deposit first memory cell in, with second memory cell on duty with 2 and deposit second memory cell in;
A36, get value reciprocal of first memory cell and deposit first memory cell in, get value reciprocal of second memory cell and deposit second memory cell in;
Train value among the value of a37, first memory cell and step a1 adduction mutually deposits first memory cell in, and the row value among the value of second memory cell and step a1 adduction mutually deposits second memory cell in;
A38, the value of first memory cell is rounded operation, the row value of the pixel explicit address after obtaining proofreading and correct rounds operation, the train value of the pixel explicit address after obtaining proofreading and correct to the value of second memory cell.
Although with reference to embodiment the present invention is illustrated and describes, those skilled in the art can understand, and under the situation that does not depart from scope and spirit of the present invention, can carry out all conspicuous modification of form and details to it.Under the situation that does not break away from the spirit and scope of the present invention, all variations and modification are all within appended claims institute restricted portion.
Claims (2)
1, a kind of method of video-frequency picture geometrical distortion correction comprises step:
A1, read the row value and the train value of pixel address in the frame memory;
A2, according to certain mode described row value and train value among the step a1 are changed, the frame memory after obtaining proofreading and correct reads the address, this is read the address deposit in and read addressed memory;
A3, the mode that foundation is certain change described row value and train value among the step a1, and the pixel explicit address after obtaining proofreading and correct deposits this explicit address in the explicit address memory;
It is characterized in that: described step a2 may further comprise the steps:
A21, the columns of pixel in the frame memory is deducted the horizontal direction minimum number of pixels of display image dot matrix and deposits first memory cell in, with the row among the step a1 on duty with first memory cell value and deposit second memory cell in, the line number of pixel in the frame memory is deducted the vertical direction minimum number of pixels of display image dot matrix and deposits the 3rd memory cell in, the train value among the step a1 be multiply by the value of the 3rd memory cell and deposits the 4th memory cell in;
A22, with first memory cell on duty with the train value among the step a1 and deposit first memory cell in, with the value of second memory cell divided by the line number of pixel in the frame memory and deposit second memory cell in, on duty with the 3rd memory cell with the row value and deposit the 3rd memory cell among the step a1, with the value of the 4th memory cell divided by the columns of pixel in the frame memory and deposit the 4th memory cell in;
A23, on duty with first memory cell with the row value and deposit first memory cell among the step a1, the columns of pixel in the frame memory is deducted the value of second memory cell and deposits second memory cell in, the 3rd memory cell on duty with the train value among the step a1 and deposit the 3rd memory cell in, deducted the line number of pixel in the frame memory value of the 4th memory cell and deposit the 4th memory cell in;
A24, with the value of first memory cell divided by the line number of pixel in the frame memory and deposit first memory cell in, with the value of the 3rd memory cell divided by the columns of pixel in the frame memory and deposit the 3rd memory cell in;
A25, with the train value among the value of first memory cell and the step a1 mutually adduction deposit first memory cell in, with the row value among the value of the 3rd memory cell and the step a1 mutually adduction deposit the 3rd memory cell in;
A26, with the value of first memory cell divided by the value of second memory cell and deposit first memory cell in, with the value of the 3rd memory cell divided by the value of the 4th memory cell and deposit the 3rd memory cell in;
A27, the value of first memory cell is rounded operation, the frame memory after obtaining proofreading and correct reads the row value of address, and the value of the 3rd memory cell is rounded operation, and the frame memory after obtaining proofreading and correct reads the train value of address;
Described step a3 may further comprise the steps:
A31, the columns of pixel in the frame memory is deducted the horizontal direction minimum number of pixels of display image dot matrix and deposits first memory cell in, the line number of pixel in the frame memory is deducted the vertical direction minimum number of pixels of display image dot matrix and deposits second memory cell in;
A32, on duty with first memory cell with the row value and deposit first memory cell among the step a1, with second memory cell on duty with the capable value among the step a1 and deposit second memory cell in;
A33, with first memory cell on duty with the train value among the step a1 and deposit first memory cell in, with second memory cell on duty with the train value among the step a1 and deposit second memory cell in;
A34, with the value of first memory cell divided by the line number of pixel in the frame memory and deposit first memory cell in, with the value of second memory cell divided by the columns of pixel in the frame memory and deposit second memory cell in;
A35, with first memory cell on duty with 2 and deposit first memory cell in, with second memory cell on duty with 2 and deposit second memory cell in;
A36, get value reciprocal of first memory cell and deposit first memory cell in, get value reciprocal of second memory cell and deposit second memory cell in;
Train value among the value of a37, first memory cell and step a1 adduction mutually deposits first memory cell in, and the row value among the value of second memory cell and step a1 adduction mutually deposits second memory cell in;
A38, the value of first memory cell is rounded operation, the row value of the pixel explicit address after obtaining proofreading and correct rounds operation, the train value of the pixel explicit address after obtaining proofreading and correct to the value of second memory cell.
2, the method for video-frequency picture geometrical distortion correction according to claim 1 is characterized in that: the operation that rounds of described step a27 and a38 adopts the mode that rounds up to carry out.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1230849A (en) * | 1997-09-30 | 1999-10-06 | 松下电器产业株式会社 | Television receiver, video signal processing device, image processing device and method |
| CN1316157A (en) * | 1999-06-30 | 2001-10-03 | 皇家菲利浦电子有限公司 | Method and apparatus for correcting convergence and geometry errors in display devices |
| CN1435999A (en) * | 2002-01-28 | 2003-08-13 | 日本电气视象技术株式会社 | Projection display device with distortion correction function |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1230849A (en) * | 1997-09-30 | 1999-10-06 | 松下电器产业株式会社 | Television receiver, video signal processing device, image processing device and method |
| CN1316157A (en) * | 1999-06-30 | 2001-10-03 | 皇家菲利浦电子有限公司 | Method and apparatus for correcting convergence and geometry errors in display devices |
| CN1435999A (en) * | 2002-01-28 | 2003-08-13 | 日本电气视象技术株式会社 | Projection display device with distortion correction function |
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