CN100578329C - Liquid crystal display device, pixel structure and driving method thereof - Google Patents

Abstract

The invention discloses a pixel structure, comprising a first scan line, a second scan line, a data line, a first thin film transistor, a first pixel electrode, a second thin film transistor, a second pixel electrode, a third thin film transistor, and a charge sharing capacitor and a fourth thin film transistor. The first thin film transistor is electrically connected to the first scan line and the data line, and the first thin film transistor has a first drain, and the first pixel electrode is electrically connected to the first drain. The second thin film transistor is electrically connected to the first scan line and the data line, and the second thin film transistor has a second drain, and the second pixel electrode is electrically connected to the second drain. The third thin film transistor is electrically connected to the second scan line and the data line, and the third thin film transistor has a third drain, and the charge sharing capacitor is electrically connected to the third drain. The source and drain of the fourth thin film transistor are respectively connected to the second pixel electrode and the charge sharing capacitor, and the gate of the fourth thin film transistor is connected to an auxiliary scanning line.

Description

Liquid crystal display device, pixel structure and driving method thereof

technical field

The present invention relates to a liquid crystal display device, more specifically, to a vertical alignment (Vertical alignment) mode liquid crystal display device, a pixel structure and a driving method thereof, which can improve the viewing angle of the liquid crystal display device.

Background technique

Liquid crystal displays are currently one of the most widely used types of flat panel display devices. A liquid crystal display generally includes two substrates: an array substrate and a color filter substrate, and a liquid crystal layer interposed between the two substrates, which have pixel electrodes and a common electrode for generating an electric field. A liquid crystal display displays an image by applying a voltage to an electric field generating electrode to generate an electric field in a liquid crystal layer. This electric field determines the alignment of liquid crystal molecules in the liquid crystal layer and controls the polarization of incident light, thereby controlling the brightness of light passing through the polarizing plate on the color filter substrate to achieve different display levels.

Recently, among different types of liquid crystal displays, a liquid crystal display with a vertical alignment mode has been widely used due to its high contrast ratio and relatively wide reference viewing angle. In the vertical alignment mode, the liquid crystal molecules are arranged in such a way that when no electric field is generated between the pixel electrode and the common electrode, the main axes of the liquid crystal molecules are perpendicular to the upper and lower substrates. As used herein, "reference viewing angle" means a viewing angle corresponding to a contrast ratio of 1:10 or a limiting angle for brightness inversion between gray levels.

In a liquid crystal display having a vertical alignment mode, in order to increase a viewing angle, slits may be formed in the pixel electrode and the common electrode, and further, protrusions may be formed in the pixel electrode and the common electrode to widen the reference viewing angle. Since the cutouts and protrusions can be used to control the tilt direction of liquid crystal molecules, liquid crystal molecules can be tilted in a desired direction by using the cutouts and protrusions. This ensures a relatively wide viewing angle.

Although a liquid crystal display device having a vertical imaging mode provides a wide viewing angle, there is a problem in that its side visibility is deteriorated compared with its front visibility. For example, in a pixel electrode pattern of a vertical alignment type liquid crystal display device provided with cutouts, an image in the side of the liquid crystal display device becomes brighter. In more severe cases, the difference in brightness between high gray levels becomes very small, causing image distortion and narrowing the viewing angle.

Various techniques have been proposed for solving the above-mentioned viewing angle problem, including the following techniques: by dividing one pixel into two pixels, the two subpixels are capacitively coupled, and by directly applying a voltage to one subpixel and due to the capacitive coupling Different voltages are provided to the two sub-pixels by reducing the voltage in the other sub-pixel to provide different transmittances, thereby improving the viewing angle.

However, since the transmittance of the two sub-pixels cannot be precisely adjusted, and because one of the sub-pixels cannot reach the highest Gamma voltage, its brightness will decrease, thereby reducing the contrast and affecting the viewing angle, so the above technology is not as good as in practice. Works in theory. Another problem with this technology is that conductive parts must be added for capacitive coupling, so the aperture ratio will be reduced.

So on the basis of this technology, another technology is proposed: although one pixel is also divided into two sub-pixels, this technology doubles the number of gate lines, and the two sub-pixels use two switching devices to predetermine the pixel electrode voltage. , so that the pixel electrode voltages of the two sub-pixels can be precisely controlled, and a better effect of improving the viewing angle can be achieved. However, since each gate line is driven by an independent gate line driver IC, the number of driver ICs needs to be doubled, which greatly increases the cost.

Contents of the invention

The technical problem to be solved by the present invention is to provide a liquid crystal display device, a pixel structure and a driving method thereof which can obtain a better effect of improving the viewing angle without doubling the gate line driving circuit, thereby not greatly increasing the cost.

The technical solution adopted by the present invention to solve the above technical problems is to provide a pixel structure, including a first scanning line, a second scanning line, a data line, a first thin film transistor, a first pixel electrode, a second thin film transistor, a second The pixel electrode, the third thin film transistor, the charge sharing capacitor and the fourth thin film transistor. The first scan line, the second scan line and the data line, the first to fourth thin film transistors, the first and second pixel electrodes and the charge sharing capacitor are all arranged on the substrate. Wherein, the first thin film transistor is electrically connected to the first scan line and the data line, and the first thin film transistor has a first drain, and the first pixel electrode is electrically connected to the first drain. The second thin film transistor is electrically connected to the first scan line and the data line, and the second thin film transistor has a second drain, and the second pixel electrode is electrically connected to the second drain. The third thin film transistor is electrically connected to the second scan line and the data line, and the third thin film transistor has a third drain, and the charge sharing capacitor is electrically connected to the third drain. One of the source and the drain of the fourth thin film transistor is connected to the second pixel electrode, the other is connected to the charge sharing capacitor, and the gate of the fourth thin film transistor is connected to an auxiliary scanning line. The auxiliary scanning line is the first scanning line of another pixel structure that is driven later in order.

In the above pixel structure, the first thin film transistor and the second thin film transistor are adjacent to the intersection of the first scan line and the data line. In addition, the first thin film transistor and the second thin film transistor have a common source.

In the above pixel structure, the third thin film transistor and the thin film transistor are adjacent to the intersection of the first scan line and the data line.

The present invention also proposes a driving method for driving the above-mentioned pixel structure, the driving method includes: turning on the first thin film transistor and the second thin film transistor through the first scanning line, and applying the first data voltage to the second thin film transistor through the data line A pixel electrode and a second pixel electrode; turn on the third thin film transistor through the second scanning line, so as to apply the second data voltage to the charge sharing capacitor through the data line; turn off the third thin film transistor, and turn on the fourth thin film transistor through the auxiliary scanning line The transistor is used to neutralize the voltage in the charge sharing capacitor and the voltage in the second pixel electrode.

In the above driving method of the pixel structure, the time when the first and second thin film transistors are turned on and the time when the third thin film transistor is turned on may not overlap at all, or may partially overlap.

The present invention also provides a liquid crystal display device, which includes a first scan driver, a second scan driver, a data driver, and a thin film transistor array substrate. Wherein, a plurality of the above-mentioned pixel structures are arranged on the thin film transistor array substrate. The first scan driver provides a first scan drive signal for each pixel of the liquid crystal display device. The second scan driver provides second scan driving signals for each pixel of the liquid crystal display device; the data driver provides data signals for each pixel of the liquid crystal display device. The second scanning lines of at least some of the pixel structures are connected to a common second scanning driving signal.

In the above liquid crystal display device, the pixel structure on the thin film transistor array substrate is divided into multiple regions, and the second scanning lines in each region are connected to a common second scanning driving signal.

The pixel structure and the liquid crystal display device of the present invention do not need to separately configure a driver IC for the second scanning lines in each column of the pixel structure, but can connect the second scanning lines of all the pixel structures together for common driving, so it is different from the existing Compared with the prior art, the present invention can save nearly half of the driving IC at most, thereby saving cost.

Description of drawings

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of a pixel structure according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the pixel structure shown in FIG. 1 .

FIG. 3 is a structural block diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of driving waveforms according to an embodiment of the present invention.

Detailed ways

Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings so that the present invention can be easily put into practice by those skilled in the art. The present invention can be implemented in various forms and is not limited to the exemplary embodiments shown here.

FIG. 1 is a pixel structure diagram of an embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of the pixel structure shown in FIG. 1 . This pixel structure is arranged on the thin film transistor array substrate, which includes a first scan line 101, a data line 102, a second scan line 103, a common electrode line 104, a first thin film transistor TFT1, a second thin film transistor TFT2, a third thin film transistor TFT3, a fourth thin film transistor TFT4, a first pixel electrode Pa, a second pixel electrode Pb, and a charge sharing capacitor C3. The scan lines 101 and 103 extend along a first direction, the data lines 102 extend along a second direction, and the two intersect to define a pixel area. The first pixel electrode Pa and the second pixel electrode Pb are located in the pixel region, wherein the area of the first pixel electrode Pa is, for example, smaller than or equal to the area of the second pixel electrode Pb.

The first thin film transistor TFT1 and the second thin film transistor TFT2 are located near the intersection of the first scan line 101 and the data line 102 . The first thin film transistor TFT1 has a first drain 105a and a gate (not marked), and the second thin film transistor TFT2 has a second drain 105b and a gate (not marked). The first thin film transistor TFT1 and the second thin film transistor TFT2 share the source 105c. Please refer to FIG. 2 , TFT1 and TFT2 are electrically connected to the first scan line 101 and the data line 102 through the source 105c and the gate respectively. The storage capacitor Csta corresponding to the first pixel electrode Pa and the liquid crystal capacitor Clca are combined into a capacitor Cs1, which is electrically connected to the first drain 105a of the TFT1, and the storage capacitor Cstb corresponding to the second pixel electrode Pb and the liquid crystal capacitor Clcb are combined into a capacitor Cs2 , which is electrically connected to the second drain 105b of the TFT2.

The third thin film transistor TFT3 and the second thin film transistor TFT4 are located near the intersection of the second scan line 103 and the data line 102 . The third thin film transistor TFT3 has a third source 106a, a third drain 106b and a gate (not shown). Please refer to FIG. Its gate is electrically connected to the second scan line 103, and the third drain 106b is connected to the charge sharing capacitor C3. The fourth thin film transistor TFT4 has a fourth source 107a, a fourth drain 107b and a gate (not shown), wherein as shown in FIG. The electrode 107b is connected to the second pixel electrode Pb, and the gate of the fourth thin film transistor is connected to the auxiliary scanning line 101a outside the pixel structure.

Specifically, the auxiliary scanning line is the first scanning line of the next row of pixel structures in the next driving order in the thin film transistor array substrate. Referring to Figure 2, the first scan line of this pixel structure is called Gate n, the auxiliary scan line of the next column of pixel structure is called Gate n+1, the second scan line is called TFT3_Open_line, and the data line is called Gate n+1. Source Line. It can be seen from the equivalent circuit of the pixel structure shown in Figure 2 that the first scanning line Gaten is used to open the thin film transistors TFT1 and TFT2, while the second scanning line TFT3_Open_line is dedicated to opening the thin film transistor TFT3, and the auxiliary scanning line Gate n+1 is used in addition to using In addition to turning on the first and second thin film transistors of the next pixel structure, it can also be used to turn on the thin film transistor TFT4.

Please refer to FIG. 3 below, which shows the structure of a liquid crystal display device having the pixel structure of the above-mentioned embodiment of the present invention. The liquid crystal display device includes a liquid crystal display panel assembly 10. As shown in FIG. Arranged in a matrix. In addition, although not shown in the figure, the liquid crystal display panel 10 further includes a color filter substrate opposite to the array substrate 100 , and a liquid crystal layer sandwiched between the two substrates.

There are multiple first scanning lines (such as Gn, Gn+1, Gn+2) for transmitting gate signals on the thin film transistor array substrate 100, a second scanning line TFT_3_OPEN_LINE that functions similarly to the gate lines, and Multiple data lines for transmitting data signals (such as Source Line_m, SourceLine_m+1, Source Line_m+2). The first scanning lines and the second scanning lines extend parallel to each other in the first direction of the substrate, and the data lines extend parallel to each other in the second direction substantially perpendicular to the first direction, so as to form a pixel structure configuration pixel area.

The liquid crystal display device includes a gray scale voltage generator not shown in the figure, which generates two sets of gray scale voltages corresponding to the transmittance of the pixel, and the two gray scale voltages are used to be independently applied to two sub-pixels Pa and Pb of a pixel. A data driver 20 is connected to each data line Source Line of the liquid crystal display panel 10, thereby selects a gray-scale voltage of the two gray-scale voltage sets of the above-mentioned gray-scale voltage generator as a data signal and applies it to the pixel. The data voltage is selected from the gray-scale voltages generated by the gray-scale voltage.

The first scan driver 30 is connected to each of the above-mentioned first scan lines (such as Gn, Gn+1, Gn+2), so as to apply the first scan drive signal formed by the combination of the gate-on voltage and the gate-off voltage. to the first scan line.

The timing controller 40 is connected to the data driver 20 and the first scan driver 30 and plays a role of signal control.

In addition, the liquid crystal display device also includes a second scan driver 50 dedicated to turning on and off the third thin film transistor TFT3 in the above pixel structure, which is connected to the above second scan line TFT_3_OPEN_LINE so that the second scan driver 50 dedicated to turning on and off the TFT3 A scan driving signal is applied to the second scan line.

In order to realize color display, each pixel is uniquely displayed with a specified primary color, and different colors are formed through the combination of different primary colors, and the primary colors usually include red, green and blue.

The display operation of the liquid crystal liquid crystal display is described below. The timing controller 40 receives image signals R, G, and B and input control signals for controlling display from the outside. These image signals represent the brightness information of each pixel, that is, a specific gray scale. Input control signals generally include vertical synchronous and horizontal synchronous signals, and data enable signal DE. After receiving these signals, the timing controller 40 generates gate control signals and data control signals, and transmits them to the first scan driver 30 and the data driver respectively. 20.

The gate control signal (that is, the first scan driving signal) includes a signal for indicating the start of a frame scan and a signal for controlling the turn-on time of the scan line.

The data control signals include a horizontal start signal for indicating data transmission of a row of sub-pixels, a load signal for supplying a charging voltage to the pixels, a data clock signal, a polarity inversion signal, and the like.

In response to a data control signal from the timing controller 40, the data driver 20 receives image data for a group of word pixels, and selects one of the two sets of gray-scale voltages from the gray-scale voltage generator, and selects the image data corresponding to the gray-scale voltage set from the gray-scale voltage generator. The gray scale voltage is applied to the relevant data lines.

A driving method for applying a data voltage to a pixel structure according to an embodiment of the present invention will be described in detail below with reference to FIGS. 2 to 4 . FIG. 4 is a schematic diagram of driving waveforms according to an embodiment of the present invention. For comparison, the voltages of pixels Pa and Pb are shown together with the Data Output waveforms.

As shown in Figures 2 to 4, during the time period when the data voltage Data Output is applied to a pixel row (one of the pixels is shown in Figure 2), firstly in a first period T1, the gate voltage is applied to the scan line Gate_n Turn on the voltage, and apply the gate off voltage to the scanning lines Gate_n+1 and TFT_3_OPEN_LINE, and open TFT 1 and TFT2 at the same time, so that TFT3 and TFT4 are in the closed state. The voltage is simultaneously applied to the first pixel electrode Pa and the second pixel electrode Pb.

Next, in a second period T2, a gate-off voltage is applied to the first scanning lines Gate_n and Gate_n+1, and a gate-opening voltage is applied to the scanning line TFT_3_OPEN_LINE to open TFT3, so that TFT1, TFT2 and TFT4 are in an off state, At this time, the voltage corresponding to the image data in the second gray scale set voltage is applied to the charge sharing capacitor C3.

Afterwards, in a third period, the gate open voltage is applied to the first scan line Gate_n+1, and the gate close voltage is applied to the scan lines Gate_n and TFT_3_OPEN_LINE to open TFT4, so that TFT1, TFT2 and TFT3 are in the closed state , at this time, the charges on the charge sharing capacitor C3 and the capacitor Cs2 of the second pixel electrode Pb are redistributed. After redistribution, the voltage Vb on the second pixel electrode will be different from the voltage Va on the first pixel electrode, as shown in the Data output waveform in FIG. 4 .

The above two grayscale voltage sets represent different Gamma curves, and are respectively applied to two different sub-pixels Pa and Pb of a pixel, so that the Gamma curve of a pixel is a mixture of these two Gamma curves, When determining the two grayscale voltage sets, determine the mixed Gamma curve to make it close to the reference Gamma curve for the front view, so that the mixed side-view Gamma curve can be close to the reference Gamma curve for the front view, so that Further improvements to landscape viewing angles.

The number of scanning lines of this LCD is twice that of ordinary LCDs, resulting in shorter opening time of each scanning line. In order to prolong the charging time of the pixel electrode, the opening time of Gate_n and TFT_3_OPEN_LINE can be partially overlapped, that is, Gate_n is opened at TFT_3_OPEN_LINE Close after a while.

It can be known from the above driving method that the second scan line TFT_3_OPEN_LINE is applicable to all pixels in the liquid crystal panel. Therefore, all TFT_3_OPEN_LINEs in the panel can be connected together to apply the second scanning drive signal (as shown in Figure 3), or can be driven separately; it can be divided into several areas, and the TFT_3_OPEN_LINEs in each area are connected together to apply the scanning drive signal Signal. In this way, compared with the prior art in which each scanning line requires a separate driving IC, the present invention can save nearly half of the gate driving ICs at most, thereby saving costs.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the claims.

Claims (9)

1. A pixel structure, characterized in that it comprises: a first scanning line configured on a substrate; a second scanning line configured on the substrate; a data line configured on the substrate; a first thin film transistor configured on the substrate and electrically connected to the first scan line and the data line, and the first thin film transistor has a first drain; a first pixel electrode configured on the substrate and electrically connected to the first drain; a second thin film transistor configured on the substrate and electrically connected to the first scan line and the data line, and the second thin film transistor has a second drain; a second pixel electrode configured on the substrate and electrically connected to the second drain; a third thin film transistor configured on the substrate and electrically connected to the second scan line and the data line, and the third thin film transistor has a third drain; a charge sharing capacitor configured on the substrate and electrically connected to the third drain; A fourth thin film transistor, configured on the substrate, one of the source and drain of the fourth thin film transistor is connected to the second pixel electrode, and the other is connected to the charge sharing capacitor, and the fourth thin film transistor The gate of the gate is connected to an auxiliary scanning line, and the auxiliary scanning line is the first scanning line of another pixel structure in the driving sequence. 2. The pixel structure according to claim 1, wherein the first thin film transistor and the second thin film transistor are adjacent to intersections of the first scan line and the data line. 3. The pixel structure according to claim 1, wherein the first thin film transistor and the second thin film transistor have a common source. 4. The pixel structure according to claim 1, wherein the third thin film transistor and the fourth thin film transistor are adjacent to intersections of the first scan line and the data line. 5. A driving method for driving the pixel structure according to claim 1, wherein the driving method comprises: turning on the first thin film transistor and the second thin film transistor through the first scan line, and applying a first data voltage to the first pixel electrode and the second pixel electrode through the data line; turning on the third thin film transistor through the second scan line to apply a second data voltage to the charge sharing capacitor through the data line; Turning off the third thin film transistor, and turning on the fourth thin film transistor through the auxiliary scanning line, so that the voltage in the charge sharing capacitor and the voltage in the second pixel electrode are neutralized. 6. The driving method according to claim 5, wherein the time when the first and second thin film transistors are turned on does not overlap with the time when the third thin film transistor is turned on. 7. The driving method according to claim 5, wherein the time when the first and second thin film transistors are turned on partially overlaps with the time when the third thin film transistor is turned on. 8. A liquid crystal display device, characterized in that it comprises: a first scan driver, providing a first scan drive signal for each pixel of the liquid crystal display device; The second scanning driver provides a second scanning driving signal for each pixel of the liquid crystal display device; The data driver provides the data signal of each pixel of the liquid crystal display device; A thin film transistor array substrate, on which a plurality of pixel structures are arranged, wherein each pixel structure includes: a first scan line, configured on the substrate and electrically connected to the first scan driver; a second scanning line, configured on the substrate and electrically connected to the second scanning driver; a data line configured on the substrate; a first thin film transistor configured on the substrate and electrically connected to the first scan line and the data line, and the first thin film transistor has a first drain; a first pixel electrode configured on the substrate and electrically connected to the first drain; a second thin film transistor configured on the substrate and electrically connected to the first scan line and the data line, and the second thin film transistor has a second drain; a second pixel electrode configured on the substrate and electrically connected to the second drain; a third thin film transistor configured on the substrate and electrically connected to the second scan line and the data line, and the third thin film transistor has a third drain; a charge sharing capacitor configured on the substrate and electrically connected to the third drain; A fourth thin film transistor, configured on the substrate, one of the source and drain of the fourth thin film transistor is connected to the second pixel electrode, and the other is connected to the charge sharing capacitor, and the fourth thin film transistor The gate of the drive sequence is connected to the first scan line of another pixel structure; The second scanning lines of at least some of the pixel structures are connected to a common second scanning driving signal. 9. The liquid crystal display device according to claim 8, wherein the pixel structure on the thin film transistor array substrate is divided into a plurality of regions, and the second scanning lines in each region are connected to a common first scanning line. Two scan driving signals.

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