CN100576506C - Design for Manufacturability of Integrated Circuits - Google Patents

Abstract

A manufacturability design method for an integrated circuit, comprising: performing density calculation on an initial design pattern, the density including local density and overall density; extracting the pattern density; adjusting the pattern density to a target pattern density, the target pattern density including local The target pattern density and the overall target pattern density; determine the manufacturability pattern density criterion according to the target pattern density; improve the initial design according to the manufacturability pattern density criterion.

Description

Design for Manufacturability of Integrated Circuits

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturability design method for integrated circuits.

Background technique

The continuous shrinking of integrated circuit (IC) process technology, especially after the 0.13 micron process, the line width of the silicon process is already smaller than the length of the exposure wavelength, making it increasingly difficult to control the stability of the process. It has not been fully considered at the time, that is, the resolution of the process is not enough to accurately convert the geometry designed by the IC engineer to the wafer, making the previous simple design work unacceptable. In this way, it is necessary to repeatedly synthesize and The work of layout and routing, which of course will delay the completion time and cause waste in cost.

The "Design For Manufacturability (DFM)" (Design For Manufacturability, DFM), which aims at the distortion of these geometric figures after the etching process, has become the subject of IC design in the past one or two years. DFM or Design for Yield (DFY), in short, refers to the various effects (Effects) and variations (Variation) that may occur when the process personnel complete the IC from design to manufacturing process and more importantly The influence of IC functions is carefully analyzed and tested, and designers include these information references in the design process, so that the designed ICs have better tolerance to process variations and are more likely to have high yields.

Therefore, in addition to considering logic design issues such as front-end logic synthesis and wiring, the current design engineer must also solve the predictable or unpredictable problems in the actual production process stages such as lithography and etching, that is, Adding the manufacturability test after the traditional design allows the most accurate electrical parameter model to be used in the design to solve the deviation between the actual critical dimension and the original design layout and process defects.

In the actual process, it is very necessary to accurately control the critical dimension and reduce the occurrence of polishing process defects for IC manufacturing. Studies have shown that the critical dimension deviation and the occurrence of polishing process defects obviously depend on the pattern density of each layer pattern. The pattern density is defined as the area ratio of the pattern area to the non-pattern area; therefore, how to control the pattern density of each layer of patterns to improve the manufacturability of the design has become an urgent problem to be solved by those skilled in the art.

The Chinese patent application with the patent number "00806056.8" provides a gate filling method for reducing the pattern density. This method obtains the target pattern density by changing the size of the filling pattern, but does not provide how to obtain the target pattern density when there is no filling pattern Therefore, there is an urgent need for a design method for manufacturability of an integrated circuit that can directly obtain a target pattern density by using the existing pattern density.

Contents of the invention

The invention provides a manufacturability design method of an integrated circuit, which can enhance the manufacturability of products by controlling the design pattern density.

The manufacturability design method of a kind of integrated circuit provided by the present invention comprises:

Carry out density calculation on the initial design graphics, the density includes local density and overall density;

Extract pattern density;

Adjusting the pattern density to a target pattern density, the target pattern density includes a local target pattern density and an overall target pattern density;

determining a manufacturability pattern density criterion according to the target pattern density;

The initial design is improved according to the manufacturability pattern density criteria.

The size range of the specific area to be selected when calculating the local density is 0.25 micron ² to 2500 micron ² ; there are overlapping areas between the adjacent specific areas, and the boundary of any specific area coincides with the center of the adjacent specific area;

The method for adjusting the pattern density to the target pattern density includes:

Partition the initial design graphics by density value;

Predetermine a pattern density;

adjusting pattern density in different partitions to the predetermined pattern density;

Comparing the simulated product characteristic parameters corresponding to the pattern density with the actual product requirements;

If the characteristic parameters of the simulated product meet the requirements of the actual product, the pattern density can be determined as the local target pattern density, and then, the overall density is calculated for the chip with the uniform local target pattern density, and the density value is determined as overall target pattern density;

Otherwise, reserve the next pattern density;

The steps of comparing and judging are repeated until the target graphic density is obtained.

The predetermined pattern density range is 1% to 30%; the simulated product characteristic parameters include optical transmission rate, maximum/minimum local density, maximum/minimum overall density, chip performance parameters, and chip yield statistics;

The method for adjusting the pattern density to a predetermined pattern density includes:

Partitioning the initial design graphics according to the density value, the partitions include a graphic area and a non-graphical area;

A hole is formed in the partition pattern area; the hole is filled with a medium different from the material of the pattern area.

The method for adjusting the pattern density to a predetermined pattern density includes:

Partitioning the initial design graphics according to the density value, the partitions include a graphic area and a non-graphical area;

Make filling graphics in the non-graphic area of the partition.

The manufacturability pattern density criterion is that the local target pattern density is less than 50%, and the overall target pattern density is less than 30%.

A method for determining the manufacturability pattern density criterion provided by the present invention includes:

Partition the initial design graphics by density value;

Predetermine a pattern density;

adjusting pattern density in different partitions to the predetermined pattern density;

Comparing the simulated product characteristic parameters corresponding to the pattern density with the actual product requirements;

If the characteristic parameters of the simulated product meet the requirements of the actual product, the pattern density can be determined as the local target pattern density, and then, the overall density is calculated for the chip with the uniform local target pattern density, and the density value is determined as overall target pattern density;

Otherwise, reserve the next pattern density;

Repeating the steps of comparing and judging to obtain the target pattern density, the target pattern density includes local target pattern density and overall target pattern density;

A manufacturability pattern density criterion is determined according to the target pattern density.

The predetermined pattern density value ranges from 1% to 30%; the simulated product characteristic parameters include optical transmission rate, maximum/minimum local density, maximum/minimum overall density, chip performance parameters, and chip yield statistics.

The method for adjusting the pattern density in different partitions to the predetermined pattern density includes:

Partitioning the initial design graphics according to the density value, the partitions include a graphic area and a non-graphical area;

A hole is formed in the partition pattern area; the hole is filled with a medium different from the material of the pattern area.

The method for adjusting the pattern density in different partitions to the predetermined pattern density includes:

Partitioning the initial design graphics according to the density value, the partitions include a graphic area and a non-graphical area;

Make filling graphics in the non-graphic area of the partition.

A method for changing the existing pattern density to obtain the target pattern density provided by the present invention includes:

Perform density calculations on initial design graphics;

Extract pattern density;

determining a target pattern density, where the target pattern density includes a local target pattern density and an overall target pattern density;

Partitioning the initial design graphics according to the density value, the partitions include a graphic area and a non-graphical area;

Adjust the graphic density in each partition to obtain the local target graphic density;

The overall target pattern density is obtained from the local target pattern density.

The method of adjusting the pattern density in each subregion to obtain the local target pattern density is to form a hole in the pattern area of the partition; the hole is filled with a medium different from the material of the pattern area; the method of adjusting the pattern density in each subregion to obtain the local target The method of graphic density is to make filling graphics in the non-graphic area of the partition.

Compared with the prior art, the present invention has the following advantages:

1. By controlling the density of the design pattern, that is, controlling the local density of the design pattern to be less than 50%, and the overall density to be less than 30%, the occurrence of uneven feature size and grinding defects is reduced, the manufacturability of the product is enhanced, and the production rate is reduced at the same time. cost;

2. By adopting the method of the present invention, by forming holes in the high-density pattern area and filling dummy electrodes in the low-density pattern area, the target pattern density can be directly obtained by utilizing the existing pattern density;

3. By controlling the density of the design pattern, while enhancing the manufacturability of the product, it can shorten the trial production time of new products and reduce the cost of research and development.

Description of drawings

Figure 1 is a schematic diagram illustrating an initial design of an embodiment of the present invention;

FIG. 2 is a schematic diagram illustrating an initial design graphic partition of an embodiment of the present invention;

3A-3B are schematic diagrams illustrating a first pattern density improvement method according to an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating a second pattern density improvement method according to an embodiment of the present invention;

Among them: the same part is marked with the same symbol;

10: initial design graphics; 20: non-graphic area;

30: graphic area; 40: high graphic density area;

50: target pattern density area; 60: low pattern density area;

70: hole; 80: filling medium;

90: fill graphics.

Detailed ways

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

The method of the present invention is applicable to the design of any layer in the integrated circuit manufacturing process, including: gate layer, diffusion layer and metal layer, etc. In order to avoid unnecessary incomprehension, well-known circuits, systems and process operations are not described.

The specific process of adopting the method of the present invention is as follows: firstly, density calculation is performed on the initial design graphics, and the density includes local density and overall density; then, the graphic density is extracted, and then the graphic density is adjusted to the target graphic density, and the target graphic density includes The local target pattern density and the overall target pattern density; then determine the manufacturability pattern density criterion according to the target pattern density; finally, improve the initial design according to the manufacturability pattern density criterion.

Firstly, the initial design is carried out according to the original design requirements, and the density calculation is performed on the initial design graphics.

Fig. 1 is the initial design sketch map illustrating the embodiment of the present invention, as shown in Fig. 1, described initial design figure 10 comprises figure area 30 and non-figure area 20; Described density is figure area 30 and non-figure area in the selected area The area ratio of 20; the selected area can be any area in the die. The term "area" refers to a space or location within a design drawing and is interchangeable with the term "area".

The density includes local density and overall density; the local pattern density is the area ratio of the graphic area and the non-graphic area in a specific area; the overall graphic density is the area ratio of the graphic area and the non-graphic area within the chip range; the The selection of the size of the specific area is related to the process node; as an embodiment of the present invention, the process node is selected as 90 nanometers, and the specific area is a square area; the size range of the specific area is selected as 0.25 micron ² ~ 2500 micron ² ; A specific area can cover any area within the chip.

Admittedly, the selection of the size and shape of the specific area is a special selection made for the convenience of describing the embodiment of the present invention, and should not be regarded as limiting the scope of protection. Any changes made by those skilled in the art should be included in this document. within the scope of the claimed invention.

In order to accurately calculate the local density in any specific area in the chip, it is necessary to sequentially select the specific areas, so that there is an overlapping area between adjacent specific areas, and the boundary of any specific area coincides with the center of the adjacent specific area; thus, Defects in the peripheral circuits of the chip can be avoided. The density calculation can be repeated according to actual needs.

Then, the pattern density is extracted, and the pattern density is adjusted to determine a target pattern density, the target pattern density includes a local target pattern density and an overall target pattern density, and then the manufacturability pattern density criterion is determined.

According to the density calculation result, the graphic density is extracted, and the initial design graphic is divided into multiple areas according to the density value, such as: the density range in the first area is 0-10%, the density range in the second area is 10%-20%, ...and so on to obtain a plurality of initially designed graphic partitions with different density ranges.

Admittedly, the division method of the initial design graphics is a special choice made for the convenience of describing the embodiment of the present invention, and should not be used as a limitation on the scope of protection. Any changes made by those skilled in the art should be included in the scope of the present invention. within the scope of the claimed protection.

In order to determine the target pattern density, and then determine the manufacturability pattern density criterion, it is necessary to first analyze the relationship between pattern density and product characteristic parameters; the characteristic parameters include: optical transmission rate, maximum/minimum local density, maximum/minimum overall density, chip Performance parameters and chip yield statistics, etc.; the characteristic parameters are actual process parameters; the target pattern density can be a specific pattern density or a specific pattern density range; as an embodiment of the present invention, the target pattern density includes a local target pattern Density and overall target graphics density.

The specific method to determine the target graphic density is:

First, a preset pattern density value, such as 10%; then, adjust the pattern density in different initial design pattern partitions, so that the pattern densities in different partitions are all less than the predetermined pattern density value; then, compare the corresponding graphics The simulated product characteristic parameters and actual product requirements in the database of the design graphics of the density value, if the obtained simulated product characteristic parameters meet the actual product requirements, then the graphical density value can be determined as the local target graphical density value, and then, for the The chips with uniform local target pattern density values are used for overall density calculation, and the density value is determined as the overall target pattern density value; otherwise, the next pattern density value is predetermined, such as 20%, and the steps of comparing and judging are repeated until the result is obtained. Output the target graphic density value.

Fig. 2 is the schematic diagram of the partition of the initial design pattern illustrating the embodiment of the present invention. Density graphics area 60 .

Admittedly, the specific selection of the predetermined pattern density value and the specific form of the partition are special selections made for the convenience of describing the embodiment of the present invention, and should not be regarded as limiting the scope of protection, and any changes made by those skilled in the art All should be included in the scope of protection claimed by the present invention.

Combining all kinds of products and the target pattern density values corresponding to different material layer patterns of the same product, determine the manufacturability pattern density criterion.

As an embodiment of the present invention, the manufacturability pattern density criterion is that the local target pattern density is less than 50%, and the overall target pattern density is less than 30%. If the density value in the selected area exceeds the manufacturability pattern density criterion, the initial design does not meet the design manufacturability detection requirements, and the initial design needs to be improved through subsequent steps; if the density value in the selected area If the manufacturability pattern density criterion is met, the initial design meets the design manufacturability testing requirements and can be delivered for production.

3A-3B are schematic diagrams illustrating the first pattern density improvement method of the embodiment of the present invention. For the initially designed high-density pattern partition 40, the specific steps for adjusting the pattern density in the partition are:

As shown in FIG. 3A , a hole 70 is formed in the initially designed pattern area, and the pattern density in the area is reduced by reducing the area of the pattern area in the area and increasing the area of the non-pattern area.

The holes 70 expose the non-pattern area 20; the number, shape and size of the holes are determined according to the manufacturability pattern density criterion. As an embodiment of the present invention, the shape of the hole is selected as square.

Admittedly, the special selection made by the square holes for the convenience of describing the embodiments of the present invention should not be regarded as limiting the scope of protection, and any changes made by those skilled in the art should be included in the scope of protection claimed by the present invention. within range.

Obviously, as shown in Figure 3B, forming a hole 70 in the pattern area, and then filling the hole with a filling medium 80 different from the material of the pattern area, so that the pattern area is connected with other layer pattern areas, is still equivalent to Reduce the area of the graphics area and increase the area of the non-graphics area, thereby achieving the purpose of reducing the graphics density in the selected area.

Fig. 4 is a schematic diagram illustrating the second pattern density improvement method of the embodiment of the present invention. As shown in Fig. 4, for the initially designed low-density pattern partition 60, the specific steps of adjusting the pattern density in the partition are: making a filling pattern in the partition 90, which is equivalent to increasing the area of the graphics area and reducing the area of the non-graphics area, thereby increasing the graphics density in the selected area. The shape and specification of the filling pattern are determined according to design requirements, process nodes and process requirements. As an embodiment of the method of the present invention, the shape of the filling figure may be selected from square, rectangle, cross, T-shape, L-shape and the like.

Admittedly, the square filling figure is a special choice made for the convenience of illustrating the embodiments of the present invention, and should not be used as a limitation on the scope of protection. Any changes made by those skilled in the art should be included in the scope of protection claimed in the present invention. In the range.

It should be noted that the filling pattern in the embodiment of the present invention will not be electrically connected to any active device in the chip. From the perspective of overall pattern density, the exact design of the filling pattern is not critical, but it should have a reasonable Spacing and distribution to meet design requirements and minimize other undesired effects.

Finally, refine the initial design and perform repeated testing.

If the local density is greater than 50% or the overall density is greater than 30%, that is, the initial design does not meet the design manufacturability testing requirements, the initial design needs to be improved through the above steps and repeated testing is performed.

By adopting the method of the present invention, by controlling the density of the design pattern, that is, controlling the local density of the design pattern to be less than 50%, and the overall density to be less than 30%, the generation of uneven characteristic size and grinding defects, etc. are reduced, and the manufacturability of the product is enhanced. Reduced production cost; adopt the method of the present invention, by forming holes in the high-density pattern area, filling dummy electrodes in the low-density pattern area, the existing pattern density can be used to directly obtain the target pattern density; by controlling the design pattern density, in enhancing While improving the manufacturability of the product, it can shorten the trial production time of new products and reduce the cost of research and development.

Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be based on the scope defined by the claims of the present invention.

Claims (17)

1. the manufacturing design method of an integrated circuit is characterized in that, comprising:

The initial designs figure is carried out density calculation, described density comprises local density and global density, described local density is the area ratio of graph area and non-graph area in the specific region, and the border that has overlapping region and arbitrary specific region between adjacent described specific region overlaps with the center of adjacent specific region;

Extract pattern density;

Adjust pattern density to targeted graphical density, described targeted graphical density comprises localized target pattern density and overall goals pattern density, when described pattern density is higher than described targeted graphical density, forms hole in having the graph area of described pattern density; When described pattern density is lower than described targeted graphical density, in having the graph area of described pattern density, fill dummy electrodes;

Determine manufacturability pattern density criterion according to described targeted graphical density;

Improve initial designs according to described manufacturability pattern density criterion.

2. method according to claim 1 is characterized in that: the specific region size range that need choose when calculating local density is 0.25 micron ²～2500 microns ²

3. method according to claim 1 is characterized in that: described adjustment pattern density to the method for targeted graphical density comprises:

The initial designs figure is pressed the density value subregion;

A predetermined pattern density;

Adjust the interior pattern density of different subregions to described predetermined pattern density;

The analog equipment characteristic parameter and the actual product of the described pattern density of correspondence are required to compare;

Judge whether described analog equipment characteristic parameter satisfies the actual product requirement, if then described pattern density can be defined as the localized target pattern density, and then, the chip with described localized target pattern density is carried out global density calculate, described density value is decided to be the overall goals pattern density; Otherwise, predetermined next pattern density;

Repeat described contrast, determining step, until drawing targeted graphical density.

4. method according to claim 3 is characterized in that: described predetermined pattern density range is 1%～30%.

5. method according to claim 3 is characterized in that: described analog equipment characteristic parameter comprises optical transmission speed, maximum/minimum local density, maximum/minimum global density, chip performance parameter and chip yield statistics.

6. method according to claim 3 is characterized in that: the described hole place is full of the medium that differs from the graph area material.

7. method according to claim 1 is characterized in that: described manufacturability pattern density criterion be described localized target pattern density less than 50%, described overall goals pattern density is less than 30%.

8. the method for a definite manufacturability pattern density criterion is characterized in that, comprising:

The initial designs figure is pressed the density value subregion;

A predetermined pattern density;

Adjust the interior pattern density of different subregions to described predetermined pattern density;

The analog equipment characteristic parameter and the actual product of the described pattern density of correspondence are required to compare;

Judge whether described analog equipment characteristic parameter satisfies the actual product requirement, if then described pattern density can be defined as the localized target pattern density, and then, the chip with described localized target pattern density is carried out global density calculate, described density value is decided to be the overall goals pattern density; Otherwise, predetermined next pattern density;

Repeat described contrast, determining step, draw targeted graphical density, described targeted graphical density comprises localized target pattern density and overall goals pattern density;

Determine manufacturability pattern density criterion according to described targeted graphical density.

9. method according to claim 8 is characterized in that: described predetermined pattern density value scope is 1%～30%.

10. method according to claim 8 is characterized in that: described analog equipment characteristic parameter comprises optical transmission speed, maximum/minimum local density, maximum/minimum global density, chip performance parameter and chip yield statistics.

11. method according to claim 8 is characterized in that: the pattern density in the different subregions of described adjustment to the method for described predetermined pattern density comprises:

Described initial designs figure is pressed the density value subregion, and described subregion comprises graph area and non-graph area;

In described subregion graph area, form hole.

12. method according to claim 11 is characterized in that: the described hole place is full of the medium that differs from the graph area material.

13. method according to claim 8 is characterized in that: the pattern density in the different subregions of described adjustment to the method for described predetermined pattern density comprises:

Described initial designs figure is pressed the density value subregion, and described subregion comprises graph area and non-graph area;

In the non-graph area of described subregion, make pattern filling.

14. one kind changes existing pattern density to obtain the method for targeted graphical density, it is characterized in that, comprising:

The initial designs figure is carried out density calculation;

Extract pattern density;

Determine targeted graphical density, described targeted graphical density comprises localized target pattern density and overall goals pattern density;

Described initial designs figure is pressed the density value subregion, and described subregion comprises graph area and non-graph area;

Adjust pattern density acquisition localized target pattern density in each subregion;

Obtain the overall goals pattern density according to the localized target pattern density.

15. method according to claim 14 is characterized in that: pattern density obtains the method for localized target pattern density for to form hole in described subregion graph area in each subregion of described adjustment.

16. method according to claim 15 is characterized in that: the described hole place is full of the medium that differs from the graph area material.

17. method according to claim 14 is characterized in that: pattern density obtains the method for localized target pattern density for to make pattern filling in the non-graph area of described subregion in each subregion of described adjustment.

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