CN100563575C - Meet system in a kind of position emissron tomography and meet method - Google Patents
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Abstract
本发明涉及医学断层成像及核成像领域,特别是一种用于正电子断层扫描设备中符合系统第一组板卡,一个信号缓存单元,第二组接收板卡,一个数据缓存单元,一个参考时钟17,一个时钟调整单元,现场可编程门阵列;方法:利用现场可编程门阵列进行各个事件之间的时间、位置和能量的判断,通过这些判选规则的两个事件成为一个符合事例。通过引入现场可编辑门阵列,采用编写硬件描述语言来快速、高效地处理由PET仪器前端探测器模块捕获到的事例信息,以确定符合事件的发生。本发明是现有PET符合系统处理的改进。本发明使用一片FPGA即可高效、快速地完成符合系统的处理,在获得高的系统灵敏度的同时没有给系统引入死时间。
The invention relates to the fields of medical tomography and nuclear imaging, in particular to a first set of boards, a signal buffer unit, a second set of receiving boards, a data buffer unit, and a reference system used in positron emission tomography equipment. Clock 17, a clock adjustment unit, field programmable gate array; method: use field programmable gate array to judge the time, position and energy between events, and two events that pass these selection rules become a matching case. By introducing field-programmable gate arrays, the hardware description language is used to quickly and efficiently process the event information captured by the front-end detector module of the PET instrument to determine the occurrence of coincident events. The present invention is an improvement over existing PET compliance systems. The invention can efficiently and quickly complete system-compliant processing by using one FPGA, and does not introduce dead time into the system while obtaining high system sensitivity.
Description
技术领域 technical field
本发明涉及医学断层成像及核成像领域,特别是一种用于正电子断层扫描设备(Positron Emission Tomography,PET)中符合系统的设计方法。The invention relates to the fields of medical tomography and nuclear imaging, in particular to a method for designing coincident systems in Positron Emission Tomography (PET) equipment.
背景技术 Background technique
符合探测是正电子发射断层扫描仪(PET)的本质,其设计好坏直接影响整个系统的性能。注入生物体内的放射性药物衰变产生的正电子与生物体内的电子发生湮没反应,产生两个方向相反、能量大小为511keV的γ光子对,如果在一定时间窗内同时被探测器捕捉,则称为探测到一个符合事例。如图1中1表示正电子湮没产生两个能量相等,方向相反的γ光子2a和2b,它们可被两个相对放置的探测器3a,3b探测到。1表示含有18F、22Na、11C等放射性同位素的物质,发生β衰变后产生正电子,与周围的电子发生湮没反应。2a和2b代表正电子湮没后产生的两个能量相等,方向相反飞行的γ光子。3a,3b表示能够探测到γ光子的探测器(在PET中常用闪烁晶体配合位置灵敏的光电倍增管构成,也可以使用其它可探测到γ光子的探测器组合方式。)Coincidence detection is the essence of positron emission tomography (PET), and its design directly affects the performance of the entire system. The positrons produced by the decay of radiopharmaceuticals injected into the living body undergo an annihilation reaction with the electrons in the living body to produce two gamma photon pairs with opposite directions and an energy of 511keV. If they are captured by the detector at the same time within a certain time window, it is called A match was detected. 1 in Fig. 1 indicates that positron annihilation produces two
图2中4a,4b代表图1中的两个γ光子2a,2b分别到达3a,3b两个探测器的时刻t1、t2。如果它们之间的差异小于预先设定的时间窗5,则认为这两个γ光子是由同一个湮没事件产生的,这个过程称为符合探测。4a and 4b in FIG. 2 represent the time t1 and t2 when the two
由于散射以及偶然符合等影响,在探测到时间上符合的事件后,符合系统需要进一步判断这两个光子信号是否由同一个事件产生。为了减少电路部分的系统死时间,PET仪器要求符合系统对这些光子做出快速判断。Due to the effects of scattering and accidental coincidence, after detecting a time coincident event, the coincidence system needs to further judge whether the two photon signals are generated by the same event. In order to reduce the system dead time of the circuit part, the PET instrument requires a compliance system to make a fast judgment on these photons.
传统PET设计中,符合系统电路采用分离器件搭制而成,电路庞杂,不易检测且造价较高;也有一些PET中符合系统电路采用专用集成电路(Application Specific Integrated Circuit,ASIC)制作而成,虽然将符合系统电路大为简化,但造价依然很高,并且制作周期长。In the traditional PET design, the compliance system circuit is made of separate devices, which is complex, difficult to detect, and expensive; there are also some PET compliance system circuits that are made of Application Specific Integrated Circuit (ASIC). The compliance system circuit is greatly simplified, but the cost is still high, and the production cycle is long.
发明内容 Contents of the invention
为了解决现有技术造价高,制作周期长的问题,本发明设计采用FPGA为核心来实现PET符合系统处理,硬件电路实现简单、造价低廉,并且能够快速实现的一种正电子断层扫描中符合系统及设计方法。In order to solve the problems of high cost and long production cycle in the prior art, the present invention adopts FPGA as the core to realize PET coincidence system processing, the hardware circuit is simple to realize, the cost is low, and a kind of coincidence system in positron emission tomography that can be realized quickly and design methods.
为了实现上述目的,本发明一方面,是提供一种正电子断层扫描中符合系统,技术方案包括:In order to achieve the above object, one aspect of the present invention is to provide a coincidence system in positron emission tomography, and the technical solution includes:
第一组板卡,用于接收并处理表示各个探测器组块探测到符合单事例的时间信号;The first group of boards is used to receive and process the time signal indicating that each detector block detects a single case;
一个信号缓存单元,用于暂存并输出第一组板卡的符合单事例的时间信号;A signal buffer unit, which is used to temporarily store and output the time signal conforming to the single case of the first group of boards;
第二组接收板卡,用于接收并处理表示各个单事例位置、能量的数据;The second group of receiving boards is used to receive and process data representing the position and energy of each single instance;
一个数据缓存单元,用于暂存第二组板卡输出的各个单事例位置、能量的数据;A data cache unit, which is used to temporarily store the data of each single instance position and energy output by the second group of boards;
一个参考时钟17,用于为系统提供参考时钟;A
一个时钟调整单元,将输入的参考时钟进行调理,生成与系统参考时钟同相位的时钟信号;A clock adjustment unit, which adjusts the input reference clock to generate a clock signal with the same phase as the system reference clock;
现场可编程门阵列,将接收PET系统中前端所有探测器采集到的表示事例信息的同步数字信号与表示时间的模拟信号,用于对表示事例信息的同步数字信号与表示时间的模拟信号进行符合判选的综合处理;The field programmable gate array will receive the synchronous digital signal representing case information and the analog signal representing time collected by all the detectors in the front end of the PET system, and is used to match the synchronous digital signal representing case information and the analog signal representing time Comprehensive treatment of judgment;
根据优选实施例,所述现场可编程门阵列采用一片或几片现场可编程门阵列,采用硬件描述语言HDL实现核心符合算法。According to a preferred embodiment, the field programmable gate array adopts one or several field programmable gate arrays, and uses hardware description language HDL to realize the core coincidence algorithm.
根据优选实施例,所述芯片包括单片机或具有CPU功能的芯片。According to a preferred embodiment, the chip includes a single-chip microcomputer or a chip with a CPU function.
根据优选实施例,所述硬件描述语言HDL采用Verilog HDL、VHDL或AHDL,用来配置实现现场可编程门阵列的功能。According to a preferred embodiment, the hardware description language HDL adopts Verilog HDL, VHDL or AHDL, and is used for configuring and realizing the function of the field programmable gate array.
为了实现上述目的,本发明另一方面,是提供一种正电子断层扫描中符合方法,技术方案如下:In order to achieve the above object, another aspect of the present invention is to provide a coincident method in positron emission tomography, the technical scheme is as follows:
利用现场可编程门阵列进行各个事件之间的时间、位置和能量的判断,通过这些判选规则的两个事件成为一个符合事例。The field programmable gate array is used to judge the time, position and energy between various events, and two events that pass these selection rules become a coincidence case.
根据优选实施例,符合事例判选步骤如下:According to a preferred embodiment, the matching steps are as follows:
步骤24:开始;Step 24: start;
步骤25:首先将所需的数据载入;Step 25: First load the required data;
步骤26:对载入的这些数据在时间上进行判断,即通过判断两个事件发生时间的差别是否小于所设时间窗:Step 26: Judging the loaded data in terms of time, that is, by judging whether the difference between the occurrence times of two events is smaller than the set time window:
如果有两个单事例在同一个时间窗内,则执行步骤27;如果否,则执行步骤30;If there are two single cases in the same time window, go to
步骤27:进行查表的操作;Step 27: perform table lookup operation;
步骤28:通过步骤27查表来判断这两个单事例是否落在所设视野之内,如果是,则执行步骤29;如果否,则执行步骤30;Step 28: Check the table in
步骤29:将这两个事件进行打包传输;Step 29: package and transmit the two events;
步骤30:然后判断扫描是否结束,以决定是否载入下一周期的数据进行判断,如果是,则执行步骤31;如果否,则执行步骤25;Step 30: Then judge whether the scanning is over, to determine whether to load the data of the next cycle for judgment, if yes, then perform
步骤31:直至结束。Step 31: until the end.
根据优选实施例,所述步骤27查表的操作,根据设定的视野范围预先设定各个位置的符合结果,通过查表直接判断两个事件在位置上是否符合。According to a preferred embodiment, the table look-up operation in
根据优选实施例,在同一片现场可编程门阵列内通过配置相应的延迟,完成延迟符合,具体步骤如下:According to a preferred embodiment, by configuring corresponding delays in the same field programmable gate array, the delay compliance is completed, and the specific steps are as follows:
利用现场可编程门阵列来实现对符合判选单元34a、34b的复用:The field programmable gate array is used to realize the multiplexing of the matching
将输入信号单元32的一路进行符合判选单元34a的符合判选过程;Carrying out one path of the input signal unit 32 to meet the selection process of the
将输入信号单元32的另一路进行相应的延迟单元33,将延迟后的信号通过一个同样的符合判选单元34b的符合判选过程;The other path of the input signal unit 32 is carried out to the corresponding delay unit 33, and the delayed signal is passed through a same coincidence selection process of the
将得到偶然符合的事例单元36和真实事例单元35一起,通过多路开关37,将偶然符合以及真实事例数据38传输出去。The
根据优选实施例,延迟单元33位于现场可编程门阵列外部;或在现场可编程门阵列内部,通过寄存器缓冲的方法实现。According to a preferred embodiment, the delay unit 33 is located outside the FPGA; or inside the FPGA, implemented by means of register buffering.
本发明的目的是提供一种可广泛用于多参数测量系统中符合系统的设计方法,特别是一种用于正电子断层扫描设备(Positron EmissionTomography,PET)中符合系统的设计方法。通过引入现场可编辑门阵列(FPGA),采用编写硬件描述语言(HDL)来快速、高效地处理由PET仪器前端探测器模块捕获到的事例信息,以确定符合事件的发生。本发明是现有PET符合系统处理的改进。本发明使用一片FPGA即可高效、快速地完成符合系统的处理,在获得高的系统灵敏度的同时没有给系统引入死时间。The purpose of the present invention is to provide a design method that can be widely used in a coincidence system in a multi-parameter measurement system, especially a design method for a coincidence system in a positron emission tomography (Positron Emission Tomography, PET) device. By introducing a field-programmable gate array (FPGA), the hardware description language (HDL) is used to quickly and efficiently process the case information captured by the front-end detector module of the PET instrument to determine the occurrence of coincident events. The present invention is an improvement over existing PET compliance systems. The invention can efficiently and quickly complete system-compliant processing by using one FPGA, and does not introduce dead time into the system while obtaining high system sensitivity.
1、本发明流水线的工作方式,每个周期对输入数据进行一次判断,避免符合处理时给系统引入死时间;1. The working method of the assembly line of the present invention is to judge the input data once in each cycle, so as to avoid introducing dead time into the system during processing;
2、本发明的设计中,硬件电路实现简单,所有符合处理均在一块FPGA内部完成,如需修改处理内容只需将重新程序编写的程序再次置入FPGA即可,毋须更改硬件。2. In the design of the present invention, the hardware circuit is simple to implement, and all coincidence processing is completed inside an FPGA. If the processing content needs to be modified, only the reprogrammed program needs to be inserted into the FPGA again, without changing the hardware.
3、本发明设计采用FPGA为核心,实现速度快,并具有在线可编程特点。做相应修改只需改动软件程序,将它们重新下载入FPGA内部即可,可做到在线迅速更改。3. The design of the present invention adopts FPGA as the core, has fast realization speed, and has the feature of online programming. It is only necessary to modify the software programs and re-download them into the FPGA to make corresponding modifications, which can be quickly changed online.
4、本发明设计与传统的符合电路、或ASIC为核心的符合电路相比,成本大为降低。4. The cost of the design of the present invention is greatly reduced compared with the conventional coinciding circuit or the coinciding circuit with ASIC as the core.
5、本发明设计方便、灵活,除PET系统外,可用于核谱学中相关事件多参数符合测量的数据获取系统。5. The present invention is convenient and flexible in design, and besides the PET system, it can also be used in a data acquisition system for multi-parameter coincidence measurement of related events in nuclear spectroscopy.
6、本发明不同于传统的分步式的处理方法,即将几个模块(Modual)的信号先由一个处理器处理,然后再汇总至一个处理器进行最后判断,本发明方法将所有探测器采集到的、表示事例信息的同步数字信号与表示时间的模拟信号,全部进入此符合系统中统一处理。6. The present invention is different from the traditional step-by-step processing method, that is, the signals of several modules (Modual) are first processed by a processor, and then aggregated to a processor for final judgment. The method of the present invention collects all detectors The received synchronous digital signals representing case information and the analog signals representing time all enter this coincidence system for unified processing.
本发明用于核谱学及核电子学的高速并行多道数据获取系统,特别是用于核谱学中相关事件多参数符合测量的数据获取系统。The invention is used in a high-speed parallel multi-channel data acquisition system for nuclear spectroscopy and nuclear electronics, especially a data acquisition system for multi-parameter coincidence measurement of related events in nuclear spectroscopy.
附图说明 Description of drawings
图1现有技术符合探测硬件框图Fig. 1 Existing technology coincidence detection hardware block diagram
图2现有技术符合判选原理示意图Fig. 2 Schematic diagram of the prior art compliance judgment principle
图3是本发明探测器环晶体结构示意图Fig. 3 is a schematic diagram of the crystal structure of the detector ring of the present invention
图4是本发明FOV及位置符合设计图Fig. 4 is the design diagram of FOV and position of the present invention
图5是本发明符合系统硬件结构图Fig. 5 is that the present invention conforms to system hardware structural diagram
图6是本发明符合电路板FPGA内部程序流程图Fig. 6 is that the present invention conforms to circuit board FPGA internal program flowchart
图7是本发明由6个探头组成的探测器环位置符合表格示意图Fig. 7 is a schematic diagram of the position of the detector ring composed of 6 probes according to the table in the present invention
图8是本发明完成偶然符合与真事例判选的功能框图Fig. 8 is a functional block diagram for the present invention to complete occasional coincidence and true case selection
具体实施方式 Detailed ways
下面将结合附图对本发明加以详细说明,应指出的是,所描述的实施例仅旨在便于对本发明的理解,而对其不起任何限定作用。The present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that the described embodiments are only intended to facilitate the understanding of the present invention, rather than limiting it in any way.
根据前端探测器设计,将探测器环上的每个探测器晶体条编号,采用查表的方式来确定是否为真正的响应事件,采用流水线技术处理这些符合判选的任务,这样对每一个时钟周期到来的事件,均可进行符合判选。According to the design of the front-end detector, each detector crystal bar on the detector ring is numbered, and the way of looking up the table is used to determine whether it is a real response event. The events that come in the cycle can be judged according to the requirements.
由图3所示,全部探测器环9由16个模块8(module)组成,每个模块8包含两个组块7(block),每个block则由1.9mm×1.9mm×10mm的条状LYSO晶体6以16×16阵列组成,这样就由8192根LYSO晶体条组成了一个32环、每环256个晶体条的探测器阵列。As shown in Figure 3, the entire detector ring 9 is composed of 16 modules 8 (modules), each module 8 contains two blocks 7 (blocks), and each block is composed of a 1.9mm×1.9mm×10mm
图3表示PET中探测器晶体环9的组成。6表示所用闪烁晶体条,由很多这种闪烁晶体条6按某种排列方式(如16×16,也可以别的数字)组成一个组块7;由两个或多个组块7构成一个模块8,由16个(也可以别的数字)模块8构成了整个PET探测器晶体环9。Figure 3 shows the composition of the detector crystal ring 9 in PET. 6 represents the scintillation crystal strip used, and a block 7 is formed by many such
图4表示由12a~12p多个探测器构成的PET探测器环,根据不同的探测视野(虚线11a、11b)要求进行各个探测器间的符合判断,探测器间的符合探测由响应线10表示。符合系统要求对探测器组块7两两之间判断符合(图1)。Fig. 4 shows a PET detector ring composed of multiple detectors 12a to 12p. According to different detection fields of view (dotted lines 11a, 11b), the coincidence judgment among the detectors is performed, and the coincidence detection among the detectors is represented by the response line 10 . Comply with the system requirements and judge whether two detector blocks 7 are consistent (Fig. 1).
图5表示符合系统硬件板卡22的构成框图,它接收由第一组板卡13a~13z处理后输送过来的表示各个探测器组块7探测到符合单事例的时间信号,并将这些信号放入信号缓存单元15中暂存起来;符合系统硬件板卡22还接收第二组板卡14a~14m处理后送来的表示各个单事例位置、能量的数据,并将它们放入数据缓存单元16中;同时,符合系统工作还需要一个参考时钟17,它可由晶体振荡器等器件、或专门的板卡等产生,这一工作时钟最好经过时钟调理单元18调理后再进行使用;符合系统22工作还需要提供电源19。然后由一片现场可编程门阵列FPGA20(或几片)进行主要的符合判选任务。处理完成后的数据在单片机等具有CPU功能的芯片21的调控下,传入后端计算机23进行进一步的处理。Fig. 5 shows the composition block diagram of conforming to the system hardware board 22, it receives the time signal that each detector block 7 detects conforming to a single case and sends these signals after being processed by the first group of
符合FPGA20内部所用到的程序流程如图6所示,利用现场可编程门阵列进行各个事件之间的时间、位置和能量的判断,通过这些判选规则的两个事件成为一个符合事例。程序从24开始后,首先将所需的数据载入25,然后对这些数据在时间上进行判断26,即通过判断两个事件发生时间的差别是否小于所设时间窗(例如6ns、10ns等),如果有且只有两个单事例在同一个时间窗内,则进行查表27的操作;否则判断扫描是否结束30。通过查表27来判断这两个单事例是否落在所设视野之内28,如果是的话将这两个事件进行打包传输29,然后判断扫描是否结束30,以决定是否载入下一周期的数据进行判断,直至结束31。The program flow used inside FPGA20 is shown in Figure 6. The field programmable gate array is used to judge the time, position and energy between events, and two events that pass these judgment rules become a coincidence case. After the program starts at 24, the required data is first loaded into 25, and then the data is judged 26 in time, that is, by judging whether the difference between the occurrence times of two events is smaller than the set time window (such as 6ns, 10ns, etc.) , if there are and only two single cases in the same time window, the operation of
图7表示图6中查表27的操作,查表的操作是根据设定的视野范围预先设定各个位置的符合结果,通过查表直接判断两个事件在位置上是否符合。Fig. 7 shows the operation of the look-up table 27 in Fig. 6, the operation of the look-up table is to pre-set the matching results of each position according to the set field of view, and directly judge whether the two events match in the position by looking up the table.
以六个探测器组成的环为例说明,根据设定的FOV大小,一个探测器模块需要与其对面的三个模块进行符合判断,在考虑载入数据的先后顺序情况下,则两两符合的判断结果如图7所示。图中‘对’号表示在视野FOV内,‘叉’号表示不在视野内。举例来说,若一个事件被探测器2,另一个被探测器5探测到,查图中表格(2,5)得出此两个事件在位置上符合,属于视野FOV内的有效事件,可以继续图6中的29步骤。采用查表的方法不但简化了操作,而且可以在一个周期内完成,使得整个程序可以顺利地利用流水线进行数据处理,在符合判选阶段没有给整个系统引入死时间。Taking a ring composed of six detectors as an example, according to the set FOV size, a detector module needs to make a coincidence judgment with the three opposite modules. Judgment results are shown in Figure 7. The 'pair' in the figure means it is within the FOV of the field of view, and the 'cross' means it is not in the field of view. For example, if one event is detected by detector 2 and the other is detected by
另外一个需注意的问题是,设计图7中的表时,应以模块为单位来进行,如果按照晶体条来设计的话,表就会很大,以16个模块组成的探测器环为例,每个组块由16×16根晶体条,如果将如此众多的晶体位置符合情况全部放入表中,那么此表矩阵将会是8192×8192,实现起来不是很容易。而如果以模块为单位的话,矩阵将会变为32×32,使用FPGA内部存储资源即可实现,无需外部存储器且速度快。Another problem that needs attention is that when designing the table in Figure 7, it should be carried out in units of modules. If it is designed according to crystal strips, the table will be very large. Take a detector ring composed of 16 modules as an example. Each block consists of 16×16 crystal strips. If so many crystal positions are all put into the table, then the table matrix will be 8192×8192, which is not very easy to realize. And if the module is used as the unit, the matrix will become 32×32, which can be realized by using the internal storage resources of the FPGA, without the need for external memory and at high speed.
此外,本发明中由于主要采用FPGA来实现符合判选,因此可以方便地对其进行复用。图8表示将输入信号单元32一路直接进行上述符合判选单元34a的符合判选过程,另外分出来一路进行相应的延迟单元33,将延迟后的信号通过一个同样的符合判选单元34b的符合判选过程,将得到偶然符合的事例单元36,它同真实事例单元35一起通过一个多路开关37,将偶然符合以及真实事例数据38传输出去。由于延迟单元33可以在外部,也可以在FPGA内部可以通过寄存器缓冲的方法方便实现,因此整个图8功能通过一片FPGA即可完成,此时整个PET系统就可方便的得到偶然符合以及真实事例的数据。大大简化了符合系统硬件实现的复杂程度。In addition, since the FPGA is mainly used to realize the match judgment in the present invention, it can be multiplexed conveniently. Fig. 8 shows that the input signal unit 32 is directly carried out the coincidence judgment process of the above-mentioned
以上所述,仅为本发明中的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉该技术的人在本发明所揭露的技术范围内,可理解想到的变换或替换,都应涵盖在本发明的包含范围之内,因此,本发明的保护范围应该以权利要求书的保护范围为准。The above is only a specific implementation mode in the present invention, but the scope of protection of the present invention is not limited thereto. Anyone familiar with the technology can understand the conceivable transformation or replacement within the technical scope disclosed in the present invention. All should be covered within the scope of the present invention, therefore, the protection scope of the present invention should be based on the protection scope of the claims.
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