CN100565912C - High K Dielectric Film - Google Patents

Abstract

A kind of dielectric layer (14,22,24,32) is made of the lanthanum that forms between two conductors or conductor (14,20,34) and the substrate (12,26,30), lutetium and oxygen.In one embodiment, dielectric layer is formed on the substrate, does not need extra boundary layer.In another embodiment, dielectric layer (22,42,46) changes the content of lanthanum or lutetium gradually, perhaps also comprises the content of aluminium.In another embodiment, insulating barrier is formed between conductor or substrate and the dielectric layer, perhaps is formed between conductor and substrate and the dielectric layer.Dielectric layer is preferably formed by molecular beam epitaxy, but also can be formed by atomic layer chemical vapour deposition, physical vapor deposition, MOCVD or pulsed laser deposition.

Description

High K Dielectric Film

technical field

The present invention relates to apparatus and methods for fabricating integrated circuits, and more particularly, to high-k dielectrics for fabricating integrated circuits.

Background technique

的SiO₂导致不可接受的漏电流以及降低的装置性能。因此，需要在CMOS器件中替换SiO₂。通过使较厚的高K层具有降低的等效(SiO₂)氧化物厚度，可以减小漏电流。CMOS devices include n-channel and p-channel field effect transistors (FETs) and form the substrate of integrated circuits. These transistors are metal oxide based semiconductor devices that include source and drain regions with an insulated gate therebetween. As the density and performance of integrated circuits increase, the size of transistors must decrease. As a result, the thickness of the insulating gate dielectric layer must be made smaller. As for the gate dielectric, a desirable property of the dielectric layer is that it couples the upper gate electrode to the underlying channel so that the channel can respond to stimuli applied to the gate. In this sense, it is desirable for the dielectric to have a high dielectric constant, also known as high K. Silicon dioxide has been by far the most commonly used and effective gate insulator in the manufacture of integrated circuits. This has a very high level of integration and, in particular, can be manufactured with a very low defect density. As a result, silicon dioxide operates very efficiently, allowing these devices to have low leakage currents. Unfortunately, as the thickness of the gate dielectric decreases, the leakage current increases greatly. For example, thickness less than 20

SiO ₂ leads to unacceptable leakage current and degraded device performance. Therefore, there is a need to replace _SiO2 in CMOS devices. By having a thicker high-K layer with a reduced equivalent ( _SiO2 ) oxide thickness, leakage current can be reduced.

One of the properties that are desirable for a high-k dielectric is that it is amorphous. It must remain amorphous throughout its useful life, including during fabrication and subsequent functional operation as part of the finished integrated circuit. Many alternative high-K dielectrics have sufficiently high K and sufficient integration when deposited, but after subsequent processing steps and the heating associated therewith, the result is that these films crystallize. These films so crystallized are not ideally crystallized across their entire length and width, but instead have regions called grain boundaries between the crystal structures that form. These grain boundaries are areas where leakage and other problems affecting electrical performance occur.

Currently, many efforts are being made to develop high-K dielectrics with higher dielectric constants than silicon dioxide. There are many such high-k dielectrics, but one advantage of silicon dioxide is that it has a high band gap and low interface state density with silicon, making it a very effective insulator. Consequently, many materials developed for high-K purposes have been found to be problematic because they do not have a sufficiently high bandgap, or because they are difficult to fabricate with sufficient integration to prevent leakage current through the dielectric. There are also some unresolved issues, such as thermal stability of the silicon substrate and gate electrode, Fermi level pinning at the oxide/metal interface, and scaling down. Even though amorphous materials including Hr-based and Zr-based oxides are being investigated, there is still no clear solution due to unresolved issues with these materials when integrated into a CMOS process flow. Additionally, these materials recrystallize during the high-temperature steps of the manufacturing process. La-based oxide materials may be able to be used as high-K dielectrics for Si CMOS devices. This oxide has a higher dielectric constant than _SiO2 and is expected to be thermodynamically stable in contact with silicon.

An alternative to amorphous are single crystal films. In theory, high-K dielectric films can usually be made of single crystals, although there are some difficulties. One of the difficulties is matching the crystal structure of the film to that of the underlying semiconductor, typically silicon, and during the forming process, which is actually extremely well formed. Epitaxial layers are well known in the art, and these epitaxial layers are layers composed of single crystals. Silicon can be produced epitaxially. One of the techniques for placing very thin films into single crystal form is molecular beam epitaxy. Even with MBE technology, it is still difficult to ensure a defect-free film.

Another potential problem in developing new high-K dielectrics is having a dielectric constant that is too high. If the dielectric constant is too high, an effect known as the fringe field effect occurs, which adversely affects the performance of the transistor. This must be overcoupled between gate and source/drain. Therefore, it is desirable that the materials being developed have a dielectric constant range of typically between 20 and 40. The range is subject to some changes as the technology advances further.

Another aspect of an ideal high-k dielectric concerns its equivalent capacitance to a certain thickness of silicon oxide. Silicon oxide has been used so commonly and effectively that it has become a standard, and the industry often refers to a relationship with silicon oxide to describe certain properties. In this case, a typical ideal silicon oxide equivalent thickness is between 5 and 15 angstroms, but 5 to 15 angstroms silicon oxide has problems with leakage, reliability, growth rate, and uniformity. Therefore, when the film is so small, there are difficulties in manufacture and use. Ideally for coupling, the dielectric has a silicon oxide equivalent thickness of 5 to 15 Angstroms, but actual thicknesses are higher.

High-K dielectric films containing aluminum have been developed, however, aluminum is known to lead to high interface state density and reduced mobility in silicon-based devices.

Therefore, there is a need for a dielectric film that has a dielectric constant within a desirable range, can be fabricated at high levels of integration, has a thickness within a desirable range, does not reduce mobility or result in high interface state density, and can be fabricated in a certain Manufacturing process manufacturing.

Contents of the invention

To achieve the foregoing and other objects and advantages, a semiconductor structure and method of constructing the semiconductor structure are disclosed, the method comprising: providing a semiconductor substrate; providing a dielectric layer comprising lanthanum, lutetium, and oxygen over the semiconductor substrate; And an electrode layer is provided over the dielectric layer.

Description of drawings

Through the following detailed description in conjunction with the preferred embodiments of the accompanying drawings, those skilled in the art will easily understand the aforementioned and other further specific purposes and advantages of the present invention:

1 is a cross-sectional view of a part of an integrated circuit according to a first embodiment of the present invention;

2 is a cross-sectional view of a portion of an integrated circuit according to a second embodiment of the invention;

3 is a cross-sectional view of a part of an integrated circuit according to a third embodiment of the present invention;

4 is a cross-sectional view of a part of an integrated circuit according to a fourth embodiment of the present invention;

5 is a cross-sectional view of a part of an integrated circuit according to a fifth embodiment of the present invention;

6 is a cross-sectional view of a part of an integrated circuit according to a sixth embodiment of the present invention;

LaLuO₃层的透射电子显微照片；FIG. 7 is a 50 Å deposited on silicon according to the invention after annealing at 700 degrees Celsius.

Transmission electron micrograph of LaLuO ₃ layer;

Figure 8 shows the Rutherford backscattering spectrum of 5OA of a layer of _LaLuO3 deposited on silicon at 200 degrees Celsius according to the present invention; and

LaLuO₃层的C-V曲线。Figure 9 graphically shows the 50

CV curves of LaLuO ₃ layers.

Detailed ways

The following detailed description is an exemplary embodiment only and is not intended to limit the invention or limit the application and uses of the invention. Rather, the following description provides a suitable illustration of exemplary embodiments for implementing the invention. Various changes to the described embodiments may be made in the function and structure of the components described without departing from the scope of the invention as set forth in the appended claims. A high-K dielectric film comprising lanthanum, lutetium, and oxygen provides a superior candidate to replace silicon dioxide. It combines the advantages of having a desirable range of dielectric constants, being able to remain amorphous at high temperatures, and having low leakage.

As shown in FIG. 1 , a portion 10 of an integrated circuit is shown having a substrate 12 of semiconductor material, a dielectric film 14 and a conductive film 16 . The substrate 12 has semiconductor regions at least on its surface. The lower portion, not shown, may also be a semiconductor material or may be an insulating material generally used for SOI. Examples of semiconductor materials include single crystal silicon and gallium arsenide. Overlying substrate 12 is dielectric layer 14 . Overlying the dielectric layer 14 is a conductive film 16, which acts as a gate electrode. The dielectric layer 14 acts as a gate insulator or gate dielectric. The region of substrate 12 shown here near the surface at the interface with dielectric film 14 is the channel of the transistor.

Gate dielectric 14 includes lanthanum-lutetium oxide, which is a compound that includes lanthanum, lutetium, and oxygen. The chemical formula is LaLuO ₃ , where lanthanum and lutetium are present in the same concentration. In the case where aluminum is added to the dielectric compound (presently discussed), the formula is La(Al) _x Lu _1-x O ₃ , where x>0. Lanthanum-lutetium oxide is disclosed as having a dielectric constant of about 25, and a bandgap greater than 5 eV. As a result, the successful deposition of lanthanum-lutetium oxide on the substrate 14, such as a silicon substrate, makes this material suitable for gate dielectric applications.

The gate dielectric 14 disclosed herein is preferably formed by molecular beam epitaxy (MBE), in which various elements are evaporated from a heat source. Additionally, elements can be produced using electron beam deposition, atomic layer chemical vapor deposition (ALCVD), physical vapor deposition, metalorganic chemical vapor deposition, and pulsed laser deposition. The preferred method is MBE, which allows precise control over layer formation, including thickness, which in this case is not less than about 15 angstroms, preferably in the range of 20 to 100 angstroms. Gate conductor 16 is typically polysilicon in current integrated circuit technology, but could be other conductors such as metals including, but not limited to, tungsten, titanium nitride, tantalum nitride, or any conductor that can be used as a gate conductor.

The gate dielectric 14 deposited by MBE is also useful in ensuring that the film is deposited under amorphous conditions. Using current MBE techniques, the surface of the substrate 12 is initially cleaned so that it is free of a native silicon oxide layer, or a thin layer of silicon oxide or silicon oxynitride (currently discussed) may be present. This disclosure contemplates that prior to depositing the lanthanum-lutetium oxide, the surface of the substrate 12 is cleaned and heated to remove impurities, thereby reducing process steps by maintaining the silicon substrate and silicon oxide interface. According to regulations, the native oxide can also be thermally removed prior to the deposition of the lanthanum-lutetium oxide by heating under UHV conditions or by using a Si-assisted desorption process or an Sr-assisted desorption process. In this example, cleaning the surface (after removing the low-K material) increases the capacitance of the dielectric stack and increases the ability to scale the device to smaller dimensions. In another alternative embodiment, it is contemplated that the native oxide may be removed prior to depositing the lanthanum-lutetium oxide, the oxygen and nitrogen treated surface forming silicon oxynitride on the surface of the substrate 12 . Forming silicon oxynitride on the surface provides an interface between the substrate and gate dielectric 14, wherein the interface has a higher dielectric constant than the interface with _SiO2 .

During the MBE process for depositing lanthanum-lutetium oxide, using a nozzle or a plasma source, oxygen molecules are controllably introduced into a reaction chamber where reactive oxygen species can be used. The introduction of lanthanum and lutetium together with oxygen thus forms a monolayer of lanthanum-lutetium oxide as dielectric layer 14 , which is located above substrate 12 .

The lanthanum-lutetium oxide favors low leakage and high capacitance in the region of optimized dielectric coefficient. Some other materials have identifiable defects. For example, a binary compound of lanthanum oxide has a dielectric constant in the proper range, but it absorbs water. Water absorption is very detrimental to ideal IC fabrication. For example, water absorption by lanthanum oxide can cause structural integrity problems, making it unusable for forming integrated circuit structures. The introduction of lutetium can provide a very stable gate dielectric that remains amorphous and does not recrystallize at high temperatures, thus remaining stable when in contact with the substrate 12 . In addition, a high bandgap above 5eV with a reasonable band shift, a dielectric constant of about 25, and a thermal expansion coefficient similar to silicon can be obtained using lanthanum-lutetium oxide.

Another benefit of lanthanum-lutetium oxide is that the dielectric constant can vary based on the range of lanthanum content and lutetium content. Therefore, an optimum dielectric constant of about 10 to 25 can be obtained. Even somewhat larger coefficients can be obtained when the lanthanum content is varied relative to the lutetium content, but this leads to problems related to water absorption. Furthermore, the disclosure contemplates the inclusion of aluminum or nitrogen in the dielectric layer 14, thereby increasing the stability of the dielectric layer, defect passivation, and possibly increasing the dielectric constant.

The lanthanum-lutetium oxide advantageously remains amorphous even at temperatures as high as 1025°C or higher. 1025 degrees Celsius is usually the highest temperature in current manufacturing processes. Consequently, lanthanum-lutetium oxide has been found to be able to withstand the highest temperatures it will receive in integrated circuit processing, which consists of many typical processes, to obtain state-of-the-art geometries, and to remain amorphous. It is generally expected that the maximum process temperature will be lowered somewhat, but the maximum temperature will still likely remain quite high because dopant activation in the source/drain requires high temperatures and such activation will still be required for the foreseeable future. The maximum temperature can be reduced to slightly below 1025 degrees Celsius, but still above 900 degrees Celsius for at least a considerable period of time. However, it is not certain that the temperature will drop significantly, and 1025 degrees Celsius is still a valid requirement for quite some time. Therefore, the amorphous lanthanum-lutetium oxide achieves desirable high-K characteristics and high integration over the expected temperature range.

Another benefit of being able to deposit efficient high-K dielectric films of amorphous lanthanum-lutetium oxide is that it can be very effective not only on silicon but also on gallium arsenide. One of the problems in effectively implementing GaAs CMOS technology to take advantage of its higher mobility benefits is that the gate dielectric used in GaAs is very difficult to match the integration of the gate dielectric of silicon, which is obtained by growing silicon oxide at high temperature. And realize. Therefore, silicon has proven superior to gallium arsenide for most applications. Now with the efficient high-k dielectric deposited using MEB, the result is that the gate dielectric can have a high degree of integration whether deposited on silicon, gallium arsenide or some other semiconductor material. Gallium arsenide may thus become the preferred choice for most integrated circuits, but it is currently only the tip of the iceberg in the semiconductor market.

As shown in FIG. 2 , a portion 18 of an integrated circuit includes a substrate 20 , blocking dielectric 22 , high-K dielectric 24 and conductor 26 . In this case, high-K dielectric 24 is similar or similar to film 14 in FIG. 1 in that it is lanthanum-lutetium oxide. Conductor 26 is similar to conductor 16 and substrate 20 is similar to substrate 12 in FIG. 1 with one of a clean surface, residual native oxide on the surface, or oxynitride present on the surface, as previously described. The blocking dielectric 22, which may also be referred to as an interfacial layer, was chosen as an insulator because of its desirable properties. For example, this can be lanthanum oxide, lutetium oxide, silicon oxide or silicon oxynitride. The presence of blocking dielectric 22 can ensure that the combination of high-K dielectric 24 and blocking dielectric 22 has sufficient insulating properties to prevent unwanted current flow. For example, the combination may have a high bandgap and may have a sufficiently high dielectric constant. In particular, this places a high bandgap material in direct contact with the substrate 20, which is a potential source of electron injection. Another potential use of blocking dielectric 22 is as a diffusion barrier region if the material chosen for substrate 20 is problematic or reactive with lanthanum-lutetium oxide.

As shown in FIG. 3 , a portion 28 of an integrated circuit including a substrate 30 , a dielectric film 32 and a conductor 34 is shown. In this case, substrate 30 is similar to substrates 20 and 12 and conductor 34 is similar to conductors 26 and 16 . Dielectric film 32 replaces dielectric 14 and the combination of dielectrics 22 and 24 . In this case, the dielectric film 32 has a graded concentration of lanthanum or lutetium, which means that the binary material, namely lanthanum oxide or lutetium oxide, is formed close to the interface of the substrate 30 and the dielectric film 32, And it gradually becomes a ternary material, that is, lanthanum-lutetium oxide, which is formed as a layer bordering the conductor 24 by adding lanthanum or lutetium. In the dielectric film 32, near the interface with the substrate 30, the material is substantially pure lanthanum oxide or lutetium oxide. During the movement towards the conductor 34, the concentration of lutetium increases continuously with the deposition of lanthanum oxide near the interface with the substrate 30 until the lanthanum and lutetium in the dielectric film 32 near the interface with the conductor 34 The ratio between them is 1:1. The advantage of this method is that a desired high bandgap is obtained closest to the substrate 30 and avoids any abrupt interface between lanthanum oxide or lutetium oxide and lanthanum lutetium oxide. The resulting permittivity can also be tuned by controlling the rate of concentration increase, ie a 1:1 ratio between lanthanum and lutetium can be achieved well before interfacing with conductor 34 . An alternative is to continue the gradual change, by more than a 1 to 1 ratio, so that the concentration of lanthanum exceeds the concentration of lutetium and vice versa.

As shown in FIG. 4 , a portion 36 of an integrated circuit is shown that includes substrate 40 , blocking dielectric 42 , high-K dielectric 44 , blocking dielectric 46 , and conductor 48 . In this case, substrate 40 is similar to substrates 12 , 20 and 30 . Blocking dielectric 42 is similar to blocking dielectric 22 . High-K dielectric 44 is similar to high-K dielectrics 14 and 24 . Conductor 48 is similar to conductors 16 , 26 and 34 . Barrier layer 46 provides a barrier between high-K dielectric 44 and conductor 48 . Barrier 46 is used where there are compatibility issues between conductor 48 and high-K dielectric 44 . The barrier 46 is also likely to be chosen from lanthanum oxide, lutetium oxide, silicon oxide and silicon oxynitride. The purpose of blocking dielectric 46 is to provide a diffusion barrier region between conductor 48 and high-K dielectric 44 . Of course, it is desirable for the barrier layer 46 to have a high dielectric constant, but the purpose is to prevent problems between the conductor 48 and the high-K dielectric 44 . Preferred choices are likely to be lanthanum oxide or lutetium oxide, since they have a higher dielectric constant than silicon oxide.

As shown in FIG. 5 , a portion 50 of an integrated circuit is shown that includes a conductor 52 , a high-K dielectric 54 , and a conductor 56 . In this case, a high-K dielectric is applied between the two conductors. This mainly occurs when the conductor 52 is a floating gate for storing charge. It can also occur where 52 and 56 include capacitive plates for storing charge. One such example is a memory cell of a dynamic random access memory. In this case, it is also desirable that the high-K dielectric 54 have a high dielectric constant and have the desirable characteristic of low leakage.

As shown in FIG. 5, the high-K dielectric 54 is a lanthanum-lutetium oxide having a graded concentration. The concentration of lanthanum is greatest in the middle and at the interface with conductor 52 and conductor 56 is pure or nearly pure lutetium oxide. This provides a relatively high dielectric constant and high bandgap at the interface with conductor 52 and conductor 56, making it both a high-K dielectric and an excellent insulator. By grading the high-K dielectric 54, a sharp interface between insulator types is avoided. Jumps between material types are often where charges can be trapped. With gradual changes in concentration, abrupt interfaces are avoided. In the case of transistors it is very important to have a high bandgap only close to the substrate because that is where charge injection is possible, whereas in the case of part 50 charge can be injected from conductor 52 or conductor 56 . Therefore, it is desirable to have a high bandgap at the interface with conductor 52 and conductor 56 . It should be understood that the present disclosure contemplates a reverse material stack, that is, where the concentration of lanthanum is greatest in the middle, with pure or nearly pure lutetium oxide at the interface with conductor 56 and conductor 52 .

As shown in FIG. 6 , a portion 60 of an integrated circuit is shown that includes conductor 62 , blocking dielectric 64 , high-K dielectric 66 , blocking dielectric 68 , and conductor 70 . This is a structure similar to that of FIG. 5 . Conductor 62 is similar to conductor 52 , conductor 70 is similar to conductor 56 , and the combination of layers 64 , 66 and 68 is similar to high-K dielectric 54 in FIG. 5 . In the case of FIG. 6 , both dielectric layers 64 and 68 serve to provide a high bandgap and act as a diffusion barrier region between conductors 62 and 70 and high-K dielectric 66 . Therefore, the addition of barrier layers 64 and 68 is necessary to obtain sufficient insulating quality and to provide a diffusion barrier region for high-K dielectric 66 . Conductors 62 and 70 may have different properties. One can be polysilicon. The other could be a metal, in which case the type of blocking dielectric is desirably different. High-K dielectric 66 includes lanthanum-lutetium oxide, which has the benefits described for lanthanum-lutetium oxide used for films in the structures of FIGS. 1-5.

The likelihood that a barrier would be required in the case of two conductors other than the formation of a transistor increases because, in fact, it is suitable for implantation between conductors 62 and 70 in some cases. Therefore, the possibility of requiring barriers 64 and 68 or a gradual change as in FIG. 5 is more likely to be a practical occurrence, wherein the above-mentioned need for barriers 64 and 68 or a gradual change as in FIG. When it happens it doesn't happen. Therefore, the need for barriers 64 and 68 or the possibility of gradation as in FIG. 5 is greater in the case of charge storage by injection. And, in the case where it acts purely as a capacitor, barrier layers 64 and 68 are still more likely to be needed. The main purpose of a capacitor is to store charge, so having a high bandgap at the interface with a conductor is even more important than a transistor.

The following example illustrates a method for constructing a semiconductor structure such as structure 10 shown in FIG. 1 in accordance with one embodiment of the present invention. The method begins by providing a single crystal semiconductor substrate comprising a material selected from Group IV or Groups III-V of the Periodic Table of the Elements. According to a preferred embodiment of the invention, the semiconductor substrate is a silicon wafer with a (100) orientation. At least a portion of the semiconductor substrate has an exposed surface, while other portions of the substrate described below may include other structures. The term "bare" herein means that the surface in that portion of the substrate has been cleaned to remove any oxides, impurities or other foreign material. Bare silicon is known to be highly reactive and tends to form a native oxide. The term "bare" includes within its meaning such a native oxide. The following process is preferably performed by molecular beam epitaxy (MBE), but other deposition processes such as physical vapor deposition, atomic layer deposition or metalorganic chemical vapor deposition may also be used according to the invention. The native oxide is removed by heating the substrate to a temperature above 800 degrees Celsius in an MBE chamber. Cleaned silicon surfaces show (2x1) surface reconstructions as monitored by reflection high energy electron diffraction (RHEED). In another embodiment, by depositing thin layers (preferably 1-3 monolayers) of strontium, barium, a combination of strontium and barium, or other alkaline earth metals or combinations of alkaline earth metals in an MBE apparatus and heating them to Temperatures in excess of 750 degrees Celsius remove this native oxide.

Immediately after the appearance of this pronounced (2x1) surface reconstruction, the temperature of the substrate is lowered to between room temperature and 500 degrees Celsius, preferably between 50 and 400 degrees Celsius. Oxygen is then introduced into the MBE chamber, directed towards the substrate being cleaned. Simultaneously, the valve on the eruption source is opened, so that atoms of lanthanum and lutetium impinge on the semiconductor substrate, forming a layer 14 of lanthanum-lutetium oxide. In another embodiment, aluminum can be introduced to form the lanthanum aluminum lutetium oxide layer. Layer 14 is then deposited to the desired thickness and the gate electrode is deposited by physical vapor deposition or other deposition techniques known in the art.

厚的LaLuO₃层的透射电子显微照片80。如图所示，在构建该介电层之后，淀积TaN层并将其在700摄氏度退火。在该介电层和该衬底之间的界面极其平整，并且出现薄的界面层。将该层加热到900摄氏度不会引发任何的再结晶。As shown in Figure 7, a 50

Transmission electron micrograph of a thick LaLuO3 _layer80 . As shown, after building up the dielectric layer, a TaN layer is deposited and annealed at 700 degrees Celsius. The interface between the dielectric layer and the substrate is extremely smooth and a thin interfacial layer occurs. Heating the layer to 900 degrees Celsius did not induce any recrystallization.

Figure 8 shows the RBS spectrum 90 of a _LaLuO3 dielectric layer deposited on silicon, showing the presence of lanthanum and lutetium. Spectroscopy analysis showed that the ratio of lanthanum to lutetium was close to 1:1. The electrical properties of this oxide layer were determined by constructing a capacitor and measuring the capacitance with reference to the applied voltage. Figure 9 shows a capacitance-voltage curve 100 for a capacitor constructed with a _LaLuO3 dielectric layer on silicon, showing good performance characteristics.

According to another embodiment of the invention, in the structure 10 of FIG. 1 , the silicon substrate may be covered with a thermally grown silicon dioxide layer (not shown). Alternatively, the surface of the silicon may be covered with a silicon oxynitride layer. The silica can be prepared using chemical methods that leave no more than 10 angstroms of oxide. Alternatively, the silicon substrate can be cleaned in situ as in the above case, to leave a clean, well-reconstructed surface. The surface is then exposed to a flow of oxygen in the form of molecular oxygen, reactive oxygen species generated in the plasma source, or ozone. The exposure conditions can be controlled to obtain a desired thickness range of silicon dioxide of 1 to 15 Angstroms, preferably 3-8 Angstroms. In another embodiment, the cleaned silicon surface may be exposed to a flow of oxygen and nitrogen to form a silicon oxynitride layer. Nitrogen can be applied in gaseous form, including nitrous oxide or reactive nitrogen generated in ion sources. After the interfacial layer of silicon dioxide or silicon oxynitride is prepared, a high-K dielectric layer can be deposited.

According to another embodiment of the present _invention , the high-K dielectric may be in the form of La(Al) _{xLu1 - xO3Ny} , where y>0. This can be accomplished by depositing a high-K dielectric layer in the presence of nitrogen as described above. Nitrogen incorporation into high-K dielectric films can potentially increase thermal stability and reduce trap density.

While the invention has been described in a number of embodiments, there are other embodiments and other materials that may be utilized in conjunction that will provide benefits or some benefits related to the present invention. Other materials than those described above may be used. Additionally, materials may be added to the lanthanum-lutetium oxide that may provide additional benefits beyond those provided by the lanthanum-lutetium oxide in combination and the various concentrations described. Accordingly, the scope of the present invention is defined by the appended claims.

Claims (4)

1. semiconductor structure comprises:

Semiconductor substrate;

Dielectric layer above the Semiconductor substrate, it comprises lanthanum, lutetium and oxygen, wherein dielectric layer also comprises aluminium and has chemical formula La (Al) _xLu _1-xO ₃, x＞0 wherein; And

Electrode layer above the dielectric layer.

2. semiconductor structure as claimed in claim 1, wherein, dielectric layer is an amorphism.

3. method that is used to form semiconductor structure comprises:

Form Semiconductor substrate;

Form dielectric layer on Semiconductor substrate, it comprises lanthanum, lutetium and oxygen, and wherein dielectric layer also comprises aluminium and has chemical formula La (Al) _xLu _1-xO ₃, x＞0 wherein; And

On dielectric layer, form electrode layer.

4. semiconductor equipment comprises:

As first material of substrate, this substrate has semiconductor surface and conductive layer;

Second material, described second material are the layers of conduction;

The 3rd material, it is arranged between first and second materials and comprises lanthanum, lutetium and oxygen, and wherein said the 3rd material is an amorphism, and wherein said the 3rd material also comprises aluminium and has chemical formula La (Al) _xLu _1-xO ₃, x＞0 wherein.

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