CN100550613C - Differential Input Limiting Amplifier - Google Patents

Abstract

Difference input range-limiting amplifier is made up of two amplitude limiter circuits, two resistance pressure-dividing networks, two current lens array and operational amplifier, differential input signal P1 links to each other with second resistance pressure-dividing network with first resistance pressure-dividing network respectively with P2, and reference input voltage Vref links to each other with first resistance pressure-dividing network; The output of second current lens array links to each other with the input of first current lens array, the input of first amplitude limiter circuit and the input of second amplitude limiter circuit respectively; First limit circuit output end links to each other with the input of first current lens array with second resistance pressure-dividing network respectively; Second limit circuit output end links to each other with the input of first current lens array with first resistance pressure-dividing network respectively; The output of first resistance pressure-dividing network links to each other with the input of first amplitude limiter circuit and operational amplifier respectively; The output of second resistance pressure-dividing network links to each other with the input of second amplitude limiter circuit and operational amplifier respectively; Operational amplifier output final result Vout.

Description

Differential Input Limiting Amplifier

technical field

The invention relates to a differential input limiting amplifier, which can realize better limiting of the input signal in the limiting region and good linear amplification in the amplifying region.

Background technique

In recent years, with the rapid development of telecommunication network, computer network and INTERNET network, the wide application of multimedia communication, and the large-scale construction of information highway, the requirements for high-speed communication system are getting higher and higher. Differential input limiting amplifiers are widely used in satellite communication, radar system, optical fiber communication and other systems. A limiting amplifier serves several purposes: first, it can serve as the main amplifier for a receiver; second, it can be used in clock recovery circuits in conjunction with passive filters to limit the amplitude of the clock signal detected from the data input; and It can also be used to shape data and clock signals in input and output buffers.

There are many studies on limiting amplifiers abroad, and there are various types of limiting amplifiers. They can be divided into CMOS structure, BICMOS structure, SIGE structure and SI_POLAR structure in terms of technology; they can be divided into high gain and low power consumption in terms of performance. And high-speed limiting amplifiers, etc. The structure of the limiting amplifier studied at home and abroad is relatively similar, generally including four parts: input buffer stage, second to fourth stage differential amplifier unit, output buffer stage and a pair of global DC negative feedback network, and the input signal is amplified in the last stage The output terminal of the unit reaches the limiting state to realize the function of limiting; the input buffer stage realizes impedance matching and level shifting, and the output buffer stage realizes impedance matching and provides sufficient driving capability; the global DC negative feedback network is used to stabilize the operating point and DC gain. This structure has its advantages, such as suppression of noise, large gain, good matching, etc., but the structure of this limiting amplifier is more complicated, and the amplitude of limiting is not easy to adjust, and the limiting amplifier of the present invention not only The structure is simple, and the limited range of the output waveform can be easily adjusted up and down with the level Vref as the center.

Contents of the invention

The technology of the present invention solves the problem: overcomes the deficiencies of the prior art, and proposes a circuit with good linearity in the linear input range, when the absolute value of the input voltage is greater than a certain value, the limiting effect is better, and the loop has good stability differential input limiting amplifier.

The technical solution of the present invention: a limiting amplifier with differential input, which is characterized in that: a first limiting circuit, a second limiting circuit, a first resistor divider network, a second resistor divider network, and a first current mirror array , a second current mirror array, and an operational amplifier. The differential input signals P1 and P2 are respectively connected to the first input terminal of the first resistor divider network and the third input terminal of the second resistor divider network. The reference input voltage Vref and the first The third input end of a resistor divider network is connected; the first, second, and third output ends of the second current mirror array are respectively connected with the first input end of the first current mirror array, the first input end of the first limiter circuit and the first input end of the first limiter circuit. The first input end of the second limiter circuit is connected; the first and second output ends of the first limiter circuit are respectively connected with the second input end of the first current mirror array and the first input end of the second resistor divider network; The first and second output ends of the second limiter circuit are respectively connected to the third input end of the first current mirror array and the second input end of the first resistance voltage divider network; the first and second output ends of the first resistance voltage divider network Ends are respectively connected with the first input terminal of the operational amplifier and the second input terminal of the first limiting circuit; the first and second output terminals of the second resistor divider network are respectively connected with the second input terminal of the operational amplifier and the second limiting circuit The second input terminal of the circuit is connected, and the output terminal of the operational amplifier is connected with the second input terminal of the second resistor voltage divider network; the operational amplifier outputs the final result Vout.

Working process of the present invention: the function of the first limiting circuit and the second limiting circuit is to limit the differential input signals P1 and P2 respectively, that is, when the voltage value of the input signal P1 is less than zero, the second limiting circuit works Limit the voltage at point Q6 to about zero amplitude; when the voltage value of the input signal P2 is less than zero, the first limiting circuit works to limit the voltage at point Q5 to about zero amplitude; the limited signal is divided by the first resistor The network and the second resistor divider network divide the voltage to obtain appropriate levels and input them to the operational amplifier respectively. Under the joint action of the first resistor divider network, the second resistor divider network and the operational amplifier, the output result Vout is about Subsection functions of Vref and voltage amplitudes of P1 and P2; the first current array and the second current array provide bias current for the circuit to ensure normal operation of the circuit.

Compared with the prior art, the present invention has the advantages that: the present invention can obtain a good linear relationship between the output voltage increment and the input voltage difference within the linear input range by setting the resistor voltage divider network and using the operational amplifier together. When the absolute value is greater than a certain value, the output voltage value is mainly related to the reference voltage and has a weak relationship with the input signal, so as to achieve the purpose of limiting; and the loop has good stability and can clamp negative input voltage. flat. Through the verification of CADENCE's SPECTRA simulator, the result proves that this circuit has the above-mentioned functions and performances.

Description of drawings

Fig. 1 is the differential input limiting amplifier input signal P1 of the present invention and P2 time sequence and amplitude relationship figure;

Fig. 2 is the principle block diagram of differential input limiting amplifier of the present invention;

FIG. 3 is an electrical schematic diagram of a differential input limiting amplifier of the present invention.

Detailed ways

As shown in Fig. 2 and Fig. 3, the differential input limiting amplifier of the present invention consists of a first limiting circuit 811, a second limiting circuit 812, a first resistor divider network 813, a second resistor divider network 814, a first current The mirror array 815, the second current mirror array 816 and the operational amplifier 817 are composed.

The input reference signal Vref is used as the reference level of the output level of the differential input limiting amplifier. The output voltage of the differential input limiting amplifier will swing up and down centered on Vref. Generally, Vref is 0.5 times the VDD voltage.

The first resistor divider network 813 is formed by serially connecting a resistor 131, a resistor 132, a resistor 133, and a resistor 134. One end of the resistor 134 is connected to the data input terminal P1, and one end of the resistor 131 is connected to the reference level Vref. The resistor 131 The connecting point Q3 of the resistor 132 is connected to the input terminal of the operational amplifier 817 (the base of the NPN tube 174), and the connecting point Q2 of the resistor 132 and the resistor 133 is connected to the input terminal of the limiting circuit 811 (the collector of the NPN tube 115). , the connection point Q6 of the resistor 133 and the resistor 134 is connected to the output terminal of the limiter circuit 812 (the emitter connection point of the NPN transistor 124 and the NPN transistor 125 ).

The second resistor divider network 814 is formed by series connection of resistor 141, resistor 142, resistor 143, and resistor 144. One end of the resistor 144 is connected to the data input terminal P2, and the emitter of the NPN tube 178 in the operational amplifier 817 is connected to the current mirror The drain end of the NMOS transistor 157 in the array 815 is connected and connected with one end of the resistor 141, the connection point Q1 of the resistor 141 and the resistor 142 is connected with the input terminal of the operational amplifier 817 (the base of the NPN transistor 173), the resistor 142 and the resistor 143 The connecting point Q4 is connected to the input terminal (the collector of the NPN tube 125) of the limiting circuit 812, and the connecting point Q5 of the resistor 143 and the resistor 144 is connected to the output terminal of the limiting circuit 811 (the emitter of the NPN tube 114 and the NPN tube 115 is connected point) connected. In order to make the two input terminals of the circuit have a good matching input impedance, it is necessary to make the sum of the resistance values of the resistor 131, the resistor 132, the resistor 133 and the resistor 134 equal to the sum of the resistance values of the resistor 141, the resistor 142, the resistor 143 and the resistor 144 , and in order to obtain a good linear relationship between the output voltage increment and the input voltage difference, and at the same time have a good clipping effect, it is necessary to adjust the resistor 131, resistor 132, resistor 133, resistor 134, resistor 141, resistor 142, resistor 143 and the respective resistance values of the resistor 144.

The first clipping circuit 811 is made up of NPN tube 111, NPN tube 112, NPN tube 113, NPN tube 114, NPN tube 115, the base of NPN tube 111 is connected with the base of NPN tube 112 and the collector of NPN tube 113 and It is connected with the drain terminal of PMOS transistor 162 in the current mirror array 816, the collectors of NPN transistor 111 and NPN transistor 112 are respectively connected with the power supply VDD end, the emitter of NPN transistor 111 is connected with the base of NPN transistor 114 and the base of NPN transistor 115 connected to the drain terminal of the NMOS transistor 153 in the current source array 815, the emitter of the NPN transistor 112 is connected to the base of the NPN transistor 113 and connected to the collector of the NPN transistor 114, and the emitter of the NPN transistor 113 is connected to the ground end. The limiter circuit 811 realizes the following functions: when the input signal P1 is positive and P2 is negative and less than a certain value, it may make Q5 point lower than 0V, but at this time because the emitter of the NPN tube 113 is connected to the ground end, so the base potential of NPN tube 113 is a Vbe, so the base potential of NPN tube 111 and NPN tube 112 is twice the Vbe, and because the emitter of NPN tube 111 and the base of NPN tube 114 and NPN tube 115 Therefore, it is easy to deduce that the emitter potential of NPN tube 114 and NPN tube 115 should be 0V, thereby clamping the potential of point Q5 to 0V, which means that no matter how small the value of input signal P2 is, the potential of point Q5 will also be Similarly, due to the existence of the limiter circuit 812, no matter how small the value of the input signal P1 is, the potential of Q6 will also be clamped to 0V, thereby achieving the purpose of clamping the input negative level.

The second clipping circuit 812 is made up of NPN tube 121, NPN tube 122, NPN tube 123, NPN tube 124, NPN tube 125, the base of NPN tube 121 is connected with the base of NPN tube 122 and the collector of NPN tube 123 and It is connected to the drain end of PMOS transistor 163 in the current mirror array 816, the collectors of NPN transistor 121 and NPN transistor 122 are respectively connected to the power supply VDD end, the emitter of NPN transistor 121 is connected to the base of NPN transistor 124 and the base of NPN transistor 125 connected to the drain terminal of the NMOS transistor 154 in the current source array 815, the emitter of the NPN transistor 122 is connected to the base of the NPN transistor 123 and connected to the collector of the NPN transistor 124, and the emitter of the NPN transistor 123 is connected to the ground end.

The first current mirror array 815 is formed by NMOS transistors 151, NMOS transistors 152, NMOS transistors 153, NMOS transistors 154, NMOS transistors 155, and NMOS transistors 156. The reference current Iref is connected, and their sources are connected to the ground, the drain of the NMOS transistor 152 is connected to the drain of the PMOS transistor 161 in the current mirror array 816, and the drain of the NMOS transistor 155 is connected to the resistor 175 and the resistor 176 of the operational amplifier 817 The drain end of the NMOS transistor 156 is connected to the drain end of the PMOS transistor 177 in the operational amplifier 817, one end of the capacitor 182 and the base of the NPN transistor 178, and the drain end of the NMOS transistor 157 is connected to the NPN transistor 178 in the operational amplifier 817. The emitter is connected; the current mirror array 816 is formed by the PMOS transistor 161, the PMOS transistor 162, and the PMOS transistor 163, and their grids are respectively connected to the drain end of the NMOS transistor 152 and the drain end of the PMOS transistor 161, and their sources The terminals are respectively connected to the power supply VDD. The role of the current mirror array 815 and the current mirror array 816 is to provide current bias to the differential input limiting amplifier, so that the circuit works in a correct state.

The second current mirror array 816 is made up of PMOS transistor 161, PMOS transistor 162, and PMOS transistor 163, and their gates are respectively connected to the drain end of NMOS transistor 152 and the drain end of PMOS transistor 161, and their source ends are respectively connected to to power supply VDD.

Operational amplifier 817 is made up of PMOS tube 171, PMOS tube 172, NPN tube 173, NPN tube 174, resistor 175, resistor 176, PMOS tube 177, NPN tube 178, resistor 181, capacitor 182, and the gate of PMOS tube 171 and PMOS tube 172 Connected and connected with the drain of PMOS tube 171 and the collector of NPN tube 173, the source terminals of PMOS tube 171, PMOS tube 172 and PMOS tube 177 are respectively connected to the power supply VDD, the drain terminal of PMOS tube 172 is connected with the gate of PMOS tube 177 and The collector of the NPN tube 174 is connected to one end of the resistor 181, the emitter of the NPN tube 173 is connected to one end of the resistor 175, one end of the resistor 176 is connected to the emitter of the NPN tube 174, and one end of the resistor 181 is connected to the capacitor 182. One end is connected, and the collector of the NPN transistor 178 is connected to the power supply VDD. The function of the operational amplifier 817 is mainly to clamp the voltages of the Q1 point and the Q3 point at the same potential, so as to implement the operation circuit by using the resistor network 813 and the resistor network 814 . If the operational amplifier 817 is an ideal operational amplifier, it can be realized that when the absolute value of the input voltage is greater than a certain value, the output voltage value is only related to the reference voltage and has nothing to do with the input signal, but the operational amplifier in the actual situation is a non-ideal operational amplifier. Therefore, when the absolute value of the input voltage is relatively large, the output voltage value still has a weak relationship with the input signal. The function of the resistor 181 and the capacitor 182 is to strengthen the stability of the loop negative feedback of the operational amplifier 817 .

It can be seen from this that the differential input limiting amplifier of the present invention can achieve better limiting of the input signal in the limiting region and good linear amplification in the amplifying region.

Claims (10)

1, difference input range-limiting amplifier, it is characterized in that: form by first amplitude limiter circuit (811), second amplitude limiter circuit (812), first resistance pressure-dividing network (813), second resistance pressure-dividing network (814), first current lens array (815), second current lens array (816), operational amplifier (817), differential input signal P1 links to each other with the first input end of first resistance pressure-dividing network (813) and the 3rd input of second resistance pressure-dividing network (814) respectively with P2, and reference input voltage Vref links to each other with the 3rd input of first resistance pressure-dividing network (813); First, second and third output of second current lens array (816) links to each other with the first input end of first current lens array (815), the first input end of first amplitude limiter circuit (811) and the first input end of second amplitude limiter circuit (812) respectively; First and second output of first amplitude limiter circuit (811) links to each other with second input of first current lens array (815) and the first input end of second resistance pressure-dividing network (814) respectively; First and second output of second amplitude limiter circuit (812) links to each other with the 3rd input of first current lens array (815) and second input of first resistance pressure-dividing network (813) respectively; First and second output of first resistance pressure-dividing network (813) links to each other with the first input end of operational amplifier (817) and second input of first amplitude limiter circuit (811) respectively; First and second output of second resistance pressure-dividing network (814) links to each other with second input of operational amplifier (817) and second input of second amplitude limiter circuit (812) respectively, and the output of operational amplifier (817) links to each other with second input of second resistance pressure-dividing network (814); Operational amplifier (817) output final result Vout.

2, difference input range-limiting amplifier according to claim 1, it is characterized in that: described first resistance pressure-dividing network (813) is by resistance (131), resistance (132), resistance (133), resistance (134) is connected in series in turn, one end of resistance (134) links to each other with data input pin P1, one end of resistance (131) links to each other with reference level Vref, the input of resistance (131) and link to each other a Q3 and the operational amplifier (817) of resistance (132), the base stage that is NPN pipe (174) links to each other, the input of link to each other a Q2 and the amplitude limiter circuit (811) of resistance (132) and resistance (133), the collector electrode that is NPN pipe (115) links to each other, the output of the tie point Q6 of resistance (133) and resistance (134) and amplitude limiter circuit (812), promptly the emitter of NPN pipe (124) and NPN pipe (125) links to each other a little continuous.

3, difference input range-limiting amplifier according to claim 1, it is characterized in that: described second resistance pressure-dividing network (814) is by resistance (141), resistance (142), resistance (143), resistance (144) is connected in series in turn, one end of resistance (144) links to each other with data input pin P2, the emitter of NPN pipe (178) links to each other and links to each other with an end of resistance (141) with the drain terminal of the middle NMOS pipe of current lens array (815) (157) in the operational amplifier (817), the input of resistance (141) and link to each other a Q1 and the operational amplifier (817) of resistance (142), the base stage that is NPN pipe (173) links to each other, the input of link to each other a Q4 and the amplitude limiter circuit (812) of resistance (142) and resistance (143), the collector electrode that is NPN pipe (125) links to each other, the output of the tie point Q5 of resistance (143) and resistance (144) and first amplitude limiter circuit (811), promptly the emitter of NPN pipe (114) and NPN pipe (115) links to each other a little continuous.

4, difference input range-limiting amplifier according to claim 1, it is characterized in that: described first amplitude limiter circuit (811) is by NPN pipe (111), NPN manages (112), NPN manages (113), NPN manages (114), NPN pipe (115) is formed, the collector electrode of the base stage of the base stage of NPN pipe (111) and NPN pipe (112) and NPN pipe (113) links to each other and links to each other with the drain terminal of the middle PMOS pipe of current lens array (816) (162), NPN pipe (111) links to each other with the power supply vdd terminal respectively with the collector electrode of NPN pipe (112), the emitter of NPN pipe (111) links to each other and links to each other with the drain terminal of NMOS pipe 153 in the current source array (815) with the base stage of NPN pipe (114) and the base stage of NPN pipe (115), the emitter of NPN pipe (112) links to each other with the base stage of NPN pipe (113) and links to each other with the collector electrode of NPN pipe (114), and the emitter of NPN pipe (113) is held with receiving.

5, difference input range-limiting amplifier according to claim 1, it is characterized in that: described second amplitude limiter circuit (812) is by NPN pipe (121), NPN manages (122), NPN manages (123), NPN manages (124), NPN pipe (125) is formed, the collector electrode of the base stage of the base stage of NPN pipe (121) and NPN pipe (122) and NPN pipe (123) links to each other and links to each other with the drain terminal of the middle PMOS pipe of current lens array (816) (163), NPN pipe (121) links to each other with the power supply vdd terminal respectively with the collector electrode of NPN pipe (122), the emitter of NPN pipe (121) links to each other and links to each other with the drain terminal of NMOS pipe (154) in the current source array (815) with the base stage of NPN pipe (124) and the base stage of NPN pipe (125), the emitter of NPN pipe (122) links to each other with the base stage of NPN pipe (123) and links to each other with the collector electrode of NPN pipe (124), and the emitter of NPN pipe (123) is held with receiving.

6, difference input range-limiting amplifier according to claim 1, it is characterized in that: described first current lens array (815) is by NMOS pipe (151), NMOS manages (152), NMOS manages (153), NMOS manages (154), NMOS manages (155), NMOS pipe (156) grid altogether is formed by connecting, and their grid link to each other and link to each other with reference current Iref with the drain terminal of NMOS pipe (151), their source end all is connected to ground, the drain terminal of NMOS pipe (152) links to each other with the drain terminal of PMOS pipe (161) in the current lens array (816), the drain terminal of NMOS pipe (155) links to each other with the point that links to each other of resistance (176) with the resistance (175) of operational amplifier (817), the drain terminal that NMOS manages (156) links to each other with the base stage of electric capacity (182) one ends and NPN pipe (178) with the drain terminal of the middle PMOS pipe of operational amplifier (817) (177) respectively, and the drain terminal of NMOS pipe (157) links to each other with the emitter that the middle NPN of operational amplifier (817) manages (178); Current lens array (816) is by PMOS pipe (161), and PMOS manages (162), and PMOS pipe (163) grid altogether forms, and their grid manage the drain terminal of (152) with NMOS respectively and the drain terminal of PMOS pipe (161) links to each other, and their source end is connected respectively to power vd D.

7, difference input range-limiting amplifier according to claim 1, it is characterized in that: described second current lens array (816) is by PMOS pipe (161), PMOS manages (162), PMOS pipe (163) grid altogether forms, and their grid link to each other with the drain terminal of NMOS pipe (152) and the drain terminal of PMOS pipe (161) respectively, and their source end is connected respectively to power vd D.

8, difference input range-limiting amplifier according to claim 1, it is characterized in that: described operational amplifier (817) is imported the three-stage operational amplifier of single-ended output for both-end, with reference-input signal Vref is benchmark, realizes the amplification to the operational amplifier input signal.

9, limiting amplifier according to claim 1 or 8 described difference inputs, it is characterized in that: described operational amplifier (817) is by PMOS pipe (171), PMOS manages (172), NPN manages (173), NPN manages (174), resistance (175), resistance (176), PMOS manages (177), NPN manages (178), resistance (181), electric capacity (182) is formed, and PMOS pipe (171) links to each other with the grid of PMOS pipe (172) and links to each other with the leakage of PMOS pipe (171) and the collector electrode of NPN pipe (173), and PMOS pipe (171) is received power vd D respectively with the source end of PMOS pipe (172) and PMOS pipe (177), the drain terminal of PMOS pipe (172) links to each other with the grid of PMOS pipe (177) and the collector electrode of NPN pipe (174), and link to each other with an end of resistance (181), the emitter of NPN pipe (173) links to each other with an end of resistance (175), and an end of resistance (176) links to each other with the emitter that NPN manages (174), one end of resistance (181) links to each other with an end of electric capacity (182), and the collector electrode of NPN pipe (178) is received power vd D.

10, difference input range-limiting amplifier according to claim 1 is characterized in that: described first current lens array (815) and second current lens array (816) are to be obtained by mirror image by same reference current source.

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