CN100559362C

CN100559362C - an external memory interface

Info

Publication number: CN100559362C
Application number: CNB2007101765301A
Authority: CN
Inventors: 车德亮; 赵宁
Original assignee: China Aerospace Modern Electronic Co 772nd Institute; Mxtronics Corp
Current assignee: China Aerospace Modern Electronic Co 772nd Institute; Mxtronics Corp
Priority date: 2007-10-30
Filing date: 2007-10-30
Publication date: 2009-11-11
Anticipated expiration: 2027-10-30
Also published as: CN101221542A

Abstract

A kind of external memory interface is by control module, the address output channel, read-write and sheet menu unit, data input channel and data output channel are formed, wherein in control module, designed three 32 map addresses register, make the 32-bit number signal processor possess and carry out mutual ability with the wide external memory storage of multidigit, this interface can be simultaneously to 8,16 and 32 s' external memory storage carries out accessing operation, thereby the extendability and the operation flexibility of 32-bit number signal processor have been improved, this interface structure is simple simultaneously, be easy to control and miniaturization, be convenient on chip, realize.

Description

A kind of external memory interface

Technical field

The present invention relates to a kind of high-performance digital signal processor interface, particularly a kind of external memory interface of high-performance digital signal processor.

Background technology

Since digital signal processor comes out, it just with the distinctive stability of its digital device, repeatability, can be integrated on a large scale, programmability and be easy to realize characteristics such as self-adaptive processing particularly is for the development of Digital Signal Processing provides wide platform.But can the data width of external memory storage is multiple bit wide normally, so support the external memory storage of multiple bit wide will directly influence the extendability and the dirigibility of digital signal processor.The external memory interface of present most of digital signal processors is for the data access underaction, only support the fixedly data access of bit wide, though there is a kind of digital signal processor SMDSP to support 32 bit instructions and 32 bit data, and the data width of permission external memory storage is 8,16 or 32, simultaneously also can be from the external memory storage of 16 or 32 bit widths run time version, but its external memory interface does not possess and the mutual ability of multidigit wide memory, has limited the extendability and the dirigibility of such digital signal processor.

Summary of the invention

Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, a kind of external memory interface that is applicable to 32 embedded high-performance digital signal processors is provided, the 32-bit number signal processor is possessed and the mutual ability of the wide external memory storage of multidigit, thereby improved the extendability and the operation flexibility of 32-bit number signal processor.

Technical solution of the present invention is: a kind of external memory interface comprises:

Control module, receive transfer request signal that CPU or DMA send and with the request-reply signal feedback to CPU or DMA, receive the 32 bit address mapping register values of transmitting on CPU or the DMA system bus, reception is used to produce the outside ready signal of inner ready signal, reception be used for that sheet selected control system, inner ready signal produce and access cycle rolling counters forward clock signal, receive the insertion gap periods signal that is used to solve the external bus conflict; Control module output transmission beginning, address field comparison and data width signal are to the address output channel, output data width and memory width signal are to read-write and sheet menu unit, output access begins, access control, data width, memory width and sign bit expansion or high-order zero padding signal be to the data input channel, and output access begins, access control, data width and memory width signal be to the data output channel;

The address output channel, receive the transmission commencing signal the current OPADD on 24 internal address bus is carried out trivial depositing, receiver address section comparison signal is used for current OPADD and OPADD are last time carried out segmentation relatively, produce the gap periods signal according to address segmentation comparative result and export control module to, receiving the data width signal handles current OPADD, and the address after will handling exports 24 outer address bus to, and the address output channel produces 32 bit address mapping registers and selects signal to export read-write and sheet menu unit to;

Read-write and sheet menu unit, read-write control signal that reception CPU or DMA send and transfer request signal produce the read-write enable signal and export data input channel and data output channel to, reception is used to produce selects low two and the 32 bit address mapping registers of data width, memory width signal, the clock signal of signal, current OPADD to select signal to outside memory chip, and gap periods signal of read-write and the output of sheet menu unit is sent to control module when converting read operation to by write operation;

The data input channel, receive the visit commencing signal and read and write enable signal external memory storage is conducted interviews, reception is used for access control signal that the data input channel is controlled, receives expansion of data width and memory width signal and sign bit or high-order zero padding signal with data read to 32 internal data bus on 32 external data buss;

The data output channel, receive the visit beginning and read and write enable signal external memory storage is conducted interviews, be used for access control signal that the data output channel is controlled in reception, the data type signal that receives data width and memory width signal and CPU or DMA output is write the data on 32 internal data buses on 32 external data buss.

Described control module is by three 32 bit address mapping register AMR0, AMR1 and AMR2, wait counter, access cycle counter, inner ready signal generation unit, request-reply module, transmission beginning module, visit beginning module and insert the gap periods module and form; The request-reply module receives the transfer request signal that CPU or DMA send and produces the request-reply signal feedback to CPU or DMA, and transmission beginning module produces and transmits commencing signal and export the address output channel to when transmission requests allows; 32 bit address mapping register AMR0, AMR1 and AMR2 receive 32 bit address mapping register values by system bus, be used for directly connecting the external memory storage of different in width in continuous address, and according to one among current OPADD gating 32 bit address mapping register AMR0, AMR1 and the AMR2; By 32 bit address mapping register output data width of gating and memory width to address output channel, sheet choosing and read-write cell, data input channel and data output channel, expansion of output symbol position or high-order zero padding signal are to the data input channel, and OPADD section comparison signal is to the address output channel; Insert the gap periods module and insert the conflict that the gap periods signal solves external bus by receiving; Wait for that counter receives by the wait rolling counters forward value in the 32 bit address mapping registers of gating; Inner ready signal generation unit is subjected to the control of inner ready signal producing method, according to the count value of waiting for counter, outside ready signal, insert gap periods whether effectively and clock signal clk 1 produce inner ready signal; Visit beginning module receives inner ready signal and produces the visit commencing signal and export the data input channel to and the data output channel; Access cycle, counter received inner ready signal and according to the data width and memory width signal combination clock signal clk 1 and the CLK2 that receive and have or not the transfer request signal cycle count that conducts interviews, and sent that the access control signal outputs to the data input channel, the data output channel is done Data Transmission Controlling.

Described 32 bit address mapping registers are by outside port locking bit HOLDST, port holding position NOHOLD, internal port holding position HIZ, inner ready signal producing method position SWW, wait for the control bit WTCNT of counter, address field is control bit BNKCMP relatively, data width Data type size, memory width Physicai memory width, sign bit expansion or high-order zero padding control bit SIGNEXT/ZERO FILL, 32 bit address mapping register configuration bit AMR-config and 32 bit address mapping registers conversion position AMR-switch form; Wherein represent locking during HOLDST=1 to outside port memory; Port occupies external bus and controls external bus during NOHOLD=1; Internal port is in hold mode during HIZ=1; Inner ready signal producing method position SWW constitutes by two, be used for being provided with inner ready signal producing method, when SWW=00, wait for outside ready signal, when SWW=01, wait for the counting ready signal, when SWW=10, wait for outside ready signal or counting ready signal, when SWW=11, wait for outside ready signal and counting ready signal; The control bit WTCNT that waits for counter constitutes by three, is used for controlling the count value of waiting for counter, and count value is from 000-111; Address field comparison control bit BNKCMP constitutes by five, and the controlling value scope is 00000-10000, and the high 0-Gao of the more current OPADD of expression and OPADD last time is 16 respectively, purpose be for efficient when the continuation address spatial operation higher; Data width Data type size constitutes by two, and it is to represent 8 bit data at 00 o'clock, is to represent 16 bit data at 01 o'clock, is to represent 32 bit data at 11 o'clock; Memory width Physical memorywidth constitutes by two, and it is to represent 8 bit memories at 00 o'clock, is to represent 16 bit memories at 01 o'clock, is to represent 32 bit memories at 11 o'clock; Sign bit expansion or high-order zero padding control bit SIGN EXT/ZERO FILL represent the sign bit expansion when it is 0, represent high-order zero padding when it is 1; 32 bit address mapping register configuration bit AMR-config represent that when it is 1 AMR0 can carry out addressing to the AMR1 address space; 32 bit address mapping registers conversion position AMR-switch, being illustrated in when it is 0 when changing between three map addresses registers does not need to insert the change-over period, represents that when it is 1 needs insert the single cycle; Remaining control bit is done and is kept the position, so that 32 bit address mapping registers are done further improvement.

Described address output channel is converted to the physical address unit by address latch unit, address decoding unit, address field comparing unit and logical address and forms; The address latch unit receives the visit commencing signal current OPADD is latched, and the address effectively also continues one-period; The sector address comparison signal that the sector address comparing unit receives the output of described control module compares the current OPADD of the trivial deposit receipt in address unit and OPADD last time high 0 to high 16, judge whether in same address field, if not in same address field then carry out address field conversion, and export one and insert gap periods to control module; Address decoding unit judges that according to the difference of current OPADD this address belongs to the mapping scope of AMR0, AMR1 or AMR2, and exports 32 bit address mapping registers according to judged result and select signal AMR0/ARM1/AMR2 ACTIVE to read-write and sheet menu unit; Logical address is converted to the physical address unit and is used for difference according to the data width of described control module output, being shifted afterwards to current OPADD, the generation physical address exports 24 outer address bus to, to satisfy with the requirement of low order address as the sheet choosing, when data width was 8, physical address equaled logical address and moves to right 2; When data width was 16, physical address equaled logical address and moves to right 1, and when data width was 32, physical address equaled logical address.

Described read-write and sheet menu unit are made up of read-write control unit and sheet selected control system unit, read-write control unit receives the transfer request signal that sends from CPU or DMA and read-write control signal and produces the read-write enable signal and export data input channel and data output channel to, exports external memory storage simultaneously to and is used for read-write control to external memory storage; Sheet selected control system unit selects signal AMR0/ARM1/AMR2 ACTIVE and 2 pairs of external memory storages of clock signal clk to carry out the sheet choosing according to the data width that receives, memory width, 32 bit address mapping registers, low two address pin of translating sign indicating number selectively as sheet respectively or connecing external memory storage in address, gap periods signal of output is given control module when converting read operation to by write operation.

Described data input channel is made up of read data control module and data Input Control Element, the data Input Control Element receives the visit commencing signal external memory storage is conducted interviews, the read data control module is transferred to the data Input Control Element according to the data width that receives and 4 data gating signals of memory width signal generation, the data Input Control Element reads 32 data on the external data bus under the control of access control and read-write enable signal, and be that a component is 4 groups with the data that read by per 8 by the data Input Control Element, carry out gating control by data strobe signal then, for the data of the data width that reads less than 32, the data Input Control Element carries out sign bit expansion or high-order zero padding by signed number or unsigned number to the data that read, be converted into 32 bit data, final by the data Input Control Element with on data read to 32 internal data bus on 32 external data buss.

Described data output channel is made of write data control module and data output control unit, data output control unit receives the visit commencing signal external memory storage is conducted interviews, the write data control module is transferred to data output control unit according to the data length that receives and 4 data gating signals of memory width signal generation, data output control unit reads 32 data on the internal data bus under the control of access control and read-write enable signal, and be that a component is 4 groups with the data that read by per 8 by data output control unit, carry out gating control by data strobe signal then, finally by data output control unit the data on 32 internal data buses are write on 32 external data buss according to the data type signal of CPU or DMA output.

Compared with prior art the present invention has the following advantages:

(1) a kind of external memory interface of the present invention's design is supported 8,16 and 32 external memory storages simultaneously, the 32-bit number signal processor is possessed and the mutual ability of the wide external memory storage of multidigit, improved the extendability and the operation flexibility of 32-bit number signal processor.

(2) a kind of external memory interface of the present invention design is simple in structure, can miniaturization, be convenient on chip, realize.

Description of drawings

Fig. 1 is a kind of external memory interface structural drawing of the present invention;

Fig. 2 is a control module structural drawing of the present invention;

Fig. 3 is the circuit diagram of the inner ready signal generation unit of the present invention;

Fig. 4 is the clear circuit figure of counter access cycle of the present invention;

Fig. 5 is an address of the present invention output channel structural drawing;

Fig. 6 writes and sheet menu meta structure figure for the present invention;

The chip selection signal circuit diagram that Fig. 7 produces for map addresses register AMR0 of the present invention;

Fig. 8 data input channel of the present invention structural drawing;

Fig. 9 is a data output channel structural drawing of the present invention;

Figure 10 is a principle of work block diagram of the present invention.

Embodiment

Below in conjunction with accompanying drawing and embodiment the present invention is done to describe in further detail:

As shown in Figure 1, a kind of external memory interface comprises control module, address output channel, read-write and sheet menu unit, data input channel and data output channel;

As shown in Figure 2, control module is by three 32 bit address mapping register AMR0, AMR1 and AMR2, wait counter, access cycle counter, inner ready signal generation unit, request-reply module, transmission beginning module, visit beginning module and insert the gap periods module and form; The request-reply module receives the transfer request signal that CPU or DMA inflammation go out and produces the request-reply signal feedback to CPU or DMA, and transmission beginning module produces and transmits commencing signal and export the address output channel to when transmission requests allows; 32 bit address mapping register AMR0, AMR1 and AMR2 receive 32 bit address mapping register values by system bus, be used for directly connecting the external memory storage of different in width in continuous address, and according to one among current OPADD gating 32 bit address mapping register AMR0, AMR1 and the AMR2; By 32 bit address mapping register output data width of gating and memory width to address output channel, sheet choosing and read-write cell, data input channel and data output channel, expansion of output symbol position or high-order zero padding signal are to the data input channel, and OPADD section comparison signal is to the address output channel; Insert the gap periods module and insert the conflict that the gap periods signal solves external bus by receiving; Wait for that counter receives by the wait rolling counters forward value in the 32 bit address mapping registers of gating; Inner ready signal generation unit is subjected to the control of inner ready signal producing method, according to the count value of waiting for counter, outside ready signal, insert gap periods whether effectively and clock signal clk 1 produce inner ready signal; Visit beginning module receives inner ready signal and produces the visit commencing signal and export the data input channel to and the data output channel; Access cycle, counter received inner ready signal and according to the data width and memory width signal combination clock signal clk 1 and the CLK2 that receive and have or not the transfer request signal cycle count that conducts interviews, and sent that the access control signal outputs to the data input channel, the data output channel is done Data Transmission Controlling.The concrete control bit of each 32 bit address mapping register is as shown in table 1.

Table 1 32 bit address mapping register control bits

Abbreviation	The register controlled position	Function	Initial value resets
Abbreviation	The register controlled position	Function	Initial value resets	HOLDST	0	Keep locking bit	0
NOHOLD	1	The port holding position	0	HOLDST	0	Keep locking bit	0
NOHOLD	1	The port holding position	0	HIZ	2	The internal port holding position	0
SWW	3-4	Inner ready signal producing method position	11	HIZ	2	The internal port holding position	0
SWW	3-4	Inner ready signal producing method position	11	WTCNT	5-7	Wait for the counter controls position	111
BNKCMP	8-12	Address field is control bit relatively	10000	WTCNT	5-7	Wait for the counter controls position	111
BNKCMP	8-12	Address field is control bit relatively	10000	Data type size	16-17	Data width	11
Physical memory Width	18-19	Memory width	11	Data type size	16-17	Data width	11
Physical memory Width	18-19	Memory width	11	Sign ext/Zero fill	20	Sign bit expansion or high-order zero padding	0

AM R-co nfig	21	The AMR configuration bit	0
AM R-co nfig	21	The AMR configuration bit	0	AM R-switch	22	AMR changes the position	0
XXXXXXXX XXX	23-31， 13-15	Keep the position	All read to do 0	AM R-switch	22	AMR changes the position	0

In the table 1, outside port locking bit HOLDST represents the locking to outside port memory during HOLDST=1; Port holding position NOHOLD, port occupies external bus and controls external bus during NOHOLD=1; Internal port holding position HIZ, internal port is in hold mode during HIZ=1; Inner ready signal producing method position SWW, constitute by two altogether, be used for being provided with inner ready signal producing method, when SWW=00, wait for outside ready signal, when SWW=01, wait for the counting ready signal, when SWW=10, wait for outside ready signal or counting ready signal, when SWW=11, wait for outside ready signal and counting ready signal; Wait for the control bit WTCNT of counter, constitute by three that be used for controlling the count value of waiting for counter, count value is from 000-111; Address field is control bit BNKCMP relatively, constitutes by five, and the controlling value scope is 00000-10000, and the high 0-Gao of the more current OPADD of expression and OPADD last time is 16 respectively, purpose be for efficient when the continuation address spatial operation higher; Data width Datatype size constitutes by two, and it is to represent 8 bit data at 00 o'clock, is to represent 16 bit data at 01 o'clock, is to represent 32 bit data at 11 o'clock; Memory width Physical memory width constitutes by two, and it is to represent 8 bit memories at 00 o'clock, is to represent 16 bit memories at 01 o'clock, is to represent 32 bit memories at 11 o'clock; Sign bit expansion or high-order zero padding control bit SIGN EXT/ZERO FILL represent the sign bit expansion when it is 0, represent high-order zero padding when it is 1; 32 bit address mapping register configuration bit AMR-config represent that when it is 1 AMR0 can carry out addressing to the AMR1 address space; 32 bit address mapping registers conversion position AMR-switch, being illustrated in when it is 0 when changing between three map addresses registers does not need to insert the change-over period, represents that when it is 1 needs insert the single cycle; Remaining control bit is done and is kept the position, so that 32 bit address mapping registers are done further improvement.

Gap periods is in order to avoid the most direct method of external bus conflict when external memory storage being read and write conversion, when same transmission state running hours the external bus conflict can not take place, be transformed into from any operation and write the external memory storage operation and also the external bus conflict can not take place.But under following three class situations, need insert gap periods for fear of the external bus conflict, the first kind is to be judged whether to need to insert a gap periods by the conversion position AMR-switch in the 32 bit address mapping registers, avoids taking place when three external memory storages transmit conversion the external bus conflict; Second class is to be transformed into read data when operation from data writing operation, needs to give the read-write conversion to reserve half period above switching time; The 3rd class is current OPADD and the address field of OPADD does not last time need to insert a gap periods more simultaneously, and the time of wherein inserting gap periods is not waited according to the difference of actual conditions, generally at half to one-period.

The producing method of inner ready signal can be by being controlled by the inside ready signal control bit AMR-3 and the AMR-4 of 32 bit address mapping registers of gating.Outside ready signal RDYext signal will be directly used in the generation of the inner ready signal RDYint of control, the moment that inner ready signal RDYint gathers is all at the clock falling edge, outside ready signal RDYext is initially located in stable at clock CLK1 negative edge when external memory storage is carried out read-write operation, so the stabilizing effective time period of outside ready signal RDYext drops to clock CLK1 rising edge for clock CLK1, thus the back all relate to the place of inner ready signal RDYint control and all can use clock signal clk 1.In interface inside, inner ready signal can produce by waiting for the counting ready signal RDYwtcnt that counter produces, the 5th AMR-5 in the 32 bit address mapping registers, the 6th AMR-6 and the 7th AMR-7 are used for giving wait counter initialize when each visit begins, wait for counter counting reciprocal, count down at 0 o'clock and stop counting, RDYwtcnt is effective for the counting ready signal, can require to adjust the transmission cycle of interface at the sequential of different external memory storages by the method for waiting for rolling counters forward, guarantee the highest transfer efficiency.Send whether insert the generation that gap periods also can directly influence inner ready signal when asking at CPU or DMA.

Among Fig. 3, outside ready signal RDYext, insert gap periods signal Insert cycle and wait for the input signal of rolling counters forward ready signal RDYwtcnt as three input nand gate nand3_07, outside ready signal RDYext, insert the non-input signal of gap periods signal Insert cycle and the 3rd ARM-3 of 32 bit address mapping registers as three input nand gate nand3_08, reset signal RESET and the input signal of no request signal Noreq signal as two input rejection gate nor2_10, the 4th AMR-4 of 32 bit address mapping registers non-through behind the reverser inv_18 with wait for rolling counters forward ready signal RDYwtcnt, insert gap periods signal Insert cycle, the non-input signal of the 3rd AMR-3 of 32 bit address mapping registers as four input nand gate nand4_02, the 3rd AMR-3 of 32 bit address mapping registers non-through behind the reverser inv_19 with wait for rolling counters forward ready signal RDYwtcnt, insert gap periods signal Insert cycle, the non-input signal of the 4th AMR-4 of 32 bit address mapping registers as four input nand gate nand4_03, the output of three input nand gate nand3_07, the output of three input nand gate nand3_08, the output of two input rejection gate nor2_10, the output of the output of four input nand gate nand4_02 and four input nand gate nand4_03 through five input nand gate nand5_01 after as the input of reverser inv_20, the output of reverser inv_20 produces inner ready signal RDYint after through reverser inv_21.

When memory width and data width not simultaneously, to the access cycle of external memory storage also can be different, table 2 shows the relation of data width, external memory storage width and access cycle.

Table 2 data width, external memory storage width and the relation of access cycle

Data width	Memory width	Access cycle
Data width	Memory width	Access cycle	8	8,16,32	1 cycle
16	8	2 cycles	8	8,16,32	1 cycle
16	8	2 cycles	16	16,32	1 cycle
32	8	4 cycles	16	16,32	1 cycle
32	8	4 cycles	32	16	2 cycles
32	32	1 cycle	32	16	2 cycles

For the different access cycle is controlled, in control module, designed one access cycle counter, access cycle, the structure of counter was to be made up of clear circuit and one two digit counter, two digit counters are made up of low level CL and high-order CH, count value is C00-C11, represent first to fourth cycle respectively, but be not that each transmission all needs four cycles, realize clear operation so need suitable clear circuit.Access cycle, counter was finished under different pieces of information width and the memory width cycle count to external memory storage by receiving inner ready signal, data width and memory width signal, no request signal and clock signal, and cycle count value is outputed to data input channel, data output channel as the access control signal was used for control data transmission.In the concrete counting process, reset signal CLEAR and clock signal clk 2 combinations participate in control rolling counters forward access cycle, if once visit needs to wait for a lot of cycles, should be hold modes at the waiting time counter, do not keep exactly when not counting yet not zero clearing, so count signal is:

COUNT(CLK2)＝RDYint·CLEAR·CLK2

After the external memory interface primary access is finished, need to access cycle counter carry out zero clearing, the free time that reset signal also indicates simultaneously current Interface status whether, when interface carries out access to data, reset signal is invalid, access cycle, counter began counting, and wherein the expression formula of reset signal is:

CLEAR＝RDYint·[Noreq+(D32M16|D16M8+C01)·(D32M8+C11)]

Noreq represents current not request in the formula, D32M8 represents 32 bit data, 8 bit memories, D32M16 represents 32 bit data, 16 bit memories, D16M8 represents 16 bit data, 8 bit memories, C11 and C01 represent 4 of current transmission needs and 2 cycles respectively, and inner ready signal RDYint represented that interface was in running order at 0 o'clock; By following formula as can be known, have only interface not to be in a hurry, just finish an access cycle, and all visits all are through with one to transmit just and finish, so ready signal RDYint is 1 to be the most important condition of gauge zero clearing access cycle.Also need zero clearing when not having transmission requests, for the arrival of transmission requests is prepared, when transmission requests, the condition of timer zero clearing access cycle is that cycle count arrives required value.

Access cycle counter clear circuit as shown in Figure 4, the low level CL of two digit counters and high-order CH are through two inputs and door and2_03 and the input signal of no request signal Noreq as two input rejection gate nor2_03, the low level CL of no request signal Noreq and two digit counters is through the input signal of two input rejection gate nor2_04 and signal D32M16/D16M8 as two input nand gate nand2_02, D32M8 and two input rejection gate nor2_03 outputs are as the input signal of two input nand gate nand2_01, and the output of inner ready signal RDYint and two input nand gate nand2_01 and the output of two input nand gate nand2_02 obtain reset signal CLEAR through phase inverter inv_01 after through three input nand gate nand3_01.

As shown in Figure 5, the address output channel is converted to the physical address unit by address latch unit, address decoding unit, address field comparing unit and logical address and forms.The address latch unit latchs current OPADD after receiving the visit commencing signal, and the address effectively also continues one-period, and this moment, the address was the most stable, and can be used for other relevant control; High 0 with the current OPADD of the trivial deposit receipt in address unit and OPADD last time after the sector address comparing unit receiver section address comparison signal compares to high 16, judge whether in same address field, if not in same address field then need to carry out address field conversion, need to insert a gap periods this moment, and should insert gap periods and export control module to; Address decoding unit judges that according to the difference of current OPADD this address belongs to the mapping scope of AMR0, AMR1 or AMR2, produces 32 bit address mapping registers according to the result who judges and selects signal AMR0/ARM1/AMR2 ACTIVE and export read-write and sheet menu unit to; Logical address is converted to the physical address unit and is used for difference according to data width, being shifted afterwards to current OPADD, the generation physical address exports 24 outer address bus to, to satisfy with the requirement of low order address as the sheet choosing, when data width was 8, physical address equaled logical address and moves to right 2; When data width was 16, physical address equaled logical address and moves to right 1, and when data width was 32, physical address equaled logical address.

As shown in Figure 6, read-write is made up of read-write control unit and sheet selected control system unit with sheet menu unit, read-write control unit receives the read-write control signal that produces after the transfer request signal that sends from CPU or DMA and the read-write control signal under this transmission mode and exports data input channel and data output channel to as the read-write enable signal, exports external memory storage simultaneously to and realizes read-write control to external memory storage; 32 bit address mapping register gating signals of sheet selected control system unit receiver address output channel output, reception is by the data width in the 32 bit address mapping registers of gating, memory width signal and current OPADD low two, receive clock signal CLK2, according to data width, the difference of memory width selects 2 pairs of external memory storages of different and clock signal clk of signal to carry out the sheet choosing with 32 bit address mapping registers, according to data width, the difference of memory width, low two address pin of translating sign indicating number selectively as sheet respectively or connecing external memory storage in address, gap periods signal of output is given control module when converting read operation to by write operation.

Because external memory interface both can have been handled 8,16 and 32 s' data, can control 8 again, 16 and 32 s' external memory storage, therefore the sheet selected control system of external memory storage needs CSAMR0[0-3], CSAMR1[0-3] and CSAMR2[0-3] three groups totally 12 control lines participate in the sheet choosing of each external memory storage, CSAMR0[0-1 wherein], CSAMR1[0-1] and CSAMR2[0-1] only be used for sheet selected control system, their logic is fairly simple, CSAMR0[2-3], CSAMR1[2-3] and CSAMR1[2-3] can the double as sheet choosing and address minimum two, do the address time spent and will distinguish the different sequential of read operation and write operation, and each sheet choosing end all has own sheet choosing to enable control and memory set is controlled.When primary access finish and access next time not at first, system is in gap periods, this moment, the chip selection signal to external memory storage was in illegal state, 32 bit address mapping register AMR0 have pair ability of AMR1 address space addressing simultaneously, only need that configuration bit AMR-config among the 32 bit address mapping register AMR0 is arranged to 1 this moment and get final product, on sheet selected control system, only the group control of map addresses register AMR0 need be done to change to get final product slightly.

Fig. 7 is the external memory storage chip select circuit that is produced by AMR0, and is identical with Fig. 7 with the external memory storage chip select circuit that AMR2 produces by AMR1.AMR-16, AMR-17, AMR-19 are respectively the 16th, 17,19 of 32 bit address mapping register AMR0 among Fig. 8; A0, A1 are respectively the 0th and first of current OPADD; CLK2 is a clock signal; M8 represents 8 bit memories, and M16 represents 16 bit memories, and M32 represents 32 bit memories, and D8 represents 8 bit data, and D16 represents 16 bit data, and D32 represents 32 bit data, CSAMR0[0-3] one group of chip selection signal producing by AMR0 of expression.

Among Fig. 7,32 bit address mapping register AMR0 useful signal AMR0 logic and data width signal D8/D16/D32 are as the input signal of two input rejection gate nor2_05, the outputs of two data width signal D8/D16/D32 and two input rejection gate nor2_05 are selected a selector switch mux3_01 through one three, and with 8 bit memories and clock signal M8﹠amp; CLK2,16 bit memories and clock signal M16﹠amp; CLK2 and 32 bit memories and clock signal M32﹠amp; CLK2 is as three control signals of selecting a selector switch mux3_01, three outputs of selecting a selector switch mux3_01 produce chip selection signal CSAMR0[3 through reverser inv_08], the output of reverser inv_08 simultaneously feeds back to the input end of inv_08 after through reverser inv_09 again.

32 bit address mapping register AMR0 useful signal AMR0 logic and data width signal D8/D16/D32 are as the input of two input rejection gate nor2_06, the outputs of two data width signal D8/D16/D32 and two input rejection gate nor2_06 are selected a selector switch mux3_02 through one three, and with 8 bit memories and clock signal M8﹠amp; CLK2,16 bit memories and clock signal M16﹠amp; CLK2 and 32 bit memories and clock signal M32﹠amp; CLK2 is as three control signals of selecting a selector switch mux3_02, three outputs of selecting a selector switch mux3_02 produce chip selection signal CSAMR0[2 through reverser inv_10], the output of reverser inv_10 simultaneously feeds back to the input end of inv_10 after through reverser inv_11 again.

The non-AMR-16not that non-A0 not that the address is the 0th and 32 bit address mapping register AMR0 are the 16th is as the input of two input nand gate nand2_03; The non-AMR-19not that 32 bit address mapping register AMR0 the 19th is as the input of reverser inv_12, and non-AMR-16not that the 1st A1 in address and 32 bit address mapping register AMR0 are the 16th and the output of reverser inv_12 are as the input of three input nand gate nand3_02; The non-AMR-17not that the output of the 0th A0 in address and the 16th AMR-16 of 32 bit address mapping register AMR0 and reverser inv_12 and 32 bit address mapping register AMR0 are the 17th is as the input of four input nand gate nand4_01; The output of the output of the output of two input nand gate nand2_03 and three input nand gate nand3_02 and four input nand gate nand4_01 is as the input of three input nand gate nand3_03.The non-RESET not of reset signal and holding signal HOLD are as the input of two input nand gate nand2_04, the 21st AMR-21 of 32 bit address mapping register AMR0 and 32 bit address mapping register gating signal AMR1 ACTIVE through behind two inputs and the door and2_04 with the input of 32 bit address mapping register gating signal AMR0 ACTIVE as two input rejection gate nor2_08, transmit not ready signal NOT READY FOR TRANSLATE, the output of the output of two input nand gate nand2_04 and two input rejection gate nor2_08 through three input rejection gate nor3_02 after with whether insert the input of the non-AN Extra cycle needed not of gap periods signal as two input nand gate nand2_05.The non-AMR-16not that the 1st A1 in address and the 19th AMR-19 of 32 bit address mapping register AMR0 and 32 bit address mapping register AMR0 are the 16th is as the input of three input nand gate nand3_04, the non-A0 not of the 0th of address through reverser inv_15 after with the non-AMR-16not of the 16th of 32 bit address mapping register AMR0 and the 16th AMR-16 of 32 bit address mapping register AMR0 input as three input nand gate nand3_05, the non-A0 not of the 0th of address through reverser inv_15 after with the non-AMR-17not of the 17th of 32 bit address mapping register AMR0 and the 19th AMR-19 of 32 bit address mapping register AMR0 input, the output of three input nand gate nand3_04 as three input nand gate nand3_06, the output of the output of three input nand gate nand3_05 and three input nand gate nand3_06 is as the input of three inputs with door and3_01; The output of the output of two input nand gate nand2_05 and three input nand gate nand3_03 exports transmission gate n_03 to after importing rejection gate nor2_07 through two, and do control by clock CLK2, the output of transmission gate n_03 produces chip selection signal CSAMR0[1 through reverser inv_13], the output of reverser inv_13 simultaneously feeds back to the input end of reverser inv_13 after through reverser inv_14 again; The output of two input nand gate nand2_05 and three inputs export transmission gate n_04 to after importing rejection gate nor2_09 with the output of door and3_01 through two, and do control by clock CLK2, the output of transmission gate n_04 produces chip selection signal CSAMR0[0 through reverser inv_16], the output of reverser inv_16 simultaneously feeds back to the input end of reverser inv_16 after through reverser inv_17 again.

As shown in Figure 8, the data input channel is made up of read data control module and data Input Control Element.The data Input Control Element receives visit beginning back external memory storage is conducted interviews, the read data control module is transferred to the data Input Control Element according to 4 data gating signals of different generations of data width and memory width, the data Input Control Element reads 32 data on the external data bus under the control of access control and read-write enable signal, and be that a component is 4 groups with the data that read by per 8 by the data Input Control Element, carry out gating control by data strobe signal then, for the data of the data width that reads less than 32, the data Input Control Element carries out sign bit expansion or high-order zero padding by signed number or unsigned number to the data that read, be converted into 32 bit data, finally by the data Input Control Element with on this data read to 32 internal data bus.

As shown in Figure 9, the data output channel is made of write data control module and data output control unit.Data output control unit receives visit beginning back external memory storage is conducted interviews, the write data control module is transferred to data output control unit according to 4 data gating signals of different generations of data length and memory width, data output control unit reads 32 data on the internal data bus under the control of access control and read-write enable signal, and be that a component is 4 groups with the data that read by per 8 by data output control unit, carry out gating control by data strobe signal then, finally by data output control unit to data type difference, the data that data width is different with memory width are written to respectively on 32 external data buss successively, for example the exponent and the truth of a matter of floating type are exported respectively.

Principle of work of the present invention is as shown in figure 10: control module received the transfer request signal that CPU or DMA send and also produces the request-reply signal when interface was started working;

Transmission beginning when request allows, and will transmit commencing signal and be sent to the address output channel, the address output channel latchs current OPADD, according to one in three 32 bit address mapping registers in the different gating control modules of current OPADD, and export 32 bit address mapping register gating signals to sheet choosing and read-write cell, data width and memory width signal are transferred to the address output channel after by the mapping of 32 bit address mapping registers of gating, read-write and sheet menu unit, data input channel and data output channel, the address output channel is carried out by the conversion of logical address to physical address current OPADD according to the data width signal that receives, the current OPADD that will receive behind the EOC is sent to 24 outer address bus, read-write and the data width of sheet menu unit according to reception, memory width, low two of 32 bit address mapping register gating signals and 24 bit address are carried out sheet selected control system to external memory storage and send the read-write enable signal and realize read-write control to external memory storage;

By 32 bit address mapping registers of gating according to inner ready signal producing method, inquiry waits for whether the count value of counter is zero, perhaps outside ready signal whether effectively and insert gap periods and whether effectively produce inner ready signal, inner ready signal produces the visit commencing signal after through visit beginning unit and outputs to data input channel and data output channel;

Access cycle, counter outputed to data input channel and data output channel with its count value as the access control signal after receiving inner ready signal, began external memory storage is conducted interviews;

Data input channel and data output channel receive read-write control signal that the current OPADD that will visit according to transmission requests behind the access control signal and read-write and sheet menu unit produce and chip selection signal and the external memory storage data that will visit are read and write are controlled and read-write operation;

Access cycle, counter carried out cycle count to read-write operation, do not continue with read-write external memory storage to be conducted interviews if counting is intact according to address and sheet choosing, after counting is finished then visit finish, this moment to access cycle counter carry out zero clearing, new request allows.

Claims

1. An external memory interface, characterized in that it comprises:

The control unit receives the transmission request signal sent by the CPU or DMA and feeds back the request response signal to the CPU or DMA, and receives the 32-bit address mapping register value transmitted on the CPU or DMA system bus through the three 32-bit address mapping registers contained inside. It is used to directly connect external memories of different widths in a continuous address space, and selects one of the three 32-bit address mapping registers according to the current output address; receives an external ready signal for generating an internal ready signal, and receives an external ready signal for chip selection Control, internal ready signal generation and access cycle counter counting clock signal, receive the interval cycle signal used to solve the external bus conflict; the control unit outputs the transmission start, address segment comparison and data width signal to the address output channel, and outputs the data width signal and Memory width signal to read/write and chip select unit, output access start, access control, data width signal, memory width signal and sign bit extension or high bit zero padding signal to data input channel, output access start, access control, data width signal and memory width signal to data output channel;

Address output channel, receiving the transmission start signal to latch the current output address on the 24-bit internal address bus, receiving the address segment comparison signal for segment comparison between the current output address and the previous output address, according to the segment comparison result of the address Generate an interval cycle signal and output it to the control unit, receive the data width signal to process the current output address, and output the processed address to the 24-bit external address bus, and the address output channel generates a 32-bit address mapping register selection signal to output to the read-write and Chip selection unit;

Read-write and chip select unit, receive read-write control signal and transmission request signal sent by CPU or DMA, generate read-write enable signal and output to data input channel and data output channel, receive data width used to generate external memory chip select signal signal, memory width signal, clock signal, the lower two bits of the current output address, and the 32-bit address mapping register selection signal. When the write operation is converted into a read operation, the read-write and chip-select unit outputs an interval cycle signal and sends it to the control unit;

The data input channel receives the access start signal and the read and write enable signal to access the external memory, receives the access control signal used to control the data input channel, receives the data width signal and the memory width signal and sign bit extension or high bit zero padding signal to read data on the 32-bit external data bus to the 32-bit internal data bus;

The data output channel receives the access start and read and write enable signals to access the external memory, and receives the access control signal used to control the data output channel, receives the data width signal and the memory width signal, and the data type output by the CPU or DMA signal to write data from the 32-bit internal data bus to the 32-bit external data bus.

2. The external memory interface according to claim 1, characterized in that: said control unit consists of a first 32-bit address mapping register, a second 32-bit address mapping register and a third 32-bit address mapping register, waiting Counter, access cycle counter, internal ready signal generating unit, request response module, transmission start module, access start module and insertion interval cycle module;

The request response module receives the transmission request signal sent by the CPU or DMA and generates a request response signal to feed back to the CPU or DMA. When the transmission request is allowed, the transmission start module generates a transmission start signal and outputs it to the address output channel; the first 32-bit address mapping register, the second The 32-bit address mapping register and the third 32-bit address mapping register receive the 32-bit address mapping register value through the system bus, which is used to directly connect external memories of different widths in the continuous address space, and gate the first 32 bits according to the current output address One of the address mapping register, the second 32-bit address mapping register, and the third 32-bit address mapping register; the gated 32-bit address mapping register outputs data width signals and memory width signals to address output channels, chip selection and read and write Unit, data input channel and data output channel, output sign bit extension or high-order zero padding signal to the data input channel, output address segment comparison signal to the address output channel; insert the interval cycle module to solve the conflict of the external bus by receiving the interval cycle signal; wait The counter receives the counting value of the waiting counter in the gated 32-bit address mapping register; the internal ready signal generation unit is controlled by the internal ready signal generation method, according to the counting value of the waiting counter, the external ready signal, whether the insertion interval period is valid and the first A clock signal generates an internal ready signal; the access start module receives the internal ready signal to generate an access start signal and outputs it to the data input channel and the data output channel; the access cycle counter receives the internal ready signal and combines the received data width signal and the memory width signal with the first The presence or absence of the first clock signal, the second clock signal and the transmission request signal is used to count the access cycle, and the access control signal is sent out to the data input channel and the data output channel for data transmission control.

3. A kind of external memory interface according to claim 2, characterized in that: said 32-bit address mapping register consists of external port lock bit, port hold bit, internal port hold bit, internal ready signal generation mode bit, wait Counter control bits, address segment comparison control bits, data width, memory width, sign bit extension or high-order zero padding control bits, 32-bit address mapping register configuration bits and 32-bit address mapping register conversion bits;

Wherein, when the value of the external port lock bit is 1, it means that the external memory port is locked; when the value of the port hold bit is 1, the port occupies the external bus and controls the external bus; when the value of the internal port hold bit is 1, the internal port is in the hold state; The internal ready signal generation mode bit is composed of two bits, which are used to set the internal ready signal generation mode. When the value of the internal ready signal generation mode bit is 00, it waits for the external ready signal, and when the value of the internal ready signal generation mode bit is 01, it waits Counting ready signal, when the value of the internal ready signal generation mode bit is 10, wait for the external ready signal or counting ready signal, when the value of the internal ready signal generation mode bit is 11, wait for the external ready signal and counting ready signal; wait for the control of the counter The bit is composed of three bits, which are used to control the count value of the waiting counter, and the count value is from 000-111; the address segment comparison control bit is composed of five bits, and the control value range is 00000-10000, which respectively represent the comparison between the current output address and the previous output The high 0 bit of the address - high 16 bits; the data width is composed of two bits. When the value of the data width is 00, it means 8 bits of data. When the value of the data width is 01, it means 16 bits of data. When the value of the data width is 11 When the value of the memory width is 32 bits; the memory width is composed of two bits. When the value of the memory width is 00, it represents an 8-bit memory; when the value of the memory width is 01, it represents a 16-bit memory; when the value of the memory width is 11, it represents a 32-bit memory Memory; sign bit extension or high-order zero padding control bit, when it is 0, it means sign bit extension, when it is 1, it means high-order zero padding; 32-bit address mapping register configuration bit, when it is 1, it means the first 32 bits The address mapping register can address the second 32-bit address mapping register address space; the 32-bit address mapping register conversion bit, when it is 0, means that the interval cycle signal does not need to be inserted when switching between the three address mapping registers, when When it is 1, it means that a single cycle needs to be inserted; the rest of the control bits are reserved for further improvement of the 32-bit address mapping register.

4. A kind of external memory interface according to claim 2, characterized in that: the interval period signal occurs in three types of situations, the first type is judged by the conversion bit in the 32-bit address mapping register whether it needs to insert An interval cycle to avoid external bus conflicts when the three external memories perform transmission conversion; the second type is when switching from writing data operations to reading data operations on the external memory, it is necessary to set aside more than half a cycle for the read-write conversion Conversion time; the third type is that when the address segment of the current output address is different from the previous output address, an interval cycle needs to be inserted.

5. An external memory interface according to claim 2, characterized in that: the circuit structure of the internal ready signal generating unit is: the external ready signal, the interval cycle signal and the waiting counter counting ready signal are used as the first three inputs The input signal of the NAND gate, the external ready signal, the interval cycle signal and the third bit of the 32-bit address mapping register are used as the input signal of the second three-input NAND gate, and the reset signal and no transmission request signal are used as the two-input NOR gate The input signal of the 32-bit address mapping register, the non-input of the fourth bit of the 32-bit address mapping register, and the waiting counter counting ready signal, the interval cycle signal, and the non-inversion of the third bit of the 32-bit address mapping register are used as the first four-input NAND gate after passing through the first inverter The input signal of the third bit of the 32-bit address mapping register is not passed through the second inverter and waits for the counter to count the ready signal, the interval cycle signal, and the fourth bit of the 32-bit address mapping register is not used as the second four-input NAND gate The input signal of the first three-input NAND gate, the output of the second three-input NAND gate, the output of the two-input NOR gate, the output of the first four-input NAND gate and the second four-input NAND gate The output passes through the five-input NAND gate and is used as the input of the third inverter, and the output of the third inverter generates an internal ready signal after passing through the fourth inverter.

6. An external memory interface according to claim 2, characterized in that: the access cycle counter is composed of a clearing circuit and a two-digit counter, the two-digit counter is composed of a low bit and a high bit, and the access cycle counter receives The internal ready signal, data width signal and memory width signal, no request signal and clock signal complete the cycle counting of the external memory, and output the cycle count value as an access control signal to the data input channel, and the data output channel is used to control data transmission; After one access of the external memory interface is completed, the access cycle counter needs to be cleared by the clearing circuit.

7. An external memory interface according to claim 6, characterized in that: said clearing circuit is: the low bit and high bit of the two-bit counter pass through the two-input AND gate and the no request signal as the first two-input NOR The input signal of the gate, no request signal and the low bit of the two-digit counter pass through the second two-input NOR gate and the 16-bit memory signal of 32-bit data or the 8-bit memory signal of 16-bit data as the input signal of the second two-input NAND gate, 32-bit data 8-bit memory signal and the output of the first two-input NOR gate as the input signal of the first two-input NAND gate, the internal ready signal and the output of the first two-input NAND gate and the second two-input NAND gate The output of the three-input NAND gate is passed through an inverter to obtain a clear signal.

8. An external memory interface according to claim 1, wherein the address output channel is composed of an address latch unit, an address decoding unit, an address segment comparison unit, and a logical address to physical address unit; The address latch unit receives the access start signal to latch the current output address, the address is valid and lasts for one cycle; the segment address comparison unit receives the segment address comparison signal and compares the current output address of the address latch unit with the high 0 bit of the previous output address Compare to the upper 16 bits to judge whether it is in the same address segment, if not, perform address segment conversion, and output an interval cycle signal to the control unit; the address decoding unit judges the address according to the difference of the current output address Whether it belongs to the mapping range of the first 32-bit address mapping register, the second 32-bit address mapping register or the third 32-bit address mapping register, and outputs the 32-bit address mapping register selection signal to the read-write and chip selection unit according to the judgment result; logic The address is converted into a physical address unit, which is used to shift the current output address according to the data width to generate a physical address output to the 24-bit external address bus to meet the requirement of using the low address as a chip select. When the data width is 8 When the data width is 16 bits, the physical address is equal to the logical address shifted 1 bit to the right; when the data width is 32 bits, the physical address is equal to the logical address.

9. An external memory interface according to claim 1, characterized in that: the read-write and chip-select unit is composed of a read-write control unit and a chip-select control unit, and the read-write control unit receives the The transmission request signal and the read-write control signal generate a read-write enable signal and output to the data input channel and data output channel, and output to the external memory at the same time for the read-write control of the external memory; the chip select control unit receives the data width signal, The memory width signal, the 32-bit address mapping register selection signal and the second clock signal perform chip selection on the external memory, and the lower two bits of the address are connected to the address pin of the chip selection decoding or to the address pin of the external memory, when converted by a write operation Output an interval period signal to the control unit during a read operation.

10. An external memory interface according to claim 1, wherein the data input channel is composed of a data read control unit and a data input control unit, and the data input control unit receives an access start signal to access the external memory According to the received data width signal and memory width signal, the read data control unit generates 4 data strobe signals and transmits them to the data input control unit. Under the control of the access control and read and write enable signals, the data input control unit reads the 32-bit external The data on the data bus, and the data input control unit divides the read data into 4 groups of 8 bits, and then performs gating control by the data strobe signal. For the read data width less than 32 bits Data, the data input control unit performs sign bit extension or high-order zero padding on the read data according to signed or unsigned numbers, and converts it into 32-bit data, and finally the data input control unit converts the data on the 32-bit external data bus Data is read onto the 32-bit internal data bus.

11. An external memory interface according to claim 1, wherein the data output channel is composed of a write data control unit and a data output control unit, and the data output control unit receives an access start signal to access the external memory , the write data control unit generates 4 data strobe signals according to the received data width signal and memory width signal and transmits them to the data output control unit, and the data output control unit reads the 32-bit internal The data on the data bus, and the data output control unit divides the read data into 4 groups of 8 bits, and then performs strobe control by the data strobe signal, and finally according to the data type signal output by the CPU or DMA The data on the 32-bit internal data bus is written to the 32-bit external data bus by the data output control unit.