CN100514677C - Thin film transistor and forming method thereof - Google Patents
Thin film transistor and forming method thereof Download PDFInfo
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- CN100514677C CN100514677C CNB2005100850257A CN200510085025A CN100514677C CN 100514677 C CN100514677 C CN 100514677C CN B2005100850257 A CNB2005100850257 A CN B2005100850257A CN 200510085025 A CN200510085025 A CN 200510085025A CN 100514677 C CN100514677 C CN 100514677C
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- molybdenum
- alloy layer
- niobium
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- 239000010409 thin film Substances 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims description 111
- 229910001257 Nb alloy Inorganic materials 0.000 claims abstract description 317
- DTSBBUTWIOVIBV-UHFFFAOYSA-N molybdenum niobium Chemical compound [Nb].[Mo] DTSBBUTWIOVIBV-UHFFFAOYSA-N 0.000 claims abstract description 311
- 239000004065 semiconductor Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 239000002131 composite material Substances 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims abstract 277
- 229910045601 alloy Inorganic materials 0.000 claims abstract 60
- 239000000956 alloy Substances 0.000 claims abstract 60
- 239000002356 single layer Substances 0.000 claims abstract 9
- 238000005121 nitriding Methods 0.000 claims description 63
- 238000000151 deposition Methods 0.000 claims description 15
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 description 66
- 238000009413 insulation Methods 0.000 description 21
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 230000003628 erosive effect Effects 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 229910052758 niobium Inorganic materials 0.000 description 3
- 239000010955 niobium Substances 0.000 description 3
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- Thin Film Transistor (AREA)
Abstract
A thin film transistor includes a gate electrode, a gate insulating layer, a semiconductor layer, and source/drain electrodes. The grid electrode is arranged on the substrate, wherein the grid electrode is a single-layer molybdenum niobium nitride alloy or a molybdenum niobium alloy composite layer comprising at least one layer of molybdenum niobium nitride alloy. The gate insulating layer is formed on the substrate to cover the gate electrode. The semiconductor layer is disposed on the gate insulating layer on the substrate. The source/drain is arranged on the semiconductor layer. The thin film transistor of the present invention has a gate and source/drain with low contact resistance or line resistance.
Description
Technical field
The present invention relates to a kind of semiconductor element and forming method thereof, and be particularly related to a kind of thin-film transistor and forming method thereof.
Background technology
Thin-film transistor (TFT) generally comprises grid, gate insulation layer, channel layer and source/drain, and in display, for example LCD (LCD) is used as switch element usually for it.Usually, the formation method of thin-film transistor is to form grid, gate insulation layer, α-Si channel layer and source/drain on substrate successively.Grid is formed by single metal levels such as aluminium, chromium, tungsten, tantalum, titaniums or by the multiple layer metal layer.
Yet when the above-mentioned metal with single metal level formed grid, film surface was etched easily, and easy and oxygen reaction and formation metal oxide, thereby caused can't carrying out etching effectively in follow-up etch process.On the other hand, when grid is made up of the multiple layer metal layer, for example be molybdenum (Mo)/aluminium/molybdenum, can avoid the problem of oxidation and erosion.But the technology that forms the multiple layer metal layer must be comparatively complicated.Because this arts demand surpasses more than one sputtered target material and cvd reactive chamber.In addition, the problems referred to above can occur in the technology that forms source/drain too.
Summary of the invention
Therefore, the present invention proposes a kind of thin-film transistor, and it has than the grid of low contact resistance or line resistance and source/drain.
The present invention proposes a kind of formation method of thin-film transistor in addition, its be to use opposing oxidation and erosion-resistant material form grid and (or) source/drain.
The present invention proposes a kind of thin-film transistor, and this thin-film transistor comprises grid, gate insulation layer, semiconductor layer and source/drain.Grid is arranged on the substrate, and wherein, grid is the molybdenum nitride niobium alloy of individual layer or comprises the molybdenum niobium alloy composite bed of one deck molybdenum nitride niobium alloy at least.Gate insulation layer is formed on the substrate with cover gate.Semiconductor layer is arranged on the gate insulation layer on the substrate.Source/drain is arranged on the semiconductor layer.
The present invention proposes a kind of thin-film transistor in addition, and this thin-film transistor comprises grid, gate insulation layer, semiconductor layer and source/drain.Grid is arranged on the substrate.Gate insulation layer is formed on the substrate with cover gate.Semiconductor layer is arranged on the gate insulation layer on the substrate.Source/drain is arranged on the semiconductor layer, wherein, source/drain very individual layer the molybdenum nitride niobium alloy or comprise the molybdenum niobium alloy composite bed of one deck molybdenum nitride niobium alloy at least.
In an embodiment of the present invention, above-mentioned grid is made up of molybdenum niobium alloy layer and molybdenum nitride niobium alloy layer.
In an embodiment of the present invention, above-mentioned grid is made up of the first molybdenum nitride niobium alloy layer, molybdenum niobium alloy layer and the second molybdenum nitride niobium alloy layer.
In an embodiment of the present invention, above-mentioned source/drain is made up of molybdenum niobium alloy layer and molybdenum nitride niobium alloy layer.
In an embodiment of the present invention, above-mentioned source/drain is made up of the first molybdenum nitride niobium alloy layer, molybdenum niobium alloy layer and the second molybdenum nitride niobium alloy layer.
The present invention proposes a kind of formation method of thin-film transistor in addition, and the method is prior to forming grid on the substrate.Wherein, grid is the molybdenum nitride niobium alloy of individual layer or comprises the molybdenum niobium alloy composite bed of one deck molybdenum nitride niobium alloy at least.Then, on substrate, form gate insulation layer with cover gate.Afterwards, on the gate insulation layer on the substrate, semiconductor layer is set.Next, source/drain is set on semiconductor layer.
The present invention proposes a kind of formation method of thin-film transistor again, and the method is prior to forming grid on the substrate.Then, on substrate, form gate insulation layer with cover gate.Afterwards, on the gate insulation layer on the substrate, form semiconductor layer.Next, on semiconductor layer, form source/drain.Wherein, source/drain very individual layer the molybdenum nitride niobium alloy or comprise the molybdenum niobium alloy composite bed of one deck molybdenum nitride niobium alloy at least.
In an embodiment of the present invention, above-mentioned grid and (or) source/drain forms with following step.At first on substrate, form molybdenum niobium alloy layer.Then molybdenum niobium alloy layer is carried out nitriding process, to form molybdenum nitride niobium alloy layer.Then with molybdenum nitride niobium alloy layer patternization with form grid and (or) source/drain.
In one of the present invention embodiment, above-mentioned grid and (or) source/drain forms with following step.At first on substrate, form the first molybdenum niobium alloy layer.On the first molybdenum niobium alloy layer, form the second molybdenum niobium alloy layer then.Then the second molybdenum niobium alloy layer is carried out nitriding process, on the first molybdenum niobium alloy layer, to form molybdenum nitride niobium alloy layer.Afterwards with molybdenum nitride niobium alloy layer and the first molybdenum niobium alloy layer patternization with form grid and (or) source/drain.
In one of the present invention embodiment, above-mentioned grid and (or) source/drain forms with following step.At first, on substrate, form the first molybdenum niobium alloy layer.Then, the first molybdenum niobium alloy layer is carried out first nitriding process, to form the first molybdenum nitride niobium alloy layer.Then, on the first molybdenum nitride niobium alloy layer, form the second molybdenum niobium alloy layer.Afterwards, on the second molybdenum niobium alloy layer, form the 3rd molybdenum niobium alloy layer.Then, the 3rd molybdenum niobium alloy layer is carried out second nitriding process, on the second molybdenum niobium alloy layer, to form the second molybdenum nitride niobium alloy layer.Then, with the second molybdenum nitride niobium alloy layer, the second molybdenum niobium alloy layer and the first molybdenum nitride niobium alloy layer patternization, with form grid and (or) source/drain.
The electrode of the present invention's thin-film transistor (grid and (or) source/drain) comprises one deck molybdenum nitride niobium alloy at least; it is because there is one deck protecting nitride film on the surface of molybdenum niobium alloy; so with the metal alloy that uses in the known technology by comparison; comparatively stable, so that electrode has preferable repellence for oxidation and erosion.
State with other purpose, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and cooperate appended accompanying drawing, be described in detail below.
Description of drawings
Fig. 1 is the generalized section according to the thin-film transistor of a preferred embodiment of the present invention.
Fig. 2 A is the generalized section according to the double-deck grid of the thin-film transistor of another preferred embodiment of the present invention.
Fig. 2 B is according to the present invention's generalized section of the double-deck source/drain of the thin-film transistor of a preferred embodiment again.
Fig. 3 A is the generalized section according to three layers of grid of the thin-film transistor of the another preferred embodiment of the present invention.
Fig. 3 B is the generalized section according to three layers of source/drain of the thin-film transistor of the another preferred embodiment of the present invention.
The main element description of symbols
100: substrate
102: grid
102a, 102d, 110a, 110d: molybdenum niobium alloy layer
102b, 102c, 102e, 110b, 110c, 110e: molybdenum nitride niobium alloy layer
104: gate insulation layer
105: semiconductor layer
106: channel layer
108: ohmic contact layer
110: source/drain
Embodiment
Fig. 1 is the generalized section according to the thin-film transistor of a preferred embodiment of the present invention.Please refer to Fig. 1, thin-film transistor comprises grid 102, gate insulation layer 104, semiconductor layer 105 and source/drain 110.Grid 102 is arranged on the substrate 100, and gate insulation layer 104 is arranged at substrate 100 tops with cover gate 102.Gate insulation layer 104 for example is that the combination layer by silicon oxide layer, silicon nitride layer or silicon oxide layer and silicon nitride layer is constituted.Semiconductor layer 105 is arranged on the gate insulation layer 104 of grid 102 tops.Source/drain 110 is arranged on the semiconductor layer 105.In the present embodiment, semiconductor layer 105 for example comprise the channel layer 106 that is formed on the gate insulation layer 104 and be formed at channel layer 106 and source/drain 110 between ohmic contact layer 108.
Particularly, according to one of the present invention preferred embodiment, grid 102 comprises one deck molybdenum nitride niobium alloy at least.In other words, grid 102 can be the molybdenum nitride niobium alloy of individual layer or comprise the composite bed of one deck molybdenum nitride niobium alloy at least.If grid 102 is an individual layer, then grid 102 is made up of molybdenum nitride niobium alloy layer.In the present embodiment, form the method such as the following steps of the grid 102 of individual layer.At first, in sputtering process chamber, evaporation process chamber or other known settling chamber, on substrate 100, form one deck molybdenum niobium alloy layer.Molybdenum niobium alloy layer is carried out nitriding process, to form molybdenum nitride niobium alloy layer.For instance, nitriding process can be to feed nitrogen after forming molybdenum niobium alloy layer in above-mentioned settling chamber, or feeds nitrogen in deposition molybdenum niobium alloy layer in above-mentioned settling chamber.Afterwards, utilize photoetching process and etch process, to form grid 102 with molybdenum nitride niobium alloy layer patternization.
If grid 102 is a double-decker, then grid 102 is made up of molybdenum niobium alloy layer 102a and molybdenum nitride niobium alloy layer 102b.Please refer to Fig. 2 A, in this example, form the method such as the following steps of double-deck grid 102.At first, on substrate 100, form the first molybdenum niobium alloy layer 102a.Then, go up the formation second molybdenum niobium alloy layer (not marking among the figure) in the first molybdenum niobium alloy layer 102a.The second molybdenum niobium alloy layer is carried out nitridation reaction technology, to form molybdenum nitride niobium alloy layer 102b.Afterwards, with the molybdenum nitride niobium alloy layer 102b and the first molybdenum niobium alloy layer 102a patterning, to form grid 102.The first molybdenum niobium alloy layer 102a and the second molybdenum niobium alloy layer are formed with foregoing method, and nitridation reaction technology also is to carry out with foregoing same procedure.
If grid 102 is a three-decker, then grid 102 is made up of the first molybdenum nitride niobium alloy layer 102c, molybdenum niobium alloy layer 102d and the second molybdenum nitride niobium alloy layer 102e, please refer to Fig. 3 A.In the present embodiment, form the method such as the following steps of three layers grid 102.At first, on substrate 100, form the first molybdenum niobium alloy layer (not marking among the figure).Then, the first molybdenum niobium alloy layer is carried out as previously described nitriding process, to form the first molybdenum nitride niobium alloy layer 102c.Then, go up the formation second molybdenum niobium alloy layer 102d in the first molybdenum nitride niobium alloy layer 102c.Then, go up formation the 3rd molybdenum niobium alloy layer (not marking among the figure) in the second molybdenum niobium alloy layer 102d.Afterwards, the 3rd molybdenum niobium alloy layer is carried out as previously described nitriding process, to form the second molybdenum nitride niobium alloy layer 102e.Then, with the second molybdenum nitride niobium alloy layer 102e, the second molybdenum niobium alloy layer 102d and the first molybdenum nitride niobium alloy layer 102c patterning, to form grid 102.
In another embodiment, source/drain 110 comprises one deck molybdenum nitride niobium alloy at least, please refer to Fig. 1.In other words, source/drain 110 can be the molybdenum nitride niobium alloy of individual layer or comprise the composite bed of one deck molybdenum nitride niobium alloy at least.If source/drain 110 is an individual layer, then source/drain 110 is made up of molybdenum nitride niobium alloy layer.Similarly, form the method such as the following steps of individual layer source/drain 110.At first, in sputtering process chamber, evaporation process chamber or other known settling chamber, on gate insulation layer 104, form molybdenum niobium alloy layer, to cover semiconductor layer 105.Molybdenum niobium alloy layer is carried out nitriding process, to form molybdenum nitride niobium alloy layer.For instance, nitriding process can be to feed nitrogen after forming molybdenum niobium alloy layer in above-mentioned settling chamber, or feeds nitrogen in deposition molybdenum niobium alloy layer in above-mentioned settling chamber.Afterwards, with molybdenum nitride niobium alloy layer patternization, to form source/drain 110.
If source/drain 110 is a double-decker, then source/drain 110 is made up of molybdenum niobium alloy layer 110a and molybdenum nitride niobium alloy layer 110b, please refer to Fig. 2 B.Similarly, form the method such as the following steps of the source/drain 110 of bilayer.At first, on gate insulation layer 104, form the first molybdenum niobium alloy layer 110a, to cover semiconductor layer 105.Then, go up the formation second molybdenum niobium alloy layer (not marking among the figure) in the first molybdenum niobium alloy layer 110a.The second molybdenum niobium alloy layer carries out nitriding process, to form molybdenum nitride niobium alloy layer 110b.Afterwards, with the molybdenum nitride niobium alloy layer 110b and the first molybdenum niobium alloy layer 110a patterning, to form source/drain 110.The first molybdenum niobium alloy layer 110a and the second molybdenum niobium alloy series of strata are formed with foregoing method, and nitriding process also is to carry out with foregoing same procedure.
When source/drain 110 is a three-decker, then source/drain 110 is made up of the first molybdenum nitride niobium alloy layer 110c, molybdenum niobium alloy layer 110d and the second molybdenum nitride niobium alloy layer 110e, please refer to Fig. 3 B.In the same manner, form the method such as the following steps of three layers source/drain 110.At first, on gate insulation layer 104, form the first molybdenum niobium alloy layer (not marking among the figure), to cover semiconductor layer 105.The first molybdenum niobium alloy layer is carried out as previously described nitriding process, to form the first molybdenum nitride niobium alloy layer 110c.Then, go up the formation second molybdenum niobium alloy layer 110d in the first molybdenum nitride niobium alloy layer 110c.Then, go up formation the 3rd molybdenum niobium alloy layer (not marking among the figure) in the second molybdenum niobium alloy layer 110d.The 3rd molybdenum niobium alloy layer is carried out as previously described nitriding process, to form the second molybdenum nitride niobium alloy layer 110e.Then, with the second molybdenum nitride niobium alloy layer 110e, the second molybdenum niobium alloy layer 110d and the first molybdenum nitride niobium alloy layer 110c patterning, to form source/drain 110.
In another embodiment, grid 102 all comprises one deck molybdenum nitride niobium alloy layer at least with source/drain 110.In other words, grid 102 all can be the molybdenum nitride niobium alloy of individual layer or comprise the composite bed of one deck molybdenum nitride niobium alloy at least with source/drain 110.The above-mentioned composite bed of one deck molybdenum nitride niobium alloy layer at least that comprises can be double-decker or three-decker, please refer to Fig. 2 A, Fig. 2 B, Fig. 3 A and Fig. 2 B.
It should be noted that; because one deck protecting nitride film is arranged on the surface of molybdenum niobium alloy; so the metal alloy in molybdenum nitride niobium alloy layer and the known technology is more stable by comparison, so that molybdenum nitride niobium alloy layer has preferable repellence for oxidation and erosion.In other words, comprise that the electrode of the thin-film transistor of one deck molybdenum nitride niobium alloy layer has preferable repellence for oxidation and erosion at least.Particularly, if when forming the source/drain of three layers grid or three layers, molybdenum niobium alloy layer can be clipped in the middle of two layers of molybdenum nitride niobium alloy layer, with avoid molybdenum niobium alloy layer oxidized with corrode.
In addition, the depositing operation of molybdenum niobium alloy layer and nitridation reaction technology can be carried out in identical reative cell (original position).If when forming double-decker or three-decker, also can in identical reative cell (original position), carry out.Therefore, grid of the present invention with (or) technology of source/drain and uncomplicated, thereby can improve explained hereafter power.
In addition, increase the content of niobium, also can promote the repellence of molybdenum niobium alloy, but the molybdenum niobium alloy target with increase content of niobium is then quite expensive for oxidation and erosion.In the present invention,, replace the content that increases the niobium in the molybdenum niobium alloy, so have the advantage of saving manufacturing cost so that the molybdenum niobium alloy is carried out nitriding process.
It should be noted that, if the present invention's thin-film transistor is during as the switch element of LCD, and when using double-deck or during three layers source/drain, in the etch process of the contact window of follow-up each dot structure, upper strata molybdenum nitride niobium alloy layer can also be used as etch stop layer.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the invention; when can doing a little change and improvement, so the present invention's protection range is as the criterion when looking the claim person of defining.
Claims (29)
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| CNB2005100850257A CN100514677C (en) | 2005-07-19 | 2005-07-19 | Thin film transistor and forming method thereof |
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| CN100514677C true CN100514677C (en) | 2009-07-15 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000284326A (en) * | 1999-03-30 | 2000-10-13 | Hitachi Ltd | Liquid crystal display device and manufacturing method thereof |
| US20020047947A1 (en) * | 1997-11-20 | 2002-04-25 | Myung-Keo Hur | Wire for liquid crystal displays, liquid crystal displays having the same, and manufacturing methods thereof |
| US20020119586A1 (en) * | 2001-02-27 | 2002-08-29 | Nec Corporation | Process for forming pattern and method for producing liquid crystal display apparatus |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020047947A1 (en) * | 1997-11-20 | 2002-04-25 | Myung-Keo Hur | Wire for liquid crystal displays, liquid crystal displays having the same, and manufacturing methods thereof |
| JP2000284326A (en) * | 1999-03-30 | 2000-10-13 | Hitachi Ltd | Liquid crystal display device and manufacturing method thereof |
| US20020119586A1 (en) * | 2001-02-27 | 2002-08-29 | Nec Corporation | Process for forming pattern and method for producing liquid crystal display apparatus |
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