CN100507578C - Method for manufacturing wafer-level test circuit board and structure thereof - Google Patents
Method for manufacturing wafer-level test circuit board and structure thereof Download PDFInfo
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- CN100507578C CN100507578C CNB2006101451329A CN200610145132A CN100507578C CN 100507578 C CN100507578 C CN 100507578C CN B2006101451329 A CNB2006101451329 A CN B2006101451329A CN 200610145132 A CN200610145132 A CN 200610145132A CN 100507578 C CN100507578 C CN 100507578C
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- 238000012360 testing method Methods 0.000 title claims abstract description 78
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 15
- 229910000679 solder Inorganic materials 0.000 claims abstract description 45
- 239000000523 sample Substances 0.000 claims abstract description 9
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 239000007769 metal material Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 claims 17
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000004069 differentiation Effects 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 abstract description 5
- 230000004308 accommodation Effects 0.000 abstract 4
- 238000001514 detection method Methods 0.000 abstract 2
- 238000010998 test method Methods 0.000 abstract 1
- 238000005259 measurement Methods 0.000 description 12
- 230000000694 effects Effects 0.000 description 8
- 239000010408 film Substances 0.000 description 7
- 238000005538 encapsulation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000013100 final test Methods 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Abstract
本发明一种晶片级测试电路板的制作方式，是于印刷电路板上定义出类似晶片中集成电路芯片分布的多个容置区，于各容置区上延伸布设多条导线至外围对应的探测区上，于各导线上对应于探测区设至少一测试焊点，对应于容置区设至少一凸块焊点，将经过芯片尺寸封装制作工艺之后的各电子组件设于容置区上，使各电子组件的导电凸块电性连接凸块焊点，即可以探针卡的探针接触各测试焊点，如同晶片级测试方式般对各电子组件快速的完成电测。
The present invention provides a method for manufacturing a wafer-level test circuit board, which is to define multiple accommodation areas similar to the distribution of integrated circuit chips in a wafer on a printed circuit board, extend multiple wires on each accommodation area to a corresponding detection area on the periphery, set at least one test solder joint on each wire corresponding to the detection area, and set at least one bump solder joint corresponding to the accommodation area, and set each electronic component after the chip size packaging manufacturing process on the accommodation area, so that the conductive bumps of each electronic component are electrically connected to the bump solder joints, that is, the probes of the probe card can contact each test solder joint, and the electrical test of each electronic component can be quickly completed in the same way as the wafer-level test method.
Description
Technical field
The present invention is relevant with the electronic circuit test system, is meant a kind of board structure of circuit of electronic package after the chip size packages manufacture craft being made wafer level test especially.
Background technology
The general makers' module testing of integrated circuit (IC) wafer is the back segment packaging and testing that can divide into after the leading portion wafer sort in manufacture craft stage and the chip module encapsulation, wherein wafer sort is under development improves for a long time, applied wafer level test system can reach the electrical measurement quality of high-level efficiency, pinpoint accuracy, and therefore the production capacity control to the entire wafer manufacture craft stage has splendid benefit; With packaging and testing, wafer-class encapsulation (Wafer Level Package is then arranged, WLP) manufacture craft and chip size packages (Chip Size Package, CSP) electrical measurement after the manufacture craft, certainly the electrical measurement after the wafer-class encapsulation manufacture craft also can place the entire wafer module on the wafer testing apparatus, utilize existing wafer sort program, then can implement the wafer scale module electrical measurement of high-level efficiency, pinpoint accuracy equally; Yet finally be installed in and still be the one chip module in the wafer level structure in the electronic application product, that is wafer after cutting into single component again through the CSP of chip size packages manufacture craft assembly, in fact must do final test to each CSP assembly, could really guarantee the quality of electronic product, even be the made image component of multistage modular engineering, CMOS video sensing chip module as integrated circuit video sensing manufacture craft technology, last each image module is behind encapsulation CSP, also need just calculate the quality test of finishing image module through general back segment packaging and testing (Final testing), so be the remaining mass keyholed back plate of electronic package production to the back segment packaging and testing of CSP assembly.
Test to the CSP assembly commonly used often can only be at single component electrical measurement one by one, perhaps provide special test machine plate and tester table by the testing apparatus supplier, place for a plurality of CSP assemblies, on hardware, finish correct electric connection then, hardware controls manufacture craft program and testing software that the cooperating equipment supplier is special, just can reach single a plurality of CSP assemblies are carried out electrical measurement fast, so extra electric logging equipment not only need expend the cost expenditure, and assembly manufacturing plant itself also can't accurately control the electrical specification of electric logging equipment, often changed the electrical measurement result of CSP assembly reality because of the electrical drift of any electronic component on the electric logging equipment, even if having arbitrary hardware component to break down in the equipment board, also influence the electrical measurement result easily and be judged as the bad of CSP assembly itself and the reduction quality of production for the moment, severe patient more can cause the reimbursement loss of volume production assembly, so assembly manufacturing plant for the high precision electronic package of self manufacture technology, is difficult to accomplish effective omnidistance keyholed back plate in fact on the electrical measurement program.
Summary of the invention
Therefore, fundamental purpose of the present invention is the production method that is to provide a kind of wafer level testing circuit board, its test circuit plate structure of making can cooperate wafer level test equipment that the assembly after the chip size packages manufacture craft is carried out the wafer scale electrical measurement, reaches the electrical measurement quality keyholed back plate of high-level efficiency and pinpoint accuracy.
Take off purpose for before reaching, the production method of a kind of wafer level testing circuit board provided by the present invention includes the following step of making:.
A. prepare a plurality of electronic packages, these electronic packages are that integrated circuit (IC) wafer is through chip size packages (Chip Size Package, CSP) the modularization package assembling after the manufacture craft, on it and a plurality of conductive projections are arranged, be connected medium as what each integrated circuit (IC) chip and external circuitry electrically conducted;
B. prepare at least one printed circuit board (PCB) (Printed Circuit Board, PCB), the size shape that is equivalent to the said integrated circuit wafer, on this printed circuit board (PCB), define a plurality of disposal areas that integrated circuit (IC) chip distributes in the similar wafer, this disposal area a peripheral and detecting area is arranged respectively, respectively this disposal area is equivalent to respectively this electronic package size;
C. lay many leads to peripheral this corresponding detecting area in extending on this disposal area respectively, in this disposal area respectively an end points of this lead with the conductive projection of this electronic package respectively corresponding graph position is arranged;
D. in respectively establishing at least one test solder joint corresponding to this detecting area on this lead, establish at least one projection solder joint (bump pad) corresponding to this disposal area, these test solder joints and projection solder joint are the metal material of tool electric conductivity, and therefore respectively the test solder joint is somebody's turn to do in the corresponding electric connection one of this projection solder joint;
E. respectively this electronic package is located on this disposal area, and making respectively, the conductive projection of this electronic package electrically connects this projection solder joint.
Therefore after placing this testing circuit board on the wafer sort pedestal, can utilize the wafer level test equipment of general wafer fabrication operation stage, get all the required test condition of respectively this chip testing and wafer sort probe ready, probe with probe contacts this test solder joint then, can be as this electronic package respectively being finished electrical measurement fast as the wafer level test mode.
Description of drawings
Fig. 1 is the unitized construction synoptic diagram that the present invention's first preferred embodiment is provided;
Fig. 2 is that above-mentioned first preferred embodiment provides the respectively structural representation of this electronic package;
Fig. 3 is that above-mentioned first preferred embodiment provides the respectively synoptic diagram of this printed circuit board (PCB);
Fig. 4 is that above-mentioned first preferred embodiment provides the local circuit of this circuit layer of lower floor to lay synoptic diagram;
Fig. 5 is the partial structurtes sectional view that above-mentioned first preferred embodiment provides this circuit layer of upper strata;
Fig. 6 is the partial structurtes schematic perspective view of above-mentioned first this fixed bed that preferred embodiment provides;
Fig. 7 is the exploded perspective view of above-mentioned first this testing circuit board that preferred embodiment provides;
Fig. 8 is the partial structurtes sectional view of the present invention's second this testing circuit board that preferred embodiment provides;
Fig. 9 is the partial structurtes sectional view of the present invention's the 3rd this testing circuit board that preferred embodiment provides.
Embodiment
Below, cooperate some accompanying drawings to enumerate a preferred embodiment now, in order to be described further as follows to composition member of the present invention and effect:
See also Fig. 1 to a testing circuit board 1 that Figure 7 shows that first preferred embodiment provided by the present invention, can make wafer level test to a plurality of electronic packages 10 of module package, these electronic packages 10 that present embodiment exemplified are for making integrated circuit (IC) wafer process chip size packages (the Chip Size Package of each video sensing chip 101, CSP) the modularization package assembling after the manufacture craft, with reference to Fig. 2, on it and a plurality of conductive projections 102 are arranged, be connected medium as what each video sensing chip 101 and external circuitry electrically conducted; Below be to do further to describe at the step of making of this testing circuit board 1:
A. see also as shown in Figure 3, prepared three printed circuit board (PCB)s (Printed CircuitBoard, PCB) 20,30,40, the size that is equivalent to above-mentioned wafer, in respectively defining a plurality of disposal areas 201,301,401 that integrated circuit (IC) chip distributes in the similar wafer on this printed circuit board (PCB) 20,30,40, the peripheral both sides of this disposal area 201,301,401 an and detecting area 202,302,402 is arranged respectively, respectively this disposal area 201,301,401 is equivalent to above-mentioned respectively these electronic package 10 sizes;
B. see also as shown in Figure 4, in a upper surface 203 correspondences of this printed circuit board (PCB) 20 respectively the periphery of this disposal area 201 extend and lay many leads 21 to this detecting area 202, in this disposal area 201 respectively an end points 211 of this lead 21 with the conductive projection 102 of this electronic package 10 respectively corresponding graph position is arranged, in this detecting area 202 respectively 212 of another end points of this lead 21 be regular array and distribute, therefore form the surface and have the circuit layer 200 that circuit pattern is laid;
C. see also as shown in Figure 5, corresponding respectively this two end points 211 of this lead 21 on this printed circuit board (PCB) 30,212 are respectively equipped with a through hole 31,32, upper surface 303 from this printed circuit board (PCB) 30 is through to its lower surface 304, this through hole 31 respectively, 32 hole wall 310,320 are provided with the metal material of tool electric conductivity, therefore form each lead 33 of longitudinal extension respectively, 34, a projection solder joint (bump pad) 35 is respectively established at respectively these lead 33 two ends that should disposal area 301, a test solder joint 36 is respectively established at respectively these lead 33 two ends that should detecting area 302, these projection solder joints 35 and test solder joint 36 are the metal material of tool electric conductivity, therefore are formed with a circuit layer 300 of longitudinal circuit conducting function;
D. see also as shown in Figure 6, given a farfetched interpretation out in respectively this disposal area 401 of this printed circuit board (PCB) 40 and this electronic package 10 sizable opens 41, and on this opens this detecting areas 402 of 41 both sides, give a farfetched interpretation out symmetrical each one open 42, these openings 42 promptly are equivalent to the block that is provided with to these test solder joints 36 on should circuit layer 300, therefore form the fixed bed 400 with most insulating spaces;
E. see also as shown in Figure 7, this circuit layer 300 is repeatedly placed this circuit layer 200, make respectively this lead 33,34 in this circuit layer 300 respectively at lower surface 304 and corresponding respectively these end points 211,212 electric connections of this lead 21, and this fixed bed 400 repeatedly placed on this circuit layer 300, make these openings 41,42 can distinguish these projection solder joints 35 and the test solder joint 36 of corresponding exposed upper surface 303;
F. respectively this electronic package 10 is located in this opening 41, and making respectively, the conductive projection 102 of this electronic package 10 electrically connects these projection solder joints 35.
Therefore this testing circuit board 1 promptly can be fixed these electronic packages 10 by this fixed bed 400, and make the lead 33 of the conductive projection 102 of this electronic package 10 respectively by this circuit layer 300, the lead 21 of this circuit layer 200 and the lead 34 of this circuit layer 300 electrically conduct to respectively this test solder joint 36 of this circuit layer 300 upper surfaces 303, after placing this testing circuit board 1 on the wafer sort pedestal, can utilize the wafer level test equipment of general wafer fabrication operation stage, get all the respectively required testing light source of these video sensing chip 101 tests ready, electrical measurement program and wafer sort probe, probe with probe contacts this test solder joint 36 then, can be as this video sensing chip 101 respectively being finished electrical measurement fast as the wafer level test mode; In addition owing to respectively make and form electric connection can reach contact float between the conductive projection 102 of this electronic package 10 and the projection solder joint 35, therefore can on this fixed bed 400, take out after these electronic packages 10 are finished the electrical measurement program, and then displacement go up other can with the electronic package of these projection solder joint 35 corresponding electric connections, to make same similarly wafer level test, so respectively do not limit the CSP modular assembly that is provided with as above-mentioned video sensing chip 101 in this opening 41, certainly any have the module package assembly that conductive projection 102 is provided with all can manufacturing process steps principle provided by the present invention, is formed with the testing circuit board of wafer level test function.
What deserves to be mentioned is, except can by respectively this opening 41 of this fixed bed 400 as with electronic package 10 between the supplementary structure that engages of contraposition, the present invention also provides a testing circuit board 2 of second preferred embodiment as shown in Figure 8, compare to the foregoing description, being positioned at respectively, this opening 41 more is provided with a binding element 43, more firm electric connection between the conductive projection 102 of these electronic packages 10 and the projection solder joint 35 can be provided, do further to describe at this binding element 43 and the structure set-up mode of finishing this testing circuit board 2 with next:
After this circuit layer 300 of above-mentioned first preferred embodiment forms, prior to coating one deck anisotropy conductive film (Anisotropic conductive film on this circuit layer 300, ACF), anisotropy conductive material for the tool tackness, only can form effectively forward and electrically conduct in thin film planar, then remove these disposal areas 301 conductive film material at position in addition again, therefore only on these projection solder joints 35, keep somewhere this anisotropy conductive film is arranged, so form corresponding to this set binding element 43 of these disposal areas 301, just this fixed bed 400 is repeatedly placed on this circuit layer 300 afterwards, make respectively to have this binding element 43 in this opening 41 then same exposed these test solder joints 36 of respectively this opening 42 of these detecting areas 302.
Therefore this binding element 43 can provide the respectively then property of this electronic package 10 and this circuit layer 300 of increase, does not electrically conduct mutually between vertical conductive characteristic of anisotropy conductive film does not also cause each conductive projection 102 of this electronic package 10 respectively simultaneously; The mode of making as for this binding element 43 is not limited to the mode that more inessential block is removed as above-mentioned elder generation comprehensive coating one deck anisotropy conductive film certainly, and can be after this fixed bed 400 is repeatedly put this circuit layer 300, again in respectively being coated with one deck anisotropy conductive film in this opening 41, can form this binding element 43, the effect of same attainable cost invention with same structure and function; Even if the respectively effect of this electronic package 10 is sticked together in single only consideration, also these binding element 43 employed anisotropy conductive materials can be substituted by the aqueous adhesive agent with good insulation characteristic, therefore when respectively this electronic package 10 is located on this disposal area 301, can make the effect that respectively reaches electric connection between this conductive projection 102 and projection solder joint 35 as long as exert pressure a little, the effect that same attainable cost is invented.
Other sees also as shown in Figure 9, testing circuit board 3 for the 3rd preferred embodiment provided by the present invention, itself and above-mentioned second preferred embodiment provide the difference of this testing circuit board 2 to be, this testing circuit board 3 is for dispensing the fixed bed 400 of this testing circuit board 2, be because the foregoing description provides the effect of this fixed bed 400 to be mainly when conveniently respectively this electronic package 10 is in inserting this opening 41, can assist between each conductive projection 102 and each the projection solder joint 35 and reach contraposition accurately, if have the characteristic of sticking together effect with this binding element 43, setting even without fixed bed, as long as will be respectively when this electronic package 10 is arranged on each disposal area 301, through close aligning instrument each conductive projection 102 is aimed at each projection solder joint 35, the effect of same attainable cost invention.
The above only is a preferable possible embodiments of the present invention, changes so use the equivalent structure that instructions of the present invention and claims do such as, ought to be included within the claim protection domain of the present invention.
Claims (9)
1. the manufacture method of a wafer level testing circuit board is made wafer level test by this testing circuit board to the integrated circuit (IC) chip of module package, it is characterized in that, includes following making step:
A. prepare a plurality of electronic packages, these electronic packages are the modularization package assembling behind the integrated circuit (IC) wafer process chip size packages processing procedure, and respectively this electronic package has a plurality of conductive projections;
B. prepare at least one printed circuit board (PCB), the size shape that is equivalent to the said integrated circuit wafer, on this printed circuit board (PCB), define a plurality of disposal areas that integrated circuit (IC) chip distributes in the similar wafer, this disposal area a peripheral and detecting area is arranged respectively, survey for the detecting probe contact, respectively this disposal area is equivalent to respectively this electronic package size;
C. in respectively extending on this detecting area of laying the extremely peripheral correspondence of many leads on this disposal area;
D. in respectively establishing at least one test solder joint corresponding to this detecting area on this lead, establish at least one projection solder joint corresponding to this disposal area, these test solder joints and projection solder joint are the metal material of tool electric conductivity, and respectively the corresponding electric connection one of this projection solder joint should be tested solder joint;
E. respectively this electronic package is located on this disposal area, and making respectively, the conductive projection of this electronic package electrically connects this projection solder joint.
2. according to the manufacture method of the described wafer level testing circuit board of claim 1, it is characterized in that, this printed circuit board (PCB) has upper and lower one first circuit layer and a second circuit layer of repeatedly putting mutually, relative a upper surface and a lower surface are respectively arranged, the lower surface of this first circuit layer is to contact with the upper surface of this second circuit layer, these leads are divided into a plurality of first leads and second lead among the step c, these first leads are located at this first circuit layer, and these second leads are located at the upper surface of this second circuit layer.
3. according to the manufacture method of the described wafer level testing circuit board of claim 2, it is characterized in that the laying of these first leads and second lead has more following step:
Extend corresponding to this disposal area respectively in the upper surface of this second circuit layer and to lay respectively this second lead to this detecting area;
Be equipped with a through hole respectively corresponding to the two ends of this second lead respectively on this first circuit layer, run through the upper and lower surface of this first circuit layer, respectively the hole wall of this through hole is provided with respectively this first lead of tool conductive metal material.
4. according to the manufacture method of claim 2 or 3 described wafer level testing circuit boards, it is characterized in that these test solder joints and projection solder joint are located on these first leads in the steps d.
5. according to the manufacture method of the described wafer level testing circuit board of claim 2, it is characterized in that before the steps d, more be provided with a fixed bed in this first circuit layer, this fixed bed has following formation step:
Prepare a circuit board, be equivalent to the size shape of above-mentioned this printed circuit board (PCB), corresponding to this disposal area respectively giving a farfetched interpretation out respectively and sizable one first opening of this electronic package;
Corresponding to this detecting area at least one second opening of giving a farfetched interpretation out, these second openings are promptly corresponding to the position that is provided with of these test solder joints on this printed circuit board (PCB) in this first around openings respectively.
6. according to the manufacture method of the described wafer level testing circuit board of claim 5, it is characterized in that, when this fixed bed is located on this first circuit layer, promptly corresponding exposed these projection solder joints of these first openings, promptly corresponding exposed these test solder joints of these second openings.
7. according to the manufacture method of the described wafer level testing circuit board of claim 1, it is characterized in that, more be provided with a binding element corresponding to these disposal areas on this printed circuit board (PCB), for the material of tool tackness made.
8. according to the manufacture method of the described wafer level testing circuit board of claim 7, it is characterized in that this binding element is that the anisotropy conductive material is made.
9. wafer level testing circuit board can be made wafer level test to the integrated circuit (IC) chip of module package, it is characterized in that, includes:
A plurality of electronic packages, these electronic packages are the modularization package assembling after the integrated circuit (IC) wafer process chip size packages manufacture craft, and respectively this electronic package has a plurality of conductive projections; And,
One printed circuit board (PCB), the size shape that is equivalent to the said integrated circuit wafer, differentiation has a plurality of disposal areas that integrated circuit (IC) chip distributes in a plurality of similar wafers, and be positioned at a respectively detecting area of this periphery, disposal area, respectively this disposal area is equivalent to respectively this electronic package size, respectively this disposal area has this detecting area that many leads extend the extremely peripheral correspondence of laying, respectively this disposal area is provided with a plurality of projection solder joints and electrically connects respectively this lead, respectively this detecting area is provided with a plurality of test solder joints and electrically connects respectively this lead, these electronic packages are located at respectively respectively on this disposal area, and making respectively, the conductive projection of this electronic package electrically connects this projection solder joint.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101451329A CN100507578C (en) | 2006-11-13 | 2006-11-13 | Method for manufacturing wafer-level test circuit board and structure thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006101451329A CN100507578C (en) | 2006-11-13 | 2006-11-13 | Method for manufacturing wafer-level test circuit board and structure thereof |
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| CN101183119A CN101183119A (en) | 2008-05-21 |
| CN100507578C true CN100507578C (en) | 2009-07-01 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102096838A (en) * | 2010-12-21 | 2011-06-15 | 捷德（中国）信息科技有限公司 | Method and device for producing integrated circuit card accordant with standard of mini universal integrated circuit card |
| TWI447414B (en) * | 2012-06-07 | 2014-08-01 | 矽品精密工業股份有限公司 | Test apparatus and test method |
| CN103811298B (en) * | 2012-11-15 | 2016-11-09 | 上海华虹宏力半导体制造有限公司 | Test alignment uses the preparation method of chip |
| CN104659041A (en) * | 2013-11-20 | 2015-05-27 | 硕达科技股份有限公司 | Sensor chip packaging method |
| CN116047246A (en) * | 2021-10-28 | 2023-05-02 | 深圳市江波龙电子股份有限公司 | Test method and test device for electronic device |
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| US20050146013A1 (en) * | 2003-01-17 | 2005-07-07 | Farnworth Warren M. | Wafer-level testing apparatus |
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| CN2528108Y (en) * | 2001-07-23 | 2002-12-25 | 吴志成 | Test equipment for semiconductor package components |
| CN2524372Y (en) * | 2002-02-01 | 2002-12-04 | 威盛电子股份有限公司 | Chip test device |
| US20050146013A1 (en) * | 2003-01-17 | 2005-07-07 | Farnworth Warren M. | Wafer-level testing apparatus |
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