CN100489727C - voltage reference circuit - Google Patents

Abstract

The voltage reference circuit includes a positive temperature coefficient current generator, a negative temperature coefficient current generator, and a first resistor. In the positive temperature coefficient current generator, two transistors are operated in a weak inversion region, and a second resistor is connected in series between the gates of the two transistors. The second resistor generates a positive temperature coefficient current by utilizing the characteristics of the transistor operating in the weak inversion region that is similar to a bipolar transistor. The negative temperature coefficient current generator generates a negative temperature coefficient current by dropping a negative temperature coefficient voltage on the third resistor. The positive temperature coefficient current and the negative temperature coefficient current flow through the first resistor together, thereby generating a stable reference voltage.

Description

voltage reference circuit

technical field

The present invention relates to a voltage reference circuit, and in particular to a voltage reference circuit of a CMOS transistor.

Background technique

FIG. 1 is a graph of parameters related to semiconductor process technology. As the channel length of MOS (metal-oxide-silicon) transistors shrinks, the threshold voltage V _TH of the MOS transistors does not decrease proportionally to the operating voltage V _DD . Therefore, under the condition that the voltage headroom is limited, all analog circuits are faced with how to maintain the original performance of the circuit under the low operating voltage V _DD .

Figure 2 is a circuit diagram of a conventional voltage reference circuit, which uses PMOS transistors MP21 and MP22 biased in the subthreshold region to successfully exchange for a larger voltage space, allowing the circuit to work at a low operating voltage V _DD . The traditional voltage reference circuit includes a current mirror composed of PMOS transistors MP24-MP26, PMOS transistors MP21-MP23, an operational amplifier 201, and resistors R21 and R22. For the convenience of the following description, the node voltages V ₂₁ and V ₂₂ are also indicated. Next, FIG. 2 will be used to illustrate the working principle and disadvantages of the traditional voltage reference circuit.

From the node voltages V ₂₁ and V ₂₂ in FIG. 2 , through the feedback mechanism formed by the operational amplifier 201 and the PMOS transistors MP24 and MP25, the node voltage V ₂₁ is equal to the node voltage V ₂₂ . Therefore, with simple circuit analysis, It can be deduced that the magnitude of the current I ₂₁ flowing through the resistor R ₂₁ is

I ₂₁ ＝(V _SG21 −V _SG22 )/R ₂₁ (1)

The current I ₂₁ is copied to the resistor R ₂₂ through the current mirror, and the output reference voltage V _BG is equal to

V _BG ＝V _SG23 +R ₂₂ /R ₂₁ *(V _SG21 -V _SG22 ) (2)

Since the PMOS transistors MP21 and MP22 are biased in the subcritical region with an area ratio of 1:K, the reference voltage V _BG can be expressed as a current characteristic similar to that of a bipolar junction transistor:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; BG</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; SG</span>}\mathrm{<span\; class="notranslate">\; twenty\; three</span>}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; two</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; twenty\; one</span>}}}<span\; class="notranslate">\; \&CenterDot;</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; K</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Among them, n is the process parameter, and V _T is the thermal voltage. It can be seen from the above formula (3) that the traditional voltage reference circuit uses the negative temperature coefficient voltage V _SG23 to synthesize the positive temperature coefficient voltage V _T to generate a temperature-independent reference voltage V _BG .

However, with the change of the circuit structure, in order to make the PMOS transistors MP21 and MP22 operate in the sub-critical region in the traditional voltage reference circuit, the resistor R21 must adopt a larger resistance value, and the current mirrors M24-M26 may operate in the sub-critical region The predicament of the district. In addition, in the reference voltage V _BG output by the traditional voltage reference circuit, the negative temperature coefficient voltage V _SG23 is not a constant item that is simply related to the negative temperature coefficient, because the negative temperature coefficient voltage V _SG23 is generated by the PMOS transistor MP23, and the bias current is at Under the current proportional to absolute temperature (PTAT), the gate-source voltage and the two input voltages of the operational amplifier 201 (that is, the node voltages V ₂₁ and V ₂₂ ) are too small Under these conditions, the circuit performance of the traditional voltage reference circuit is limited.

Contents of the invention

The purpose of the present invention is to provide a voltage reference circuit to ensure that the circuit can still supply a stable reference voltage with low temperature dependence even under a low operating voltage.

To achieve the above and other objectives, the present invention provides a voltage reference circuit. The positive temperature coefficient current generator is used for generating positive temperature coefficient current. The negative temperature coefficient current generator is used to generate the negative temperature coefficient current. The positive temperature coefficient current and the negative temperature coefficient current flow through the second resistor and are collected into a temperature-independent current, and then a stable reference voltage is output from the second resistor. The positive temperature coefficient current generator includes: a first resistor, a first PMOS transistor, a second PMOS transistor, a positive temperature coefficient current mirror, a first operational amplifier, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor. The first PMOS transistor and the second PMOS transistor are biased in the weak inversion region, so the first resistor connected in series between the gates of the two transistors can use the first PMOS transistor and the second PMOS transistor to approximate a bipolar junction transistor The current characteristic produces a positive temperature coefficient current. The positive temperature coefficient current mirror uses the negative feedback mechanism formed by the first operational amplifier to generate the bias current required by the first PMOS transistor and the second PMOS transistor, and uses another current path to ground provided by the third and fourth resistors , to ensure that the positive temperature coefficient current mirror is maintained in the strong inversion region. The two input voltages of the first operational amplifier are increased to the common-mode input range of the first operational amplifier through the voltage drop of the fifth resistor and the sixth resistor.

The negative temperature coefficient current generator includes: a negative temperature coefficient current mirror, a second operational amplifier, a seventh resistor, a ninth PMOS transistor, and a temperature-independent current source. The temperature-independent current source provides a bias current to the ninth PMOS transistor, so that the gate-source voltage of the ninth PMOS transistor is a voltage purely related to a negative temperature coefficient. The negative temperature coefficient voltage (the gate-source voltage of the ninth PMOS transistor) drops on the seventh resistor through the virtual short-circuit characteristic of the two input terminals of the second operational amplifier, thereby generating a negative temperature coefficient current.

Therefore, in the voltage reference circuit of the present invention, the positive temperature coefficient current and the negative temperature coefficient current are combined into a current with low temperature dependence and then flows through the second resistor, thereby generating a stable reference voltage. Compared with the traditional structure, the positive temperature coefficient current generator therein also allows the circuit to operate at a low operating voltage by changing the connection mode of the first resistor, and also reduces the consumption of the circuit layout area.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments of the present invention will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 is a graph of parameters related to semiconductor process technology.

FIG. 2 is a circuit diagram of a conventional voltage reference circuit.

FIG. 3 is a circuit diagram of a voltage reference circuit according to an embodiment of the invention.

4 to 8 are circuit characteristic curves of the voltage reference circuit according to the present embodiment.

Description of main component marking

201, 311, 312: operational amplifiers

300: Voltage reference circuit

301: Positive temperature coefficient current generator

302: Negative temperature coefficient current generator

304: Positive temperature coefficient current mirror

305: Negative temperature coefficient current mirror

313: Temperature Independent Current Source

R37, R21, R22, R31, R32, R33, R34, R35, R36: resistance

MP21, MP22, MP23, MP24, MP25, MP26, MP31, MP32, MP33, MP34, MP35, MP36, MP37, MP38, MP39: PMOS transistors

Detailed ways

FIG. 3 is a voltage reference circuit according to an embodiment of the present invention, including a positive temperature coefficient current generator 301 , a negative temperature coefficient current generator 302 , and a resistor R37 . The outputs of the positive temperature coefficient generator 301 and the negative temperature coefficient generator 302 are both connected to the ground terminal through the resistor R37. The positive temperature coefficient generator 301 is used to generate the positive temperature coefficient current I _PTC , and the negative temperature coefficient current generator 302 is used to generate the negative temperature coefficient current _INTC . Afterwards _, the two currents I _PTC and _INTC synthesize a temperature-independent current I _TC , which flows through the resistor R37 to form a stable reference voltage V _BG with low temperature dependence.

The positive temperature coefficient current generator 301 includes an operational amplifier 311, a positive temperature coefficient current mirror 304 composed of PMOS transistors MP31-MP34, PMOS transistors MP35 and MP36, and resistors R31-R34. The two input terminals of the operational amplifier 311 are respectively connected to

The drains of the PMOS transistors MP31 and MP32 are electrically connected to the gates of the PMOS transistors MP31 - MP34 at their output terminals. The PMOS transistor MP31 has: a source connected to the operating voltage V _DD ; a drain connected to the resistor R31 ; and a gate connected to the operational amplifier 311 . The PMOS transistor MP32 has: a source connected to the operating voltage V _DD ; a drain connected to the resistor R32 ; and a gate connected to the operational amplifier 311 . The PMOS transistor MP33 has: a source connected to the operating voltage V _DD ; a drain connected to the resistor R35 ; and a gate connected to the operational amplifier 311 . The transistor MP34 has: a source connected to the operating voltage V _DD ; a drain connected to the resistor R37 ; and a gate connected to the operational amplifier 311 . The resistor R31 is connected in series between the drains of the PMOS transistor MP31 and the PMOS transistor MP35 , and the resistor R32 is connected in series between the drains of the PMOS transistor MP32 and the PMOS transistor MP36 . The two resistors R31 and R32 are also connected to the ground terminal through the other two resistors R33 and R34 respectively. Both ends of the resistor R35 are respectively connected to the gates of the PMOS transistors MP35 and MP36. For the convenience of the following description, the node voltages Va and Vb are marked here.

The positive temperature coefficient current generator 301 makes the node voltage Va equal to the node voltage Vb through the feedback mechanism formed by the operational amplifier 311 and the PMOS transistors MP31 and MP32 . In this way, it can be seen that the voltage difference ΔV _SG derived from the voltage drop across the resistor R35 can be expressed as follows:

ΔV _SG =V _SG35 -V _SG36 (4)

The relative current I31 flowing through the resistor R35 can be expressed as follows:

I31＝(V _SG35 -V _SG36 )/R35 (5)

In order to enable the voltage reference circuit to work under the low operating voltage V _DD , the PMOS transistors MP35 and MP36 of this embodiment operate in the subcritical region with an area ratio of 1:K. When the current characteristics of the two transistors MP35 and MP36 are similar to those of bipolar junction transistors, the voltages V _SG35 and V _SG36 can be expressed by the following formulas

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; SG</span>}\mathrm{<span\; class="notranslate">\; 25</span>}}<span\; class="notranslate">\; \&ap;</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; \&CenterDot;</span>\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; 35</span>}}}{{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 35</span>}}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; do</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="36"\; label="V\; SG"\; filenames="C200610065589E00141.png"\; state="\{\{state\}\}">V</figure-callout></span><figure-callout\; id="36"\; label="V\; SG"\; filenames="C200610065589E00141.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; \&ap;</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; TH</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}\mathrm{<span\; class="notranslate">\; 36</span>}}}{{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; W</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; L</span>}<span\; class="notranslate">\; )</span>}_{\mathrm{<span\; class="notranslate">\; 36</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; do</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>$

Where V _TH is the critical voltage, n and I _DO are the process parameters, V _T is the thermal voltage, I _D is the drain current flowing through the MOS transistor, (W/L) ₃₅ is the element width-to-length ratio of the PMOS transistor MP35, ( W/L) ₃₆ is the element width-to-length ratio of the PMOS transistor MP36. Through formulas (4) to (7), it can be further deduced that the current I31 flowing through the resistor R35 is

$\mathrm{<span\; class="notranslate">\; I</span>}\mathrm{<span\; class="notranslate">\; 31</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="35"\; label="R"\; filenames="C200610065589E00141.png"\; state="\{\{state\}\}">R</figure-callout></span>}\mathrm{<span\; class="notranslate">\; 35</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; ln</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; K</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; )</span>$

Since the thermal voltage V _T is a constant term of the positive temperature coefficient, the output current I _PTC formed by replicating the current I31 through the positive temperature coefficient current mirror 304 is a positive temperature coefficient current.

In order to prevent the positive temperature coefficient current mirror 304 from operating in the subcritical region, the positive temperature coefficient current generator 301 uses resistors R33 and R34 to form another current path for the positive temperature coefficient current mirror 304, so that the positive temperature coefficient current mirror 304 can pass through The branch currents I32 and I33 are maintained in a strong inversion region. In addition, two input terminals of the operational amplifier 311 are respectively connected to PMOS transistors MP35 and MP36 through resistors R31 and R32 . The voltage drop across the resistors R31 and R32 will help to increase the two input voltages of the operational amplifier 311 (that is, the node voltages Va and Vb), so that the operational amplifier 311 will not be limited by the common-mode input range in use. consider.

In the voltage reference circuit according to this embodiment, the negative temperature coefficient current generator 302 includes an operational amplifier 312, a temperature-independent current source 313, a negative temperature coefficient current mirror 305 composed of PMOS transistors MP37 and MP38, a PMOS transistor MP39, and Resistor R36. The two input ends of the operational amplifier 312 are respectively connected to the ground through the diode-connected PMOS transistor MP39 and the resistor R36 , and its output is connected to the gates of the PMOS transistors MP37 and MP38 . The temperature independent current source 313 is connected in series between the operating voltage V _DD and the PMOS transistor MP39 . The gate and the drain of the PMOS transistor MP39 are connected to the ground terminal, and the source thereof is connected to the temperature independent current source 313 . The connection relationship of the negative temperature coefficient current mirror 305 is described as follows. The PMOS transistor MP37 has: a source connected to the operating voltage V _DD ; a gate connected to the output terminal of the operational amplifier 312 ; a drain connected to the resistor R37 . The PMOS transistor MP38 has: a source connected to the operating voltage V _DD ; a gate connected to the output terminal of the operational amplifier 312 ; a drain connected to the resistor R36 .

In order to provide the current with negative temperature coefficient, the negative temperature coefficient current generator 302 uses the temperature independent current source 313 to provide the bias current of the PMOS transistor MP39 to generate the voltage V _SG39 only related to the negative temperature coefficient. Utilizing the virtual short-circuit characteristic of the two input terminals of the operational amplifier 312, the voltage V _SG39 is dropped on the resistor R36 to form a current I34 whose magnitude is V _SG39 /R36. Afterwards, the current I34 is replicated by the negative temperature coefficient current mirror 305 , so that the negative temperature coefficient current generator 302 generates a negative temperature coefficient current _INTC .

In order to further understand the voltage reference circuit of this embodiment, FIG. 4 to FIG. 8 mark the circuit characteristics of this embodiment, which will be described one by one below. In FIG. 4 , when the operating voltage V _DD is 1V and the output reference voltage V _BG changes from -40° C. to 125° C. in this embodiment, the variation ΔV _BG of the reference voltage is 2.73 mV. In FIG. 5 , the relationship between the positive temperature coefficient current I _PTC and the negative temperature coefficient current I _NTC is shown when the operating voltage V _DD is 1V and the reference voltage variation ΔV _BG is 2.66 mV. In FIG. 6 , the voltage reference circuit of the present embodiment is marked. Under normal operation, the allowable minimum operating voltage V _DD is about 600 mV. In FIG. 7 , it shows the variation of the reference voltage V _BG with temperature under different operating voltages V _DD (V _DD =0.6V～1.5V) in this embodiment, wherein the reference voltage caused by different operating voltages V _DD The voltage change ΔV _BG was 8.91 mV. Finally, FIG. 8 shows the variation of the reference voltage V _BG under different models (FF, TT, SF, FS, SS) under the variation of process parameters of the voltage reference circuit of this embodiment. These models above are the process technology adopted by the present invention, and the accompanying process changes are considered.

To sum up, the embodiments of the present invention utilize the positive temperature coefficient generator and the negative temperature coefficient generator to generate a stable reference voltage with low dependence on temperature. Compared with the traditional structure, the present invention enables the circuit to work at a low operating voltage by changing the circuit structure of the resistance connection mode, and at the same time reduces the layout area of the circuit and the limitation of the circuit itself on the operational amplifier. The resistance value of the resistor R35 is greatly reduced compared with the conventional technology, so the circuit area of this embodiment can be further reduced.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (8)

1. reference circuits is characterized in that comprising:

The positive temperature coefficient (PTC) current mirror is used for producing mapping electric current and positive temperature coefficient (PTC) electric current, wherein duplicates described mapping electric current to produce described positive temperature coefficient (PTC) electric current;

The negative temperature parameter current mirror is connected in described positive temperature coefficient (PTC) current mirror, is used to produce negative temperature parameter current;

First resistance, described mapping electric current described first resistance of flowing through;

The first transistor has first source electrode that is connected in described positive temperature coefficient (PTC) current mirror; Be connected in the first grid of described first resistance; And first drain electrode that connects earth terminal;

Transistor seconds has second source electrode that is connected in described positive temperature coefficient (PTC) current mirror; Be connected in the second grid of described first resistance; And second drain electrode that is connected in described the first transistor;

Second resistance is connected in described positive temperature coefficient (PTC) current mirror and described negative temperature parameter current current mirror, described positive temperature coefficient (PTC) electric current and described negative temperature parameter current described second resistance of flowing through, and reference voltage is exported from described second resistance;

The 5th resistance is connected between described first source electrode and described earth terminal of described the first transistor;

The 6th resistance is connected between described second source electrode and described earth terminal of described transistor seconds; And

First operational amplifier has first positive input terminal of described second source electrode that is connected in described transistor seconds; Be connected in first negative input end of described first source electrode of described the first transistor; And first output terminal that is connected in described positive temperature coefficient (PTC) current mirror, wherein said positive temperature coefficient (PTC) current mirror is controlled by the bias voltage of first output terminal of described first operational amplifier.

2. reference circuits according to claim 1 is characterized in that described positive temperature coefficient (PTC) electric current current mirror comprises:

The 3rd transistor has: the 3rd source electrode that is connected in power end; The 3rd grid; And the 3rd the drain electrode;

The 4th transistor has: the 4th source electrode that is connected in described power end; Be connected in the 4th grid of the described the 3rd transistorized described the 3rd grid; And the 4th the drain electrode;

The 5th transistor has: the 5th source electrode that is connected in described power end; Be connected in the 5th grid of the described the 3rd transistorized described the 3rd grid; And the 5th drain electrode that is connected in described first resistance; And

The 6th transistor has: the 6th source electrode that is connected in described power end; Be connected in the 6th grid of the described the 3rd transistorized described the 3rd grid; And the 6th drain electrode that is connected in described second resistance.

3. reference circuits according to claim 2 is characterized in that described negative temperature parameter current current mirror comprises:

The 7th transistor has: the 7th source electrode that is connected in described power end; The 7th grid; And the 7th drain electrode that is connected in the described the 6th transistorized described the 6th drain electrode; And

The 8th transistor has: the 8th source electrode that is connected in described power end; Be connected in the 7th grid of the described the 7th transistorized described the 7th grid; And the 8th the drain electrode.

4. reference circuits according to claim 2 is characterized in that also comprising:

The 3rd resistance is connected between described first source electrode of the described the 3rd transistorized described the 3rd drain electrode and described the first transistor; And

The 4th resistance is connected between described second source electrode of the described the 4th transistorized described the 4th drain electrode and described transistor seconds.

5. reference circuits according to claim 2 is characterized in that also comprising the 7th resistance, is connected between the described the 8th transistorized described the 8th drain electrode and the described earth terminal described negative temperature parameter current described the 7th resistance of flowing through.

6. reference circuits according to claim 5 is characterized in that also comprising temperature independent current source, is connected in described power supply, to produce temperature independent current.

7. reference circuits according to claim 6, it is characterized in that also comprising the 9th transistor, have: be connected in the 9th source electrode of described temperature independent current source, and the 9th grid of ground connection and the 9th drain electrode, the described the 9th transistorized grid-source voltage is a negative temperature coefficient voltage.

8. reference circuits according to claim 7 is characterized in that also comprising second operational amplifier, has: second positive input terminal that is connected in the described the 8th transistorized described the 8th drain electrode; Be connected in second negative input end of described temperature independent current source; And second output terminal that is connected in the described the 7th transistorized described the 7th grid and the described the 8th transistorized described the 8th grid; The voltage of described second positive input terminal is described negative temperature coefficient voltage.

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